Unified Coverage Report :: Module :: uart_core

Module : uart_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.49	98.94	99.04			96.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_core	98.98	98.94	99.04			97.96	100.00

---

Module Instance : tb.dut.uart_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.98	98.94	99.04			97.96	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.73	99.70	95.90			99.32	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
intr_hw_rx_break_err	100.00	100.00	100.00			100.00	100.00
intr_hw_rx_frame_err	100.00	100.00	100.00			100.00	100.00
intr_hw_rx_overflow	100.00	100.00	100.00			100.00	100.00
intr_hw_rx_parity_err	100.00	100.00	100.00			100.00	100.00
intr_hw_rx_timeout	100.00	100.00	100.00			100.00	100.00
intr_hw_rx_watermark	100.00	100.00	100.00			100.00	100.00
intr_hw_tx_done	100.00	100.00	100.00			100.00	100.00
intr_hw_tx_empty	94.44	100.00	77.78			100.00	100.00
intr_hw_tx_watermark	94.44	100.00	77.78			100.00	100.00
sync_rx	100.00	100.00				100.00
u_uart_rxfifo	97.22	100.00	88.89			100.00	100.00
u_uart_txfifo	97.22	100.00	88.89			100.00	100.00
uart_rx	100.00	100.00	100.00			100.00
uart_tx	100.00	100.00	100.00			100.00

Line Coverage for Module : uart_core

	Line No.	Total	Covered	Percent
TOTAL		94	93	98.94
CONT_ASSIGN	73	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	105	4	4	100.00
ALWAYS	113	4	4	100.00
ALWAYS	122	7	7	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
ALWAYS	166	4	4	100.00
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	179	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
ALWAYS	215	7	7	100.00
ALWAYS	246	5	5	100.00
CONT_ASSIGN	255	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
ALWAYS	302	4	4	100.00
ALWAYS	314	4	4	100.00
CONT_ASSIGN	322	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
ALWAYS	327	3	3	100.00
ALWAYS	337	6	5	83.33
CONT_ASSIGN	353	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	356	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
ALWAYS	379	5	5	100.00
CONT_ASSIGN	388	1	1	100.00
CONT_ASSIGN	389	1	1	100.00
CONT_ASSIGN	512	1	1	100.00

72                      
73         1/1            assign tx_enable        = reg2hw.ctrl.tx.q;
           Tests:       T1 T2 T3 
74         1/1            assign rx_enable        = reg2hw.ctrl.rx.q;
           Tests:       T1 T2 T3 
75         1/1            assign rxnf_enable      = reg2hw.ctrl.nf.q;
           Tests:       T1 T2 T3 
76         1/1            assign sys_loopback     = reg2hw.ctrl.slpbk.q;
           Tests:       T1 T2 T3 
77         1/1            assign line_loopback    = reg2hw.ctrl.llpbk.q;
           Tests:       T1 T2 T3 
78                      
79         1/1            assign uart_fifo_rxrst  = reg2hw.fifo_ctrl.rxrst.q & reg2hw.fifo_ctrl.rxrst.qe;
           Tests:       T1 T2 T3 
80         1/1            assign uart_fifo_txrst  = reg2hw.fifo_ctrl.txrst.q & reg2hw.fifo_ctrl.txrst.qe;
           Tests:       T1 T2 T3 
81         1/1            assign uart_fifo_rxilvl = reg2hw.fifo_ctrl.rxilvl.q;
           Tests:       T1 T2 T3 
82         1/1            assign uart_fifo_txilvl = reg2hw.fifo_ctrl.txilvl.q;
           Tests:       T1 T2 T3 
83                      
84         1/1            assign ovrd_tx_en       = reg2hw.ovrd.txen.q;
           Tests:       T1 T2 T3 
85         1/1            assign ovrd_tx_val      = reg2hw.ovrd.txval.q;
           Tests:       T1 T2 T3 
86                      
87                        typedef enum logic {
88                          BRK_CHK,
89                          BRK_WAIT
90                        } break_st_e ;
91                      
92                        break_st_e break_st_q;
93                      
94         1/1            assign not_allzero_char = rx_valid & (~event_rx_frame_err | (rx_fifo_data != 8'h0));
           Tests:       T1 T2 T3 
95         1/1            assign allzero_err = event_rx_frame_err & (rx_fifo_data == 8'h0);
           Tests:       T1 T2 T3 
96                      
97                      
98         1/1            assign allzero_cnt_d = (break_st_q == BRK_WAIT || not_allzero_char) ? 5'h0 :
           Tests:       T1 T2 T3 
99                                                //allzero_cnt_q[4] never be 1b without break_st_q as BRK_WAIT
100                                               //allzero_cnt_q[4] ? allzero_cnt_q :
101                                               allzero_err ? allzero_cnt_q + 5'd1 :
102                                               allzero_cnt_q;
103                     
104                       always_ff @(posedge clk_i or negedge rst_ni) begin
105        2/2              if (!rst_ni)        allzero_cnt_q <= '0;
           Tests:       T1 T2 T3  | T1 T2 T3 
106        2/2              else if (rx_enable) allzero_cnt_q <= allzero_cnt_d;
           Tests:       T1 T2 T3  | T1 T2 T3 
                        MISSING_ELSE
107                       end
108                     
109                       // break_err edges in same cycle as event_rx_frame_err edges ; that way the
110                       // reset-on-read works the same way for break and frame error interrupts.
111                     
112                       always_comb begin
113        1/1              unique case (reg2hw.ctrl.rxblvl.q)
           Tests:       T1 T2 T3 
114        1/1                2'h0:    break_err = allzero_cnt_d >= 5'd2;
           Tests:       T1 T2 T3 
115        1/1                2'h1:    break_err = allzero_cnt_d >= 5'd4;
           Tests:       T7 T8 T11 
116        1/1                2'h2:    break_err = allzero_cnt_d >= 5'd8;
           Tests:       T2 T7 T8 
117                           default: break_err = allzero_cnt_d >= 5'd16;
118                         endcase
119                       end
120                     
121                       always_ff @(posedge clk_i or negedge rst_ni) begin
122        2/2              if (!rst_ni) break_st_q <= BRK_CHK;
           Tests:       T1 T2 T3  | T1 T2 T3 
123                         else begin
124        1/1                unique case (break_st_q)
           Tests:       T1 T2 T3 
125                             BRK_CHK: begin
126        2/2                    if (event_rx_break_err) break_st_q <= BRK_WAIT;
           Tests:       T1 T2 T3  | T21 T22 T24 
                        MISSING_ELSE
127                             end
128                     
129                             BRK_WAIT: begin
130        2/2                    if (rx_in) break_st_q <= BRK_CHK;
           Tests:       T21 T22 T24  | T21 T22 T24 
                        MISSING_ELSE
131                             end
132                     
133                             default: begin
134                               break_st_q <= BRK_CHK;
135                             end
136                           endcase
137                         end
138                       end
139                     
140        1/1            assign hw2reg.val.d  = rx_val_q;
           Tests:       T1 T2 T3 
141                     
142        1/1            assign hw2reg.rdata.d = uart_rdata;
           Tests:       T1 T2 T3 
143                     
144        1/1            assign hw2reg.status.rxempty.d     = ~rx_fifo_rvalid;
           Tests:       T1 T2 T3 
145        1/1            assign hw2reg.status.rxidle.d      = rx_uart_idle;
           Tests:       T1 T2 T3 
146        1/1            assign hw2reg.status.txidle.d      = tx_uart_idle & ~tx_fifo_rvalid;
           Tests:       T1 T2 T3 
147        1/1            assign hw2reg.status.txempty.d     = ~tx_fifo_rvalid;
           Tests:       T1 T2 T3 
148        1/1            assign hw2reg.status.rxfull.d      = ~rx_fifo_wready;
           Tests:       T1 T2 T3 
149        1/1            assign hw2reg.status.txfull.d      = ~tx_fifo_wready;
           Tests:       T1 T2 T3 
150                     
151        1/1            assign hw2reg.fifo_status.txlvl.d  = 8'(tx_fifo_depth);
           Tests:       T1 T2 T3 
152        1/1            assign hw2reg.fifo_status.rxlvl.d  = 8'(rx_fifo_depth);
           Tests:       T1 T2 T3 
153                     
154                       // resets are self-clearing, so need to update FIFO_CTRL
155                       assign hw2reg.fifo_ctrl.rxilvl.de = 1'b0;
156                       assign hw2reg.fifo_ctrl.rxilvl.d  = 3'h0;
157                       assign hw2reg.fifo_ctrl.txilvl.de = 1'b0;
158                       assign hw2reg.fifo_ctrl.txilvl.d  = 3'h0;
159                     
160                       //              NCO 16x Baud Generator
161                       // output clock rate is:
162                       //      Fin * (NCO/2**NcoWidth)
163                       logic   [NcoWidth:0]     nco_sum_q; // extra bit to get the carry
164                     
165                       always_ff @(posedge clk_i or negedge rst_ni) begin
166        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
167        1/1                nco_sum_q <= 17'h0;
           Tests:       T1 T2 T3 
168        1/1              end else if (tx_enable || rx_enable) begin
           Tests:       T1 T2 T3 
169        1/1                nco_sum_q <= {1'b0,nco_sum_q[NcoWidth-1:0]} + {1'b0,reg2hw.ctrl.nco.q[NcoWidth-1:0]};
           Tests:       T1 T2 T3 
170                         end
                        MISSING_ELSE
171                       end
172                     
173        1/1            assign tick_baud_x16 = nco_sum_q[16];
           Tests:       T1 T2 T3 
174                     
175                       //////////////
176                       // TX Logic //
177                       //////////////
178                     
179        1/1            assign tx_fifo_rready = tx_uart_idle & tx_fifo_rvalid & tx_enable;
           Tests:       T1 T2 T3 
180                     
181                       prim_fifo_sync #(
182                         .Width   (8),
183                         .Pass    (1'b0),
184                         .Depth   (TxFifoDepth)
185                       ) u_uart_txfifo (
186                         .clk_i,
187                         .rst_ni,
188                         .clr_i   (uart_fifo_txrst),
189                         .wvalid_i(reg2hw.wdata.qe),
190                         .wready_o(tx_fifo_wready),
191                         .wdata_i (reg2hw.wdata.q),
192                         .depth_o (tx_fifo_depth),
193                         .full_o (),
194                         .rvalid_o(tx_fifo_rvalid),
195                         .rready_i(tx_fifo_rready),
196                         .rdata_o (tx_fifo_data),
197                         .err_o   ()
198                       );
199                     
200                       uart_tx uart_tx (
201                         .clk_i,
202                         .rst_ni,
203                         .tx_enable,
204                         .tick_baud_x16,
205                         .parity_enable  (reg2hw.ctrl.parity_en.q),
206                         .wr             (tx_fifo_rready),
207                         .wr_parity      ((^tx_fifo_data) ^ reg2hw.ctrl.parity_odd.q),
208                         .wr_data        (tx_fifo_data),
209                         .idle           (tx_uart_idle),
210                         .tx             (tx_out)
211                       );
212                     
213        1/1            assign tx = line_loopback ? rx : tx_out_q ;
           Tests:       T1 T2 T3 
214                       always_ff @(posedge clk_i or negedge rst_ni) begin
215        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
216        1/1                tx_out_q <= 1'b1;
           Tests:       T1 T2 T3 
217        1/1              end else if (ovrd_tx_en) begin
           Tests:       T1 T2 T3 
218        1/1                tx_out_q <= ovrd_tx_val ;
           Tests:       T4 T16 T20 
219        1/1              end else if (sys_loopback) begin
           Tests:       T1 T2 T3 
220        1/1                tx_out_q <= 1'b1;
           Tests:       T7 T15 T25 
221                         end else begin
222        1/1                tx_out_q <= tx_out;
           Tests:       T1 T2 T3 
223                         end
224                       end
225                     
226                       //////////////
227                       // RX Logic //
228                       //////////////
229                     
230                       //      sync the incoming data
231                       prim_flop_2sync #(
232                         .Width(1),
233                         .ResetValue(1'b1)
234                       ) sync_rx (
235                         .clk_i,
236                         .rst_ni,
237                         .d_i(rx),
238                         .q_o(rx_sync)
239                       );
240                     
241                       // Based on: en.wikipedia.org/wiki/Repetition_code mentions the use of a majority filter
242                       // in UART to ignore brief noise spikes
243                       logic   rx_sync_q1, rx_sync_q2, rx_in_mx, rx_in_maj;
244                     
245                       always_ff @(posedge clk_i or negedge rst_ni) begin
246        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
247        1/1                rx_sync_q1 <= 1'b1;
           Tests:       T1 T2 T3 
248        1/1                rx_sync_q2 <= 1'b1;
           Tests:       T1 T2 T3 
249                         end else begin
250        1/1                rx_sync_q1 <= rx_sync;
           Tests:       T1 T2 T3 
251        1/1                rx_sync_q2 <= rx_sync_q1;
           Tests:       T1 T2 T3 
252                         end
253                       end
254                     
255        1/1            assign rx_in_maj = (rx_sync    & rx_sync_q1) |
           Tests:       T1 T2 T3 
256                                          (rx_sync    & rx_sync_q2) |
257                                          (rx_sync_q1 & rx_sync_q2);
258        1/1            assign rx_in_mx  = rxnf_enable ? rx_in_maj : rx_sync;
           Tests:       T1 T2 T3 
259                     
260        1/1            assign rx_in =  sys_loopback ? tx_out   :
           Tests:       T1 T2 T3 
261                                       line_loopback ? 1'b1 :
262                                       rx_in_mx;
263                     
264                       uart_rx uart_rx (
265                         .clk_i,
266                         .rst_ni,
267                         .rx_enable,
268                         .tick_baud_x16,
269                         .parity_enable  (reg2hw.ctrl.parity_en.q),
270                         .parity_odd     (reg2hw.ctrl.parity_odd.q),
271                         .tick_baud      (rx_tick_baud),
272                         .rx_valid,
273                         .rx_data        (rx_fifo_data),
274                         .idle           (rx_uart_idle),
275                         .frame_err      (event_rx_frame_err),
276                         .rx             (rx_in),
277                         .rx_parity_err  (event_rx_parity_err)
278                       );
279                     
280        1/1            assign rx_fifo_wvalid = rx_valid & ~event_rx_frame_err & ~event_rx_parity_err;
           Tests:       T1 T2 T3 
281                     
282                       prim_fifo_sync #(
283                         .Width   (8),
284                         .Pass    (1'b0),
285                         .Depth   (RxFifoDepth)
286                       ) u_uart_rxfifo (
287                         .clk_i,
288                         .rst_ni,
289                         .clr_i   (uart_fifo_rxrst),
290                         .wvalid_i(rx_fifo_wvalid),
291                         .wready_o(rx_fifo_wready),
292                         .wdata_i (rx_fifo_data),
293                         .depth_o (rx_fifo_depth),
294                         .full_o (),
295                         .rvalid_o(rx_fifo_rvalid),
296                         .rready_i(reg2hw.rdata.re),
297                         .rdata_o (uart_rdata),
298                         .err_o   ()
299                       );
300                     
301                       always_ff @(posedge clk_i or negedge rst_ni) begin
302        2/2              if (!rst_ni)            rx_val_q <= 16'h0;
           Tests:       T1 T2 T3  | T1 T2 T3 
303        2/2              else if (tick_baud_x16) rx_val_q <= {rx_val_q[14:0], rx_in};
           Tests:       T1 T2 T3  | T1 T2 T3 
                        MISSING_ELSE
304                       end
305                     
306                       ////////////////////////
307                       // Interrupt & Status //
308                       ////////////////////////
309                     
310                       logic [TxFifoDepthW-1:0] tx_watermark_thresh;
311                       always_comb begin
312                         // Create power of two thresholds.
313                         // The threshold saturates at half the FIFO depth.
314        1/1              if (uart_fifo_txilvl >= (TxFifoDepthW-2)) begin
           Tests:       T1 T2 T3 
315        1/1                tx_watermark_thresh = TxFifoDepthW'(TxFifoDepth/2);
           Tests:       T2 T7 T8 
316                         end else begin
317        1/1                tx_watermark_thresh = 1'b1 << uart_fifo_txilvl;
           Tests:       T1 T2 T3 
318                         end
319        1/1              event_tx_watermark = tx_fifo_depth < tx_watermark_thresh;
           Tests:       T1 T2 T3 
320                       end
321                     
322        1/1            assign event_tx_empty = tx_fifo_depth == '0;
           Tests:       T1 T2 T3 
323                     
324        1/1            assign event_tx_done = ~tx_fifo_rvalid & ~tx_uart_idle_q & tx_uart_idle;
           Tests:       T1 T2 T3 
325                     
326                       always_ff @(posedge clk_i or negedge rst_ni) begin
327        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
328        1/1                tx_uart_idle_q       <= 1'b1;
           Tests:       T1 T2 T3 
329                         end else begin
330        1/1                tx_uart_idle_q       <= tx_uart_idle;
           Tests:       T1 T2 T3 
331                         end
332                       end
333                     
334                       logic [RxFifoDepthW-1:0] rx_watermark_thresh;
335                       always_comb begin
336                         // Create power of two thresholds.
337        1/1              if (uart_fifo_rxilvl > (RxFifoDepthW-1)) begin
           Tests:       T1 T2 T3 
338                           // This results in the comparison always returning 0 below because RxFifoDepth can
339                           // encode depths up to 2*RxFifoDepth-1.
340        0/1     ==>        rx_watermark_thresh = {RxFifoDepthW{1'b1}};
341        1/1              end else if (uart_fifo_rxilvl == (RxFifoDepthW-1)) begin
           Tests:       T1 T2 T3 
342                           // The maximum valid threshold threshold is an exception and saturates at RxFifoDepth-2.
343        1/1                rx_watermark_thresh = RxFifoDepthW'(RxFifoDepth-2);
           Tests:       T7 T8 T10 
344                         end else begin
345        1/1                rx_watermark_thresh = 1'b1 << uart_fifo_rxilvl;
           Tests:       T1 T2 T3 
346                         end
347        1/1              event_rx_watermark = rx_fifo_depth >= rx_watermark_thresh;
           Tests:       T1 T2 T3 
348                       end
349                     
350                     
351                     
352                       // rx timeout interrupt
353        1/1            assign uart_rxto_en  = reg2hw.timeout_ctrl.en.q;
           Tests:       T1 T2 T3 
354        1/1            assign uart_rxto_val = reg2hw.timeout_ctrl.val.q;
           Tests:       T1 T2 T3 
355                     
356        1/1            assign rx_fifo_depth_changed = (rx_fifo_depth != rx_fifo_depth_prev_q);
           Tests:       T1 T2 T3 
357                     
358        1/1            assign rx_timeout_count_d =
           Tests:       T1 T2 T3 
359                                   // don't count if timeout feature not enabled ;
360                                   // will never reach timeout val + lower power
361                                   (uart_rxto_en == 1'b0)              ? 24'd0 :
362                                   // reset count if timeout interrupt is set
363                                   event_rx_timeout                    ? 24'd0 :
364                                   // reset count upon change in fifo level: covers both read and receiving a new byte
365                                   rx_fifo_depth_changed               ? 24'd0 :
366                                   // reset count if no bytes are pending
367                                   (rx_fifo_depth == '0)               ? 24'd0 :
368                                   // stop the count at timeout value (this will set the interrupt)
369                                   //   Removed below line as when the timeout reaches the value,
370                                   //   event occured, and timeout value reset to 0h.
371                                   //(rx_timeout_count_q == uart_rxto_val) ? rx_timeout_count_q :
372                                   // increment if at rx baud tick
373                                   rx_tick_baud                        ? (rx_timeout_count_q + 24'd1) :
374                                   rx_timeout_count_q;
375                     
376        1/1            assign event_rx_timeout = (rx_timeout_count_q == uart_rxto_val) & uart_rxto_en;
           Tests:       T1 T2 T3 
377                     
378                       always_ff @(posedge clk_i or negedge rst_ni) begin
379        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
380        1/1                rx_timeout_count_q   <= 24'd0;
           Tests:       T1 T2 T3 
381        1/1                rx_fifo_depth_prev_q <= '0;
           Tests:       T1 T2 T3 
382                         end else begin
383        1/1                rx_timeout_count_q    <= rx_timeout_count_d;
           Tests:       T1 T2 T3 
384        1/1                rx_fifo_depth_prev_q  <= rx_fifo_depth;
           Tests:       T1 T2 T3 
385                         end
386                       end
387                     
388        1/1            assign event_rx_overflow  = rx_fifo_wvalid & ~rx_fifo_wready;
           Tests:       T1 T2 T3 
389        1/1            assign event_rx_break_err = break_err & (break_st_q == BRK_CHK);
           Tests:       T1 T2 T3 
390                     
391                       // instantiate interrupt hardware primitives
392                     
393                       prim_intr_hw #(.Width(1), .IntrT("Status")) intr_hw_tx_watermark (
394                         .clk_i,
395                         .rst_ni,
396                         .event_intr_i           (event_tx_watermark),
397                         .reg2hw_intr_enable_q_i (reg2hw.intr_enable.tx_watermark.q),
398                         .reg2hw_intr_test_q_i   (reg2hw.intr_test.tx_watermark.q),
399                         .reg2hw_intr_test_qe_i  (reg2hw.intr_test.tx_watermark.qe),
400                         .reg2hw_intr_state_q_i  (reg2hw.intr_state.tx_watermark.q),
401                         .hw2reg_intr_state_de_o (hw2reg.intr_state.tx_watermark.de),
402                         .hw2reg_intr_state_d_o  (hw2reg.intr_state.tx_watermark.d),
403                         .intr_o                 (intr_tx_watermark_o)
404                       );
405                     
406                       prim_intr_hw #(.Width(1), .IntrT("Status")) intr_hw_tx_empty (
407                         .clk_i,
408                         .rst_ni,
409                         .event_intr_i           (event_tx_empty),
410                         .reg2hw_intr_enable_q_i (reg2hw.intr_enable.tx_empty.q),
411                         .reg2hw_intr_test_q_i   (reg2hw.intr_test.tx_empty.q),
412                         .reg2hw_intr_test_qe_i  (reg2hw.intr_test.tx_empty.qe),
413                         .reg2hw_intr_state_q_i  (reg2hw.intr_state.tx_empty.q),
414                         .hw2reg_intr_state_de_o (hw2reg.intr_state.tx_empty.de),
415                         .hw2reg_intr_state_d_o  (hw2reg.intr_state.tx_empty.d),
416                         .intr_o                 (intr_tx_empty_o)
417                       );
418                     
419                       prim_intr_hw #(.Width(1), .IntrT("Status")) intr_hw_rx_watermark (
420                         .clk_i,
421                         .rst_ni,
422                         .event_intr_i           (event_rx_watermark),
423                         .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_watermark.q),
424                         .reg2hw_intr_test_q_i   (reg2hw.intr_test.rx_watermark.q),
425                         .reg2hw_intr_test_qe_i  (reg2hw.intr_test.rx_watermark.qe),
426                         .reg2hw_intr_state_q_i  (reg2hw.intr_state.rx_watermark.q),
427                         .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_watermark.de),
428                         .hw2reg_intr_state_d_o  (hw2reg.intr_state.rx_watermark.d),
429                         .intr_o                 (intr_rx_watermark_o)
430                       );
431                     
432                       prim_intr_hw #(.Width(1)) intr_hw_tx_done (
433                         .clk_i,
434                         .rst_ni,
435                         .event_intr_i           (event_tx_done),
436                         .reg2hw_intr_enable_q_i (reg2hw.intr_enable.tx_done.q),
437                         .reg2hw_intr_test_q_i   (reg2hw.intr_test.tx_done.q),
438                         .reg2hw_intr_test_qe_i  (reg2hw.intr_test.tx_done.qe),
439                         .reg2hw_intr_state_q_i  (reg2hw.intr_state.tx_done.q),
440                         .hw2reg_intr_state_de_o (hw2reg.intr_state.tx_done.de),
441                         .hw2reg_intr_state_d_o  (hw2reg.intr_state.tx_done.d),
442                         .intr_o                 (intr_tx_done_o)
443                       );
444                     
445                       prim_intr_hw #(.Width(1)) intr_hw_rx_overflow (
446                         .clk_i,
447                         .rst_ni,
448                         .event_intr_i           (event_rx_overflow),
449                         .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_overflow.q),
450                         .reg2hw_intr_test_q_i   (reg2hw.intr_test.rx_overflow.q),
451                         .reg2hw_intr_test_qe_i  (reg2hw.intr_test.rx_overflow.qe),
452                         .reg2hw_intr_state_q_i  (reg2hw.intr_state.rx_overflow.q),
453                         .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_overflow.de),
454                         .hw2reg_intr_state_d_o  (hw2reg.intr_state.rx_overflow.d),
455                         .intr_o                 (intr_rx_overflow_o)
456                       );
457                     
458                       prim_intr_hw #(.Width(1)) intr_hw_rx_frame_err (
459                         .clk_i,
460                         .rst_ni,
461                         .event_intr_i           (event_rx_frame_err),
462                         .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_frame_err.q),
463                         .reg2hw_intr_test_q_i   (reg2hw.intr_test.rx_frame_err.q),
464                         .reg2hw_intr_test_qe_i  (reg2hw.intr_test.rx_frame_err.qe),
465                         .reg2hw_intr_state_q_i  (reg2hw.intr_state.rx_frame_err.q),
466                         .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_frame_err.de),
467                         .hw2reg_intr_state_d_o  (hw2reg.intr_state.rx_frame_err.d),
468                         .intr_o                 (intr_rx_frame_err_o)
469                       );
470                     
471                       prim_intr_hw #(.Width(1)) intr_hw_rx_break_err (
472                         .clk_i,
473                         .rst_ni,
474                         .event_intr_i           (event_rx_break_err),
475                         .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_break_err.q),
476                         .reg2hw_intr_test_q_i   (reg2hw.intr_test.rx_break_err.q),
477                         .reg2hw_intr_test_qe_i  (reg2hw.intr_test.rx_break_err.qe),
478                         .reg2hw_intr_state_q_i  (reg2hw.intr_state.rx_break_err.q),
479                         .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_break_err.de),
480                         .hw2reg_intr_state_d_o  (hw2reg.intr_state.rx_break_err.d),
481                         .intr_o                 (intr_rx_break_err_o)
482                       );
483                     
484                       prim_intr_hw #(.Width(1)) intr_hw_rx_timeout (
485                         .clk_i,
486                         .rst_ni,
487                         .event_intr_i           (event_rx_timeout),
488                         .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_timeout.q),
489                         .reg2hw_intr_test_q_i   (reg2hw.intr_test.rx_timeout.q),
490                         .reg2hw_intr_test_qe_i  (reg2hw.intr_test.rx_timeout.qe),
491                         .reg2hw_intr_state_q_i  (reg2hw.intr_state.rx_timeout.q),
492                         .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_timeout.de),
493                         .hw2reg_intr_state_d_o  (hw2reg.intr_state.rx_timeout.d),
494                         .intr_o                 (intr_rx_timeout_o)
495                       );
496                     
497                       prim_intr_hw #(.Width(1)) intr_hw_rx_parity_err (
498                         .clk_i,
499                         .rst_ni,
500                         .event_intr_i           (event_rx_parity_err),
501                         .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_parity_err.q),
502                         .reg2hw_intr_test_q_i   (reg2hw.intr_test.rx_parity_err.q),
503                         .reg2hw_intr_test_qe_i  (reg2hw.intr_test.rx_parity_err.qe),
504                         .reg2hw_intr_state_q_i  (reg2hw.intr_state.rx_parity_err.q),
505                         .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_parity_err.de),
506                         .hw2reg_intr_state_d_o  (hw2reg.intr_state.rx_parity_err.d),
507                         .intr_o                 (intr_rx_parity_err_o)
508                       );
509                     
510                       // unused registers
511                       logic unused_reg;
512        1/1            assign unused_reg = ^reg2hw.alert_test;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : uart_core

	Total	Covered	Percent
Conditions	104	103	99.04
Logical	104	103	99.04
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (reg2hw.fifo_ctrl.rxrst.q & reg2hw.fifo_ctrl.rxrst.qe)
             ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T2,T7,T10
1	1	Covered	T2,T7,T10

 LINE       80
 EXPRESSION (reg2hw.fifo_ctrl.txrst.q & reg2hw.fifo_ctrl.txrst.qe)
             ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T8,T12,T21
1	1	Covered	T8,T12,T21

 LINE       94
 EXPRESSION (rx_valid & (((~event_rx_frame_err)) | (rx_fifo_data != 8'b0)))
             ----1---   -------------------------2------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T24
1	1	Covered	T1,T2,T3

 LINE       94
 SUB-EXPRESSION (((~event_rx_frame_err)) | (rx_fifo_data != 8'b0))
                 -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T24
0	1	Covered	T2,T10,T22
1	0	Covered	T1,T2,T3

 LINE       94
 SUB-EXPRESSION (rx_fifo_data != 8'b0)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       95
 EXPRESSION (event_rx_frame_err & (rx_fifo_data == 8'b0))
             ---------1--------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T22
1	1	Covered	T21,T22,T24

 LINE       95
 SUB-EXPRESSION (rx_fifo_data == 8'b0)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (((break_st_q == BRK_WAIT) || not_allzero_char) ? 5'b0 : (allzero_err ? ((allzero_cnt_q + 5'b1)) : allzero_cnt_q))
             -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 SUB-EXPRESSION ((break_st_q == BRK_WAIT) || not_allzero_char)
                 ------------1-----------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T24

 LINE       98
 SUB-EXPRESSION (break_st_q == BRK_WAIT)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T24

 LINE       98
 SUB-EXPRESSION (allzero_err ? ((allzero_cnt_q + 5'b1)) : allzero_cnt_q)
                 -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T24

 LINE       146
 EXPRESSION (tx_uart_idle & ((~tx_fifo_rvalid)))
             ------1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       168
 EXPRESSION (tx_enable || rx_enable)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T10
1	0	Covered	T8,T11,T12

 LINE       179
 EXPRESSION (tx_uart_idle & tx_fifo_rvalid & tx_enable)
             ------1-----   -------2------   ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T8,T14
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T8,T11,T12
1	1	1	Covered	T1,T3,T4

 LINE       200
 EXPRESSION (((^tx_fifo_data)) ^ reg2hw.ctrl.parity_odd.q)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T7

 LINE       213
 EXPRESSION (line_loopback ? rx : tx_out_q)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T15,T25

 LINE       255
 EXPRESSION ((rx_sync & rx_sync_q1) | (rx_sync & rx_sync_q2) | (rx_sync_q1 & rx_sync_q2))
             -----------1----------   -----------2----------   ------------3------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T3,T4
1	0	0	Covered	T1,T2,T3

 LINE       255
 SUB-EXPRESSION (rx_sync & rx_sync_q1)
                 ---1---   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       255
 SUB-EXPRESSION (rx_sync & rx_sync_q2)
                 ---1---   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       255
 SUB-EXPRESSION (rx_sync_q1 & rx_sync_q2)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       258
 EXPRESSION (rxnf_enable ? rx_in_maj : rx_sync)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       260
 EXPRESSION (sys_loopback ? tx_out : (line_loopback ? 1'b1 : rx_in_mx))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T15,T25

 LINE       260
 SUB-EXPRESSION (line_loopback ? 1'b1 : rx_in_mx)
                 ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T15,T25

 LINE       280
 EXPRESSION (rx_valid & ((~event_rx_frame_err)) & ((~event_rx_parity_err)))
             ----1---   -----------2-----------   ------------3-----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T10,T22
1	1	0	Covered	T10,T21,T26
1	1	1	Covered	T1,T3,T4

 LINE       322
 EXPRESSION (tx_fifo_depth == '0)
            ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       324
 EXPRESSION (((~tx_fifo_rvalid)) & ((~tx_uart_idle_q)) & tx_uart_idle)
             ---------1---------   ---------2---------   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T8,T14
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T3,T4
1	1	1	Covered	T1,T3,T4

 LINE       341
 EXPRESSION (uart_fifo_rxilvl == (RxFifoDepthW - 1))
            --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T10

 LINE       356
 EXPRESSION (rx_fifo_depth != rx_fifo_depth_prev_q)
            -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       358
 EXPRESSION 
 Number  Term
      1  (uart_rxto_en == 1'b0) ? 24'b0 : (event_rx_timeout ? 24'b0 : (rx_fifo_depth_changed ? 24'b0 : ((rx_fifo_depth == '0) ? 24'b0 : (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q)))))

-1-	Status	Tests
0	Covered	T2,T7,T8
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (uart_rxto_en == 1'b0)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION 
 Number  Term
      1  event_rx_timeout ? 24'b0 : (rx_fifo_depth_changed ? 24'b0 : ((rx_fifo_depth == '0) ? 24'b0 : (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q))))

-1-	Status	Tests
0	Covered	T2,T7,T8
1	Covered	T8,T11,T12

 LINE       358
 SUB-EXPRESSION (rx_fifo_depth_changed ? 24'b0 : ((rx_fifo_depth == '0) ? 24'b0 : (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q)))
                 ----------1----------

-1-	Status	Tests
0	Covered	T2,T7,T8
1	Covered	T7,T8,T10

 LINE       358
 SUB-EXPRESSION ((rx_fifo_depth == '0) ? 24'b0 : (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q))
                 ----------1----------

-1-	Status	Tests
0	Covered	T7,T8,T10
1	Covered	T2,T7,T8

 LINE       358
 SUB-EXPRESSION (rx_fifo_depth == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T7,T8,T10
1	Covered	T2,T7,T8

 LINE       358
 SUB-EXPRESSION (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q)
                 ------1-----

-1-	Status	Tests
0	Covered	T7,T8,T10
1	Covered	T8,T10,T11

 LINE       376
 EXPRESSION ((rx_timeout_count_q == uart_rxto_val) & uart_rxto_en)
             ------------------1------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T11,T12

 LINE       376
 SUB-EXPRESSION (rx_timeout_count_q == uart_rxto_val)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       388
 EXPRESSION (rx_fifo_wvalid & ((~rx_fifo_wready)))
             -------1------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T17,T18,T19

 LINE       389
 EXPRESSION (break_err & (break_st_q == BRK_CHK))
             ----1----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T21,T22,T24

 LINE       389
 SUB-EXPRESSION (break_st_q == BRK_CHK)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : uart_core

	Line No.	Total	Covered	Percent
Branches		50	48	96.00
TERNARY	98	3	3	100.00
TERNARY	213	2	2	100.00
TERNARY	258	2	2	100.00
TERNARY	260	3	3	100.00
TERNARY	358	6	6	100.00
IF	105	3	3	100.00
CASE	113	4	4	100.00
IF	122	6	5	83.33
IF	166	3	3	100.00
IF	215	4	4	100.00
IF	246	2	2	100.00
IF	302	3	3	100.00
IF	314	2	2	100.00
IF	327	2	2	100.00
IF	337	3	2	66.67
IF	379	2	2	100.00

98           assign allzero_cnt_d = (break_st_q == BRK_WAIT || not_allzero_char) ? 5'h0 :
                                                                                 -1-  
                                                                                 ==>  
99                                   //allzero_cnt_q[4] never be 1b without break_st_q as BRK_WAIT
                                                                                                  
100                                  //allzero_cnt_q[4] ? allzero_cnt_q :
                                                                         
101                                  allzero_err ? allzero_cnt_q + 5'd1 :
                                                 -2-  
                                                 ==>  
                                                 ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T21,T22,T24
0	0	Covered	T1,T2,T3

213          assign tx = line_loopback ? rx : tx_out_q ;
                                       -1-  
                                       ==>  
                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T7,T15,T25
0	Covered	T1,T2,T3

258          assign rx_in_mx  = rxnf_enable ? rx_in_maj : rx_sync;
                                            -1-  
                                            ==>  
                                            ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

260          assign rx_in =  sys_loopback ? tx_out   :
                                          -1-  
                                          ==>  
261                          line_loopback ? 1'b1 :
                                           -2-  
                                           ==>  
                                           ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T15,T25
0	1	Covered	T7,T15,T25
0	0	Covered	T1,T2,T3

358          assign rx_timeout_count_d =
                                        
359                      // don't count if timeout feature not enabled ;
                                                                        
360                      // will never reach timeout val + lower power
                                                                      
361                      (uart_rxto_en == 1'b0)              ? 24'd0 :
                                                             -1-  
                                                             ==>  
362                      // reset count if timeout interrupt is set
                                                                   
363                      event_rx_timeout                    ? 24'd0 :
                                                             -2-  
                                                             ==>  
364                      // reset count upon change in fifo level: covers both read and receiving a new byte
                                                                                                            
365                      rx_fifo_depth_changed               ? 24'd0 :
                                                             -3-  
                                                             ==>  
366                      // reset count if no bytes are pending
                                                               
367                      (rx_fifo_depth == '0)               ? 24'd0 :
                                                             -4-  
                                                             ==>  
368                      // stop the count at timeout value (this will set the interrupt)
                                                                                         
369                      //   Removed below line as when the timeout reaches the value,
                                                                                       
370                      //   event occured, and timeout value reset to 0h.
                                                                           
371                      //(rx_timeout_count_q == uart_rxto_val) ? rx_timeout_count_q :
                                                                                       
372                      // increment if at rx baud tick
                                                        
373                      rx_tick_baud                        ? (rx_timeout_count_q + 24'd1) :
                                                             -5-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T8,T11,T12
0	0	1	-	-	Covered	T7,T8,T10
0	0	0	1	-	Covered	T2,T7,T8
0	0	0	0	1	Covered	T8,T10,T11
0	0	0	0	0	Covered	T7,T8,T10

105            if (!rst_ni)        allzero_cnt_q <= '0;
               -1-  
               ==>
106            else if (rx_enable) allzero_cnt_q <= allzero_cnt_d;
                    -2-  
               ==>
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

113            unique case (reg2hw.ctrl.rxblvl.q)
                      -1-  
114              2'h0:    break_err = allzero_cnt_d >= 5'd2;
                 ==>
115              2'h1:    break_err = allzero_cnt_d >= 5'd4;
                 ==>
116              2'h2:    break_err = allzero_cnt_d >= 5'd8;
                 ==>
117              default: break_err = allzero_cnt_d >= 5'd16;
                 ==>

Branches:

-1-	Status	Tests
2'h0	Covered	T1,T2,T3
2'h1	Covered	T7,T8,T11
2'h2	Covered	T2,T7,T8
default	Covered	T7,T8,T10

122            if (!rst_ni) break_st_q <= BRK_CHK;
               -1-  
               ==>
123            else begin
124              unique case (break_st_q)
                        -2-  
125                BRK_CHK: begin
126                  if (event_rx_break_err) break_st_q <= BRK_WAIT;
                     -3-  
                     ==>
                     MISSING_ELSE
                     ==>
127                end
128        
129                BRK_WAIT: begin
130                  if (rx_in) break_st_q <= BRK_CHK;
                     -4-  
                     ==>
                     MISSING_ELSE
                     ==>
131                end
132        
133                default: begin
134                  break_st_q <= BRK_CHK;
                     ==>

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	BRK_CHK	1	-	Covered	T21,T22,T24
0	BRK_CHK	0	-	Covered	T1,T2,T3
0	BRK_WAIT	-	1	Covered	T21,T22,T24
0	BRK_WAIT	-	0	Covered	T21,T22,T24
0	default	-	-	Not Covered

166            if (!rst_ni) begin
               -1-  
167              nco_sum_q <= 17'h0;
                 ==>
168            end else if (tx_enable || rx_enable) begin
                        -2-  
169              nco_sum_q <= {1'b0,nco_sum_q[NcoWidth-1:0]} + {1'b0,reg2hw.ctrl.nco.q[NcoWidth-1:0]};
                 ==>
170            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

215            if (!rst_ni) begin
               -1-  
216              tx_out_q <= 1'b1;
                 ==>
217            end else if (ovrd_tx_en) begin
                        -2-  
218              tx_out_q <= ovrd_tx_val ;
                 ==>
219            end else if (sys_loopback) begin
                        -3-  
220              tx_out_q <= 1'b1;
                 ==>
221            end else begin
222              tx_out_q <= tx_out;
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T16,T20
0	0	1	Covered	T7,T15,T25
0	0	0	Covered	T1,T2,T3

246            if (!rst_ni) begin
               -1-  
247              rx_sync_q1 <= 1'b1;
                 ==>
248              rx_sync_q2 <= 1'b1;
249            end else begin
250              rx_sync_q1 <= rx_sync;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

302            if (!rst_ni)            rx_val_q <= 16'h0;
               -1-  
               ==>
303            else if (tick_baud_x16) rx_val_q <= {rx_val_q[14:0], rx_in};
                    -2-  
               ==>
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

314            if (uart_fifo_txilvl >= (TxFifoDepthW-2)) begin
               -1-                            
315              tx_watermark_thresh = TxFifoDepthW'(TxFifoDepth/2);
                 ==>
316            end else begin
317              tx_watermark_thresh = 1'b1 << uart_fifo_txilvl;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T8
0	Covered	T1,T2,T3

327            if (!rst_ni) begin
               -1-  
328              tx_uart_idle_q       <= 1'b1;
                 ==>
329            end else begin
330              tx_uart_idle_q       <= tx_uart_idle;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

337            if (uart_fifo_rxilvl > (RxFifoDepthW-1)) begin
               -1-                           
338              // This results in the comparison always returning 0 below because RxFifoDepth can
339              // encode depths up to 2*RxFifoDepth-1.
340              rx_watermark_thresh = {RxFifoDepthW{1'b1}};
                 ==>
341            end else if (uart_fifo_rxilvl == (RxFifoDepthW-1)) begin
                        -2-                            
342              // The maximum valid threshold threshold is an exception and saturates at RxFifoDepth-2.
343              rx_watermark_thresh = RxFifoDepthW'(RxFifoDepth-2);
                 ==>
344            end else begin
345              rx_watermark_thresh = 1'b1 << uart_fifo_rxilvl;
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T7,T8,T10
0	0	Covered	T1,T2,T3

379            if (!rst_ni) begin
               -1-  
380              rx_timeout_count_q   <= 24'd0;
                 ==>
381              rx_fifo_depth_prev_q <= '0;
382            end else begin
383              rx_timeout_count_q    <= rx_timeout_count_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : uart_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RxFifoDepth_A	1151	1151	0	0
TxFifoDepth_A	1151	1151	0	0

RxFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

TxFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.uart_core

	Line No.	Total	Covered	Percent
TOTAL		94	93	98.94
CONT_ASSIGN	73	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	105	4	4	100.00
ALWAYS	113	4	4	100.00
ALWAYS	122	7	7	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
ALWAYS	166	4	4	100.00
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	179	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
ALWAYS	215	7	7	100.00
ALWAYS	246	5	5	100.00
CONT_ASSIGN	255	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
ALWAYS	302	4	4	100.00
ALWAYS	314	4	4	100.00
CONT_ASSIGN	322	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
ALWAYS	327	3	3	100.00
ALWAYS	337	6	5	83.33
CONT_ASSIGN	353	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	356	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
ALWAYS	379	5	5	100.00
CONT_ASSIGN	388	1	1	100.00
CONT_ASSIGN	389	1	1	100.00
CONT_ASSIGN	512	1	1	100.00

72                      
73         1/1            assign tx_enable        = reg2hw.ctrl.tx.q;
           Tests:       T1 T2 T3 
74         1/1            assign rx_enable        = reg2hw.ctrl.rx.q;
           Tests:       T1 T2 T3 
75         1/1            assign rxnf_enable      = reg2hw.ctrl.nf.q;
           Tests:       T1 T2 T3 
76         1/1            assign sys_loopback     = reg2hw.ctrl.slpbk.q;
           Tests:       T1 T2 T3 
77         1/1            assign line_loopback    = reg2hw.ctrl.llpbk.q;
           Tests:       T1 T2 T3 
78                      
79         1/1            assign uart_fifo_rxrst  = reg2hw.fifo_ctrl.rxrst.q & reg2hw.fifo_ctrl.rxrst.qe;
           Tests:       T1 T2 T3 
80         1/1            assign uart_fifo_txrst  = reg2hw.fifo_ctrl.txrst.q & reg2hw.fifo_ctrl.txrst.qe;
           Tests:       T1 T2 T3 
81         1/1            assign uart_fifo_rxilvl = reg2hw.fifo_ctrl.rxilvl.q;
           Tests:       T1 T2 T3 
82         1/1            assign uart_fifo_txilvl = reg2hw.fifo_ctrl.txilvl.q;
           Tests:       T1 T2 T3 
83                      
84         1/1            assign ovrd_tx_en       = reg2hw.ovrd.txen.q;
           Tests:       T1 T2 T3 
85         1/1            assign ovrd_tx_val      = reg2hw.ovrd.txval.q;
           Tests:       T1 T2 T3 
86                      
87                        typedef enum logic {
88                          BRK_CHK,
89                          BRK_WAIT
90                        } break_st_e ;
91                      
92                        break_st_e break_st_q;
93                      
94         1/1            assign not_allzero_char = rx_valid & (~event_rx_frame_err | (rx_fifo_data != 8'h0));
           Tests:       T1 T2 T3 
95         1/1            assign allzero_err = event_rx_frame_err & (rx_fifo_data == 8'h0);
           Tests:       T1 T2 T3 
96                      
97                      
98         1/1            assign allzero_cnt_d = (break_st_q == BRK_WAIT || not_allzero_char) ? 5'h0 :
           Tests:       T1 T2 T3 
99                                                //allzero_cnt_q[4] never be 1b without break_st_q as BRK_WAIT
100                                               //allzero_cnt_q[4] ? allzero_cnt_q :
101                                               allzero_err ? allzero_cnt_q + 5'd1 :
102                                               allzero_cnt_q;
103                     
104                       always_ff @(posedge clk_i or negedge rst_ni) begin
105        2/2              if (!rst_ni)        allzero_cnt_q <= '0;
           Tests:       T1 T2 T3  | T1 T2 T3 
106        2/2              else if (rx_enable) allzero_cnt_q <= allzero_cnt_d;
           Tests:       T1 T2 T3  | T1 T2 T3 
                        MISSING_ELSE
107                       end
108                     
109                       // break_err edges in same cycle as event_rx_frame_err edges ; that way the
110                       // reset-on-read works the same way for break and frame error interrupts.
111                     
112                       always_comb begin
113        1/1              unique case (reg2hw.ctrl.rxblvl.q)
           Tests:       T1 T2 T3 
114        1/1                2'h0:    break_err = allzero_cnt_d >= 5'd2;
           Tests:       T1 T2 T3 
115        1/1                2'h1:    break_err = allzero_cnt_d >= 5'd4;
           Tests:       T7 T8 T11 
116        1/1                2'h2:    break_err = allzero_cnt_d >= 5'd8;
           Tests:       T2 T7 T8 
117                           default: break_err = allzero_cnt_d >= 5'd16;
118                         endcase
119                       end
120                     
121                       always_ff @(posedge clk_i or negedge rst_ni) begin
122        2/2              if (!rst_ni) break_st_q <= BRK_CHK;
           Tests:       T1 T2 T3  | T1 T2 T3 
123                         else begin
124        1/1                unique case (break_st_q)
           Tests:       T1 T2 T3 
125                             BRK_CHK: begin
126        2/2                    if (event_rx_break_err) break_st_q <= BRK_WAIT;
           Tests:       T1 T2 T3  | T21 T22 T24 
                        MISSING_ELSE
127                             end
128                     
129                             BRK_WAIT: begin
130        2/2                    if (rx_in) break_st_q <= BRK_CHK;
           Tests:       T21 T22 T24  | T21 T22 T24 
                        MISSING_ELSE
131                             end
132                     
133                             default: begin
134                               break_st_q <= BRK_CHK;
135                             end
136                           endcase
137                         end
138                       end
139                     
140        1/1            assign hw2reg.val.d  = rx_val_q;
           Tests:       T1 T2 T3 
141                     
142        1/1            assign hw2reg.rdata.d = uart_rdata;
           Tests:       T1 T2 T3 
143                     
144        1/1            assign hw2reg.status.rxempty.d     = ~rx_fifo_rvalid;
           Tests:       T1 T2 T3 
145        1/1            assign hw2reg.status.rxidle.d      = rx_uart_idle;
           Tests:       T1 T2 T3 
146        1/1            assign hw2reg.status.txidle.d      = tx_uart_idle & ~tx_fifo_rvalid;
           Tests:       T1 T2 T3 
147        1/1            assign hw2reg.status.txempty.d     = ~tx_fifo_rvalid;
           Tests:       T1 T2 T3 
148        1/1            assign hw2reg.status.rxfull.d      = ~rx_fifo_wready;
           Tests:       T1 T2 T3 
149        1/1            assign hw2reg.status.txfull.d      = ~tx_fifo_wready;
           Tests:       T1 T2 T3 
150                     
151        1/1            assign hw2reg.fifo_status.txlvl.d  = 8'(tx_fifo_depth);
           Tests:       T1 T2 T3 
152        1/1            assign hw2reg.fifo_status.rxlvl.d  = 8'(rx_fifo_depth);
           Tests:       T1 T2 T3 
153                     
154                       // resets are self-clearing, so need to update FIFO_CTRL
155                       assign hw2reg.fifo_ctrl.rxilvl.de = 1'b0;
156                       assign hw2reg.fifo_ctrl.rxilvl.d  = 3'h0;
157                       assign hw2reg.fifo_ctrl.txilvl.de = 1'b0;
158                       assign hw2reg.fifo_ctrl.txilvl.d  = 3'h0;
159                     
160                       //              NCO 16x Baud Generator
161                       // output clock rate is:
162                       //      Fin * (NCO/2**NcoWidth)
163                       logic   [NcoWidth:0]     nco_sum_q; // extra bit to get the carry
164                     
165                       always_ff @(posedge clk_i or negedge rst_ni) begin
166        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
167        1/1                nco_sum_q <= 17'h0;
           Tests:       T1 T2 T3 
168        1/1              end else if (tx_enable || rx_enable) begin
           Tests:       T1 T2 T3 
169        1/1                nco_sum_q <= {1'b0,nco_sum_q[NcoWidth-1:0]} + {1'b0,reg2hw.ctrl.nco.q[NcoWidth-1:0]};
           Tests:       T1 T2 T3 
170                         end
                        MISSING_ELSE
171                       end
172                     
173        1/1            assign tick_baud_x16 = nco_sum_q[16];
           Tests:       T1 T2 T3 
174                     
175                       //////////////
176                       // TX Logic //
177                       //////////////
178                     
179        1/1            assign tx_fifo_rready = tx_uart_idle & tx_fifo_rvalid & tx_enable;
           Tests:       T1 T2 T3 
180                     
181                       prim_fifo_sync #(
182                         .Width   (8),
183                         .Pass    (1'b0),
184                         .Depth   (TxFifoDepth)
185                       ) u_uart_txfifo (
186                         .clk_i,
187                         .rst_ni,
188                         .clr_i   (uart_fifo_txrst),
189                         .wvalid_i(reg2hw.wdata.qe),
190                         .wready_o(tx_fifo_wready),
191                         .wdata_i (reg2hw.wdata.q),
192                         .depth_o (tx_fifo_depth),
193                         .full_o (),
194                         .rvalid_o(tx_fifo_rvalid),
195                         .rready_i(tx_fifo_rready),
196                         .rdata_o (tx_fifo_data),
197                         .err_o   ()
198                       );
199                     
200                       uart_tx uart_tx (
201                         .clk_i,
202                         .rst_ni,
203                         .tx_enable,
204                         .tick_baud_x16,
205                         .parity_enable  (reg2hw.ctrl.parity_en.q),
206                         .wr             (tx_fifo_rready),
207                         .wr_parity      ((^tx_fifo_data) ^ reg2hw.ctrl.parity_odd.q),
208                         .wr_data        (tx_fifo_data),
209                         .idle           (tx_uart_idle),
210                         .tx             (tx_out)
211                       );
212                     
213        1/1            assign tx = line_loopback ? rx : tx_out_q ;
           Tests:       T1 T2 T3 
214                       always_ff @(posedge clk_i or negedge rst_ni) begin
215        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
216        1/1                tx_out_q <= 1'b1;
           Tests:       T1 T2 T3 
217        1/1              end else if (ovrd_tx_en) begin
           Tests:       T1 T2 T3 
218        1/1                tx_out_q <= ovrd_tx_val ;
           Tests:       T4 T16 T20 
219        1/1              end else if (sys_loopback) begin
           Tests:       T1 T2 T3 
220        1/1                tx_out_q <= 1'b1;
           Tests:       T7 T15 T25 
221                         end else begin
222        1/1                tx_out_q <= tx_out;
           Tests:       T1 T2 T3 
223                         end
224                       end
225                     
226                       //////////////
227                       // RX Logic //
228                       //////////////
229                     
230                       //      sync the incoming data
231                       prim_flop_2sync #(
232                         .Width(1),
233                         .ResetValue(1'b1)
234                       ) sync_rx (
235                         .clk_i,
236                         .rst_ni,
237                         .d_i(rx),
238                         .q_o(rx_sync)
239                       );
240                     
241                       // Based on: en.wikipedia.org/wiki/Repetition_code mentions the use of a majority filter
242                       // in UART to ignore brief noise spikes
243                       logic   rx_sync_q1, rx_sync_q2, rx_in_mx, rx_in_maj;
244                     
245                       always_ff @(posedge clk_i or negedge rst_ni) begin
246        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
247        1/1                rx_sync_q1 <= 1'b1;
           Tests:       T1 T2 T3 
248        1/1                rx_sync_q2 <= 1'b1;
           Tests:       T1 T2 T3 
249                         end else begin
250        1/1                rx_sync_q1 <= rx_sync;
           Tests:       T1 T2 T3 
251        1/1                rx_sync_q2 <= rx_sync_q1;
           Tests:       T1 T2 T3 
252                         end
253                       end
254                     
255        1/1            assign rx_in_maj = (rx_sync    & rx_sync_q1) |
           Tests:       T1 T2 T3 
256                                          (rx_sync    & rx_sync_q2) |
257                                          (rx_sync_q1 & rx_sync_q2);
258        1/1            assign rx_in_mx  = rxnf_enable ? rx_in_maj : rx_sync;
           Tests:       T1 T2 T3 
259                     
260        1/1            assign rx_in =  sys_loopback ? tx_out   :
           Tests:       T1 T2 T3 
261                                       line_loopback ? 1'b1 :
262                                       rx_in_mx;
263                     
264                       uart_rx uart_rx (
265                         .clk_i,
266                         .rst_ni,
267                         .rx_enable,
268                         .tick_baud_x16,
269                         .parity_enable  (reg2hw.ctrl.parity_en.q),
270                         .parity_odd     (reg2hw.ctrl.parity_odd.q),
271                         .tick_baud      (rx_tick_baud),
272                         .rx_valid,
273                         .rx_data        (rx_fifo_data),
274                         .idle           (rx_uart_idle),
275                         .frame_err      (event_rx_frame_err),
276                         .rx             (rx_in),
277                         .rx_parity_err  (event_rx_parity_err)
278                       );
279                     
280        1/1            assign rx_fifo_wvalid = rx_valid & ~event_rx_frame_err & ~event_rx_parity_err;
           Tests:       T1 T2 T3 
281                     
282                       prim_fifo_sync #(
283                         .Width   (8),
284                         .Pass    (1'b0),
285                         .Depth   (RxFifoDepth)
286                       ) u_uart_rxfifo (
287                         .clk_i,
288                         .rst_ni,
289                         .clr_i   (uart_fifo_rxrst),
290                         .wvalid_i(rx_fifo_wvalid),
291                         .wready_o(rx_fifo_wready),
292                         .wdata_i (rx_fifo_data),
293                         .depth_o (rx_fifo_depth),
294                         .full_o (),
295                         .rvalid_o(rx_fifo_rvalid),
296                         .rready_i(reg2hw.rdata.re),
297                         .rdata_o (uart_rdata),
298                         .err_o   ()
299                       );
300                     
301                       always_ff @(posedge clk_i or negedge rst_ni) begin
302        2/2              if (!rst_ni)            rx_val_q <= 16'h0;
           Tests:       T1 T2 T3  | T1 T2 T3 
303        2/2              else if (tick_baud_x16) rx_val_q <= {rx_val_q[14:0], rx_in};
           Tests:       T1 T2 T3  | T1 T2 T3 
                        MISSING_ELSE
304                       end
305                     
306                       ////////////////////////
307                       // Interrupt & Status //
308                       ////////////////////////
309                     
310                       logic [TxFifoDepthW-1:0] tx_watermark_thresh;
311                       always_comb begin
312                         // Create power of two thresholds.
313                         // The threshold saturates at half the FIFO depth.
314        1/1              if (uart_fifo_txilvl >= (TxFifoDepthW-2)) begin
           Tests:       T1 T2 T3 
315        1/1                tx_watermark_thresh = TxFifoDepthW'(TxFifoDepth/2);
           Tests:       T2 T7 T8 
316                         end else begin
317        1/1                tx_watermark_thresh = 1'b1 << uart_fifo_txilvl;
           Tests:       T1 T2 T3 
318                         end
319        1/1              event_tx_watermark = tx_fifo_depth < tx_watermark_thresh;
           Tests:       T1 T2 T3 
320                       end
321                     
322        1/1            assign event_tx_empty = tx_fifo_depth == '0;
           Tests:       T1 T2 T3 
323                     
324        1/1            assign event_tx_done = ~tx_fifo_rvalid & ~tx_uart_idle_q & tx_uart_idle;
           Tests:       T1 T2 T3 
325                     
326                       always_ff @(posedge clk_i or negedge rst_ni) begin
327        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
328        1/1                tx_uart_idle_q       <= 1'b1;
           Tests:       T1 T2 T3 
329                         end else begin
330        1/1                tx_uart_idle_q       <= tx_uart_idle;
           Tests:       T1 T2 T3 
331                         end
332                       end
333                     
334                       logic [RxFifoDepthW-1:0] rx_watermark_thresh;
335                       always_comb begin
336                         // Create power of two thresholds.
337        1/1              if (uart_fifo_rxilvl > (RxFifoDepthW-1)) begin
           Tests:       T1 T2 T3 
338                           // This results in the comparison always returning 0 below because RxFifoDepth can
339                           // encode depths up to 2*RxFifoDepth-1.
340        0/1     ==>        rx_watermark_thresh = {RxFifoDepthW{1'b1}};
341        1/1              end else if (uart_fifo_rxilvl == (RxFifoDepthW-1)) begin
           Tests:       T1 T2 T3 
342                           // The maximum valid threshold threshold is an exception and saturates at RxFifoDepth-2.
343        1/1                rx_watermark_thresh = RxFifoDepthW'(RxFifoDepth-2);
           Tests:       T7 T8 T10 
344                         end else begin
345        1/1                rx_watermark_thresh = 1'b1 << uart_fifo_rxilvl;
           Tests:       T1 T2 T3 
346                         end
347        1/1              event_rx_watermark = rx_fifo_depth >= rx_watermark_thresh;
           Tests:       T1 T2 T3 
348                       end
349                     
350                     
351                     
352                       // rx timeout interrupt
353        1/1            assign uart_rxto_en  = reg2hw.timeout_ctrl.en.q;
           Tests:       T1 T2 T3 
354        1/1            assign uart_rxto_val = reg2hw.timeout_ctrl.val.q;
           Tests:       T1 T2 T3 
355                     
356        1/1            assign rx_fifo_depth_changed = (rx_fifo_depth != rx_fifo_depth_prev_q);
           Tests:       T1 T2 T3 
357                     
358        1/1            assign rx_timeout_count_d =
           Tests:       T1 T2 T3 
359                                   // don't count if timeout feature not enabled ;
360                                   // will never reach timeout val + lower power
361                                   (uart_rxto_en == 1'b0)              ? 24'd0 :
362                                   // reset count if timeout interrupt is set
363                                   event_rx_timeout                    ? 24'd0 :
364                                   // reset count upon change in fifo level: covers both read and receiving a new byte
365                                   rx_fifo_depth_changed               ? 24'd0 :
366                                   // reset count if no bytes are pending
367                                   (rx_fifo_depth == '0)               ? 24'd0 :
368                                   // stop the count at timeout value (this will set the interrupt)
369                                   //   Removed below line as when the timeout reaches the value,
370                                   //   event occured, and timeout value reset to 0h.
371                                   //(rx_timeout_count_q == uart_rxto_val) ? rx_timeout_count_q :
372                                   // increment if at rx baud tick
373                                   rx_tick_baud                        ? (rx_timeout_count_q + 24'd1) :
374                                   rx_timeout_count_q;
375                     
376        1/1            assign event_rx_timeout = (rx_timeout_count_q == uart_rxto_val) & uart_rxto_en;
           Tests:       T1 T2 T3 
377                     
378                       always_ff @(posedge clk_i or negedge rst_ni) begin
379        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
380        1/1                rx_timeout_count_q   <= 24'd0;
           Tests:       T1 T2 T3 
381        1/1                rx_fifo_depth_prev_q <= '0;
           Tests:       T1 T2 T3 
382                         end else begin
383        1/1                rx_timeout_count_q    <= rx_timeout_count_d;
           Tests:       T1 T2 T3 
384        1/1                rx_fifo_depth_prev_q  <= rx_fifo_depth;
           Tests:       T1 T2 T3 
385                         end
386                       end
387                     
388        1/1            assign event_rx_overflow  = rx_fifo_wvalid & ~rx_fifo_wready;
           Tests:       T1 T2 T3 
389        1/1            assign event_rx_break_err = break_err & (break_st_q == BRK_CHK);
           Tests:       T1 T2 T3 
390                     
391                       // instantiate interrupt hardware primitives
392                     
393                       prim_intr_hw #(.Width(1), .IntrT("Status")) intr_hw_tx_watermark (
394                         .clk_i,
395                         .rst_ni,
396                         .event_intr_i           (event_tx_watermark),
397                         .reg2hw_intr_enable_q_i (reg2hw.intr_enable.tx_watermark.q),
398                         .reg2hw_intr_test_q_i   (reg2hw.intr_test.tx_watermark.q),
399                         .reg2hw_intr_test_qe_i  (reg2hw.intr_test.tx_watermark.qe),
400                         .reg2hw_intr_state_q_i  (reg2hw.intr_state.tx_watermark.q),
401                         .hw2reg_intr_state_de_o (hw2reg.intr_state.tx_watermark.de),
402                         .hw2reg_intr_state_d_o  (hw2reg.intr_state.tx_watermark.d),
403                         .intr_o                 (intr_tx_watermark_o)
404                       );
405                     
406                       prim_intr_hw #(.Width(1), .IntrT("Status")) intr_hw_tx_empty (
407                         .clk_i,
408                         .rst_ni,
409                         .event_intr_i           (event_tx_empty),
410                         .reg2hw_intr_enable_q_i (reg2hw.intr_enable.tx_empty.q),
411                         .reg2hw_intr_test_q_i   (reg2hw.intr_test.tx_empty.q),
412                         .reg2hw_intr_test_qe_i  (reg2hw.intr_test.tx_empty.qe),
413                         .reg2hw_intr_state_q_i  (reg2hw.intr_state.tx_empty.q),
414                         .hw2reg_intr_state_de_o (hw2reg.intr_state.tx_empty.de),
415                         .hw2reg_intr_state_d_o  (hw2reg.intr_state.tx_empty.d),
416                         .intr_o                 (intr_tx_empty_o)
417                       );
418                     
419                       prim_intr_hw #(.Width(1), .IntrT("Status")) intr_hw_rx_watermark (
420                         .clk_i,
421                         .rst_ni,
422                         .event_intr_i           (event_rx_watermark),
423                         .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_watermark.q),
424                         .reg2hw_intr_test_q_i   (reg2hw.intr_test.rx_watermark.q),
425                         .reg2hw_intr_test_qe_i  (reg2hw.intr_test.rx_watermark.qe),
426                         .reg2hw_intr_state_q_i  (reg2hw.intr_state.rx_watermark.q),
427                         .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_watermark.de),
428                         .hw2reg_intr_state_d_o  (hw2reg.intr_state.rx_watermark.d),
429                         .intr_o                 (intr_rx_watermark_o)
430                       );
431                     
432                       prim_intr_hw #(.Width(1)) intr_hw_tx_done (
433                         .clk_i,
434                         .rst_ni,
435                         .event_intr_i           (event_tx_done),
436                         .reg2hw_intr_enable_q_i (reg2hw.intr_enable.tx_done.q),
437                         .reg2hw_intr_test_q_i   (reg2hw.intr_test.tx_done.q),
438                         .reg2hw_intr_test_qe_i  (reg2hw.intr_test.tx_done.qe),
439                         .reg2hw_intr_state_q_i  (reg2hw.intr_state.tx_done.q),
440                         .hw2reg_intr_state_de_o (hw2reg.intr_state.tx_done.de),
441                         .hw2reg_intr_state_d_o  (hw2reg.intr_state.tx_done.d),
442                         .intr_o                 (intr_tx_done_o)
443                       );
444                     
445                       prim_intr_hw #(.Width(1)) intr_hw_rx_overflow (
446                         .clk_i,
447                         .rst_ni,
448                         .event_intr_i           (event_rx_overflow),
449                         .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_overflow.q),
450                         .reg2hw_intr_test_q_i   (reg2hw.intr_test.rx_overflow.q),
451                         .reg2hw_intr_test_qe_i  (reg2hw.intr_test.rx_overflow.qe),
452                         .reg2hw_intr_state_q_i  (reg2hw.intr_state.rx_overflow.q),
453                         .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_overflow.de),
454                         .hw2reg_intr_state_d_o  (hw2reg.intr_state.rx_overflow.d),
455                         .intr_o                 (intr_rx_overflow_o)
456                       );
457                     
458                       prim_intr_hw #(.Width(1)) intr_hw_rx_frame_err (
459                         .clk_i,
460                         .rst_ni,
461                         .event_intr_i           (event_rx_frame_err),
462                         .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_frame_err.q),
463                         .reg2hw_intr_test_q_i   (reg2hw.intr_test.rx_frame_err.q),
464                         .reg2hw_intr_test_qe_i  (reg2hw.intr_test.rx_frame_err.qe),
465                         .reg2hw_intr_state_q_i  (reg2hw.intr_state.rx_frame_err.q),
466                         .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_frame_err.de),
467                         .hw2reg_intr_state_d_o  (hw2reg.intr_state.rx_frame_err.d),
468                         .intr_o                 (intr_rx_frame_err_o)
469                       );
470                     
471                       prim_intr_hw #(.Width(1)) intr_hw_rx_break_err (
472                         .clk_i,
473                         .rst_ni,
474                         .event_intr_i           (event_rx_break_err),
475                         .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_break_err.q),
476                         .reg2hw_intr_test_q_i   (reg2hw.intr_test.rx_break_err.q),
477                         .reg2hw_intr_test_qe_i  (reg2hw.intr_test.rx_break_err.qe),
478                         .reg2hw_intr_state_q_i  (reg2hw.intr_state.rx_break_err.q),
479                         .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_break_err.de),
480                         .hw2reg_intr_state_d_o  (hw2reg.intr_state.rx_break_err.d),
481                         .intr_o                 (intr_rx_break_err_o)
482                       );
483                     
484                       prim_intr_hw #(.Width(1)) intr_hw_rx_timeout (
485                         .clk_i,
486                         .rst_ni,
487                         .event_intr_i           (event_rx_timeout),
488                         .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_timeout.q),
489                         .reg2hw_intr_test_q_i   (reg2hw.intr_test.rx_timeout.q),
490                         .reg2hw_intr_test_qe_i  (reg2hw.intr_test.rx_timeout.qe),
491                         .reg2hw_intr_state_q_i  (reg2hw.intr_state.rx_timeout.q),
492                         .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_timeout.de),
493                         .hw2reg_intr_state_d_o  (hw2reg.intr_state.rx_timeout.d),
494                         .intr_o                 (intr_rx_timeout_o)
495                       );
496                     
497                       prim_intr_hw #(.Width(1)) intr_hw_rx_parity_err (
498                         .clk_i,
499                         .rst_ni,
500                         .event_intr_i           (event_rx_parity_err),
501                         .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_parity_err.q),
502                         .reg2hw_intr_test_q_i   (reg2hw.intr_test.rx_parity_err.q),
503                         .reg2hw_intr_test_qe_i  (reg2hw.intr_test.rx_parity_err.qe),
504                         .reg2hw_intr_state_q_i  (reg2hw.intr_state.rx_parity_err.q),
505                         .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_parity_err.de),
506                         .hw2reg_intr_state_d_o  (hw2reg.intr_state.rx_parity_err.d),
507                         .intr_o                 (intr_rx_parity_err_o)
508                       );
509                     
510                       // unused registers
511                       logic unused_reg;
512        1/1            assign unused_reg = ^reg2hw.alert_test;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.uart_core

	Total	Covered	Percent
Conditions	104	103	99.04
Logical	104	103	99.04
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (reg2hw.fifo_ctrl.rxrst.q & reg2hw.fifo_ctrl.rxrst.qe)
             ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T2,T7,T10
1	1	Covered	T2,T7,T10

 LINE       80
 EXPRESSION (reg2hw.fifo_ctrl.txrst.q & reg2hw.fifo_ctrl.txrst.qe)
             ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T8,T12,T21
1	1	Covered	T8,T12,T21

 LINE       94
 EXPRESSION (rx_valid & (((~event_rx_frame_err)) | (rx_fifo_data != 8'b0)))
             ----1---   -------------------------2------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T24
1	1	Covered	T1,T2,T3

 LINE       94
 SUB-EXPRESSION (((~event_rx_frame_err)) | (rx_fifo_data != 8'b0))
                 -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T24
0	1	Covered	T2,T10,T22
1	0	Covered	T1,T2,T3

 LINE       94
 SUB-EXPRESSION (rx_fifo_data != 8'b0)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       95
 EXPRESSION (event_rx_frame_err & (rx_fifo_data == 8'b0))
             ---------1--------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T22
1	1	Covered	T21,T22,T24

 LINE       95
 SUB-EXPRESSION (rx_fifo_data == 8'b0)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (((break_st_q == BRK_WAIT) || not_allzero_char) ? 5'b0 : (allzero_err ? ((allzero_cnt_q + 5'b1)) : allzero_cnt_q))
             -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 SUB-EXPRESSION ((break_st_q == BRK_WAIT) || not_allzero_char)
                 ------------1-----------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T22,T24

 LINE       98
 SUB-EXPRESSION (break_st_q == BRK_WAIT)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T24

 LINE       98
 SUB-EXPRESSION (allzero_err ? ((allzero_cnt_q + 5'b1)) : allzero_cnt_q)
                 -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T24

 LINE       146
 EXPRESSION (tx_uart_idle & ((~tx_fifo_rvalid)))
             ------1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       168
 EXPRESSION (tx_enable || rx_enable)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T10
1	0	Covered	T8,T11,T12

 LINE       179
 EXPRESSION (tx_uart_idle & tx_fifo_rvalid & tx_enable)
             ------1-----   -------2------   ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T8,T14
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T8,T11,T12
1	1	1	Covered	T1,T3,T4

 LINE       200
 EXPRESSION (((^tx_fifo_data)) ^ reg2hw.ctrl.parity_odd.q)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T7

 LINE       213
 EXPRESSION (line_loopback ? rx : tx_out_q)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T15,T25

 LINE       255
 EXPRESSION ((rx_sync & rx_sync_q1) | (rx_sync & rx_sync_q2) | (rx_sync_q1 & rx_sync_q2))
             -----------1----------   -----------2----------   ------------3------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T3,T4
1	0	0	Covered	T1,T2,T3

 LINE       255
 SUB-EXPRESSION (rx_sync & rx_sync_q1)
                 ---1---   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       255
 SUB-EXPRESSION (rx_sync & rx_sync_q2)
                 ---1---   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       255
 SUB-EXPRESSION (rx_sync_q1 & rx_sync_q2)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       258
 EXPRESSION (rxnf_enable ? rx_in_maj : rx_sync)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       260
 EXPRESSION (sys_loopback ? tx_out : (line_loopback ? 1'b1 : rx_in_mx))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T15,T25

 LINE       260
 SUB-EXPRESSION (line_loopback ? 1'b1 : rx_in_mx)
                 ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T15,T25

 LINE       280
 EXPRESSION (rx_valid & ((~event_rx_frame_err)) & ((~event_rx_parity_err)))
             ----1---   -----------2-----------   ------------3-----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T10,T22
1	1	0	Covered	T10,T21,T26
1	1	1	Covered	T1,T3,T4

 LINE       322
 EXPRESSION (tx_fifo_depth == '0)
            ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       324
 EXPRESSION (((~tx_fifo_rvalid)) & ((~tx_uart_idle_q)) & tx_uart_idle)
             ---------1---------   ---------2---------   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T8,T14
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T3,T4
1	1	1	Covered	T1,T3,T4

 LINE       341
 EXPRESSION (uart_fifo_rxilvl == (RxFifoDepthW - 1))
            --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T10

 LINE       356
 EXPRESSION (rx_fifo_depth != rx_fifo_depth_prev_q)
            -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       358
 EXPRESSION 
 Number  Term
      1  (uart_rxto_en == 1'b0) ? 24'b0 : (event_rx_timeout ? 24'b0 : (rx_fifo_depth_changed ? 24'b0 : ((rx_fifo_depth == '0) ? 24'b0 : (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q)))))

-1-	Status	Tests
0	Covered	T2,T7,T8
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (uart_rxto_en == 1'b0)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION 
 Number  Term
      1  event_rx_timeout ? 24'b0 : (rx_fifo_depth_changed ? 24'b0 : ((rx_fifo_depth == '0) ? 24'b0 : (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q))))

-1-	Status	Tests
0	Covered	T2,T7,T8
1	Covered	T8,T11,T12

 LINE       358
 SUB-EXPRESSION (rx_fifo_depth_changed ? 24'b0 : ((rx_fifo_depth == '0) ? 24'b0 : (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q)))
                 ----------1----------

-1-	Status	Tests
0	Covered	T2,T7,T8
1	Covered	T7,T8,T10

 LINE       358
 SUB-EXPRESSION ((rx_fifo_depth == '0) ? 24'b0 : (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q))
                 ----------1----------

-1-	Status	Tests
0	Covered	T7,T8,T10
1	Covered	T2,T7,T8

 LINE       358
 SUB-EXPRESSION (rx_fifo_depth == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T7,T8,T10
1	Covered	T2,T7,T8

 LINE       358
 SUB-EXPRESSION (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q)
                 ------1-----

-1-	Status	Tests
0	Covered	T7,T8,T10
1	Covered	T8,T10,T11

 LINE       376
 EXPRESSION ((rx_timeout_count_q == uart_rxto_val) & uart_rxto_en)
             ------------------1------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T11,T12

 LINE       376
 SUB-EXPRESSION (rx_timeout_count_q == uart_rxto_val)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       388
 EXPRESSION (rx_fifo_wvalid & ((~rx_fifo_wready)))
             -------1------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T17,T18,T19

 LINE       389
 EXPRESSION (break_err & (break_st_q == BRK_CHK))
             ----1----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T21,T22,T24

 LINE       389
 SUB-EXPRESSION (break_st_q == BRK_CHK)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.uart_core

	Line No.	Total	Covered	Percent
Branches		49	48	97.96
TERNARY	98	3	3	100.00
TERNARY	213	2	2	100.00
TERNARY	258	2	2	100.00
TERNARY	260	3	3	100.00
TERNARY	358	6	6	100.00
IF	105	3	3	100.00
CASE	113	4	4	100.00
IF	122	5	5	100.00
IF	166	3	3	100.00
IF	215	4	4	100.00
IF	246	2	2	100.00
IF	302	3	3	100.00
IF	314	2	2	100.00
IF	327	2	2	100.00
IF	337	3	2	66.67
IF	379	2	2	100.00

98           assign allzero_cnt_d = (break_st_q == BRK_WAIT || not_allzero_char) ? 5'h0 :
                                                                                 -1-  
                                                                                 ==>  
99                                   //allzero_cnt_q[4] never be 1b without break_st_q as BRK_WAIT
                                                                                                  
100                                  //allzero_cnt_q[4] ? allzero_cnt_q :
                                                                         
101                                  allzero_err ? allzero_cnt_q + 5'd1 :
                                                 -2-  
                                                 ==>  
                                                 ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T21,T22,T24
0	0	Covered	T1,T2,T3

213          assign tx = line_loopback ? rx : tx_out_q ;
                                       -1-  
                                       ==>  
                                       ==>  

Branches:

-1-	Status	Tests
1	Covered	T7,T15,T25
0	Covered	T1,T2,T3

258          assign rx_in_mx  = rxnf_enable ? rx_in_maj : rx_sync;
                                            -1-  
                                            ==>  
                                            ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

260          assign rx_in =  sys_loopback ? tx_out   :
                                          -1-  
                                          ==>  
261                          line_loopback ? 1'b1 :
                                           -2-  
                                           ==>  
                                           ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T15,T25
0	1	Covered	T7,T15,T25
0	0	Covered	T1,T2,T3

358          assign rx_timeout_count_d =
                                        
359                      // don't count if timeout feature not enabled ;
                                                                        
360                      // will never reach timeout val + lower power
                                                                      
361                      (uart_rxto_en == 1'b0)              ? 24'd0 :
                                                             -1-  
                                                             ==>  
362                      // reset count if timeout interrupt is set
                                                                   
363                      event_rx_timeout                    ? 24'd0 :
                                                             -2-  
                                                             ==>  
364                      // reset count upon change in fifo level: covers both read and receiving a new byte
                                                                                                            
365                      rx_fifo_depth_changed               ? 24'd0 :
                                                             -3-  
                                                             ==>  
366                      // reset count if no bytes are pending
                                                               
367                      (rx_fifo_depth == '0)               ? 24'd0 :
                                                             -4-  
                                                             ==>  
368                      // stop the count at timeout value (this will set the interrupt)
                                                                                         
369                      //   Removed below line as when the timeout reaches the value,
                                                                                       
370                      //   event occured, and timeout value reset to 0h.
                                                                           
371                      //(rx_timeout_count_q == uart_rxto_val) ? rx_timeout_count_q :
                                                                                       
372                      // increment if at rx baud tick
                                                        
373                      rx_tick_baud                        ? (rx_timeout_count_q + 24'd1) :
                                                             -5-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T8,T11,T12
0	0	1	-	-	Covered	T7,T8,T10
0	0	0	1	-	Covered	T2,T7,T8
0	0	0	0	1	Covered	T8,T10,T11
0	0	0	0	0	Covered	T7,T8,T10

105            if (!rst_ni)        allzero_cnt_q <= '0;
               -1-  
               ==>
106            else if (rx_enable) allzero_cnt_q <= allzero_cnt_d;
                    -2-  
               ==>
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

113            unique case (reg2hw.ctrl.rxblvl.q)
                      -1-  
114              2'h0:    break_err = allzero_cnt_d >= 5'd2;
                 ==>
115              2'h1:    break_err = allzero_cnt_d >= 5'd4;
                 ==>
116              2'h2:    break_err = allzero_cnt_d >= 5'd8;
                 ==>
117              default: break_err = allzero_cnt_d >= 5'd16;
                 ==>

Branches:

-1-	Status	Tests
2'h0	Covered	T1,T2,T3
2'h1	Covered	T7,T8,T11
2'h2	Covered	T2,T7,T8
default	Covered	T7,T8,T10

122            if (!rst_ni) break_st_q <= BRK_CHK;
               -1-  
               ==>
123            else begin
124              unique case (break_st_q)
                        -2-  
125                BRK_CHK: begin
126                  if (event_rx_break_err) break_st_q <= BRK_WAIT;
                     -3-  
                     ==>
                     MISSING_ELSE
                     ==>
127                end
128        
129                BRK_WAIT: begin
130                  if (rx_in) break_st_q <= BRK_CHK;
                     -4-  
                     ==>
                     MISSING_ELSE
                     ==>
131                end
132        
133                default: begin
134                  break_st_q <= BRK_CHK;
                     ==> (Excluded)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	BRK_CHK	1	-	Covered	T21,T22,T24
0	BRK_CHK	0	-	Covered	T1,T2,T3
0	BRK_WAIT	-	1	Covered	T21,T22,T24
0	BRK_WAIT	-	0	Covered	T21,T22,T24
0	default	-	-	Excluded

166            if (!rst_ni) begin
               -1-  
167              nco_sum_q <= 17'h0;
                 ==>
168            end else if (tx_enable || rx_enable) begin
                        -2-  
169              nco_sum_q <= {1'b0,nco_sum_q[NcoWidth-1:0]} + {1'b0,reg2hw.ctrl.nco.q[NcoWidth-1:0]};
                 ==>
170            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

215            if (!rst_ni) begin
               -1-  
216              tx_out_q <= 1'b1;
                 ==>
217            end else if (ovrd_tx_en) begin
                        -2-  
218              tx_out_q <= ovrd_tx_val ;
                 ==>
219            end else if (sys_loopback) begin
                        -3-  
220              tx_out_q <= 1'b1;
                 ==>
221            end else begin
222              tx_out_q <= tx_out;
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T16,T20
0	0	1	Covered	T7,T15,T25
0	0	0	Covered	T1,T2,T3

246            if (!rst_ni) begin
               -1-  
247              rx_sync_q1 <= 1'b1;
                 ==>
248              rx_sync_q2 <= 1'b1;
249            end else begin
250              rx_sync_q1 <= rx_sync;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

302            if (!rst_ni)            rx_val_q <= 16'h0;
               -1-  
               ==>
303            else if (tick_baud_x16) rx_val_q <= {rx_val_q[14:0], rx_in};
                    -2-  
               ==>
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

314            if (uart_fifo_txilvl >= (TxFifoDepthW-2)) begin
               -1-                            
315              tx_watermark_thresh = TxFifoDepthW'(TxFifoDepth/2);
                 ==>
316            end else begin
317              tx_watermark_thresh = 1'b1 << uart_fifo_txilvl;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T8
0	Covered	T1,T2,T3

327            if (!rst_ni) begin
               -1-  
328              tx_uart_idle_q       <= 1'b1;
                 ==>
329            end else begin
330              tx_uart_idle_q       <= tx_uart_idle;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

337            if (uart_fifo_rxilvl > (RxFifoDepthW-1)) begin
               -1-                           
338              // This results in the comparison always returning 0 below because RxFifoDepth can
339              // encode depths up to 2*RxFifoDepth-1.
340              rx_watermark_thresh = {RxFifoDepthW{1'b1}};
                 ==>
341            end else if (uart_fifo_rxilvl == (RxFifoDepthW-1)) begin
                        -2-                            
342              // The maximum valid threshold threshold is an exception and saturates at RxFifoDepth-2.
343              rx_watermark_thresh = RxFifoDepthW'(RxFifoDepth-2);
                 ==>
344            end else begin
345              rx_watermark_thresh = 1'b1 << uart_fifo_rxilvl;
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T7,T8,T10
0	0	Covered	T1,T2,T3

379            if (!rst_ni) begin
               -1-  
380              rx_timeout_count_q   <= 24'd0;
                 ==>
381              rx_fifo_depth_prev_q <= '0;
382            end else begin
383              rx_timeout_count_q    <= rx_timeout_count_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.uart_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RxFifoDepth_A	1151	1151	0	0
TxFifoDepth_A	1151	1151	0	0

RxFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

TxFifoDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0