Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1086310	0	0
ctrl_rd_A	2147483647	19355	0	0
intr_enable_rd_A	2147483647	18383	0	0
ovrd_rd_A	2147483647	18650	0	0
timeout_ctrl_rd_A	2147483647	18618	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1086310	0	0
T20	193539	9008	0	0
T22	430584	0	0	0
T23	197237	9057	0	0
T25	639555	0	0	0
T27	0	5452	0	0
T31	1915	0	0	0
T32	4228	0	0	0
T33	0	11205	0	0
T34	0	4880	0	0
T35	0	23839	0	0
T36	0	7722	0	0
T37	0	7471	0	0
T38	0	18793	0	0
T39	0	5249	0	0
T40	211833	0	0	0
T41	162022	0	0	0
T42	88447	0	0	0
T43	275823	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	19355	0	0
T27	246159	632	0	0
T34	0	578	0	0
T37	0	853	0	0
T51	109571	0	0	0
T86	0	573	0	0
T87	0	444	0	0
T88	0	317	0	0
T89	0	944	0	0
T90	0	760	0	0
T91	0	396	0	0
T92	0	774	0	0
T93	107078	0	0	0
T94	601207	0	0	0
T95	151146	0	0	0
T96	584589	0	0	0
T97	147605	0	0	0
T98	463005	0	0	0
T99	169628	0	0	0
T100	219761	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	18383	0	0
T27	246159	606	0	0
T34	0	612	0	0
T37	0	816	0	0
T51	109571	0	0	0
T73	0	32	0	0
T86	0	594	0	0
T87	0	484	0	0
T88	0	290	0	0
T89	0	740	0	0
T90	0	774	0	0
T91	0	383	0	0
T93	107078	0	0	0
T94	601207	0	0	0
T95	151146	0	0	0
T96	584589	0	0	0
T97	147605	0	0	0
T98	463005	0	0	0
T99	169628	0	0	0
T100	219761	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	18650	0	0
T27	246159	615	0	0
T34	0	481	0	0
T37	0	974	0	0
T51	109571	0	0	0
T86	0	652	0	0
T87	0	538	0	0
T88	0	373	0	0
T89	0	818	0	0
T90	0	769	0	0
T91	0	491	0	0
T92	0	880	0	0
T93	107078	0	0	0
T94	601207	0	0	0
T95	151146	0	0	0
T96	584589	0	0	0
T97	147605	0	0	0
T98	463005	0	0	0
T99	169628	0	0	0
T100	219761	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	18618	0	0
T27	246159	715	0	0
T34	0	473	0	0
T37	0	791	0	0
T51	109571	0	0	0
T86	0	614	0	0
T87	0	580	0	0
T88	0	282	0	0
T89	0	849	0	0
T90	0	923	0	0
T91	0	392	0	0
T92	0	797	0	0
T93	107078	0	0	0
T94	601207	0	0	0
T95	151146	0	0	0
T96	584589	0	0	0
T97	147605	0	0	0
T98	463005	0	0	0
T99	169628	0	0	0
T100	219761	0	0	0