Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	66919154	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

14393207

1

T1

10

T2

10

T3

32

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	80055205	1			T1	354		T2	32		T3	1868
values[0x0]	609479	1			T1	9		T2	6		T3	16
values[0x1]	647677	1			T1	4		T2	7		T3	21

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46195172	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

35117189

1

T1

125

T2

14

T3

646

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	307521	1			T1	3		T3	2		T4	2
valid_sources[0x01]	288603	1			T1	4		T3	3		T5	1
valid_sources[0x02]	263459	1			T3	5		T8	72		T9	10
valid_sources[0x03]	304475	1			T1	18		T3	2		T4	2
valid_sources[0x04]	331536	1			T1	1		T3	4		T4	2
valid_sources[0x05]	278252	1			T3	4		T4	1		T5	4
valid_sources[0x06]	319923	1			T3	5		T5	2		T8	85
valid_sources[0x07]	329927	1			T3	2		T4	4		T5	5
valid_sources[0x08]	309056	1			T1	1		T3	3		T5	2
valid_sources[0x09]	459233	1			T1	2		T3	8		T5	5
valid_sources[0x0a]	284843	1			T1	1		T3	12		T4	2
valid_sources[0x0b]	305051	1			T1	9		T3	1		T5	2
valid_sources[0x0c]	411990	1			T3	4		T5	1		T8	34
valid_sources[0x0d]	326895	1			T3	3		T5	1		T8	68
valid_sources[0x0e]	308754	1			T1	5		T3	6		T5	3
valid_sources[0x0f]	322721	1			T3	9		T4	1		T5	4
valid_sources[0x10]	291725	1			T1	4		T3	7		T4	1
valid_sources[0x11]	289772	1			T3	5		T4	2		T5	1
valid_sources[0x12]	330896	1			T3	6		T4	1		T8	36
valid_sources[0x13]	283712	1			T1	2		T3	3		T5	3
valid_sources[0x14]	286514	1			T1	5		T3	7		T8	60
valid_sources[0x15]	282399	1			T3	8		T4	2		T5	3
valid_sources[0x16]	297564	1			T3	8		T4	4		T5	1
valid_sources[0x17]	315148	1			T1	11		T3	28		T4	4
valid_sources[0x18]	308674	1			T3	10		T4	1		T5	4
valid_sources[0x19]	319516	1			T3	18		T5	4		T8	77
valid_sources[0x1a]	280110	1			T3	11		T4	4		T5	4
valid_sources[0x1b]	358414	1			T1	3		T3	6		T4	2
valid_sources[0x1c]	291419	1			T1	2		T3	4		T4	2
valid_sources[0x1d]	310179	1			T1	3		T3	7		T4	2
valid_sources[0x1e]	303913	1			T3	15		T4	1		T5	7
valid_sources[0x1f]	302639	1			T3	8		T4	5		T5	5
valid_sources[0x20]	349192	1			T3	4		T4	2		T5	4
valid_sources[0x21]	343170	1			T1	6		T3	2		T5	8
valid_sources[0x22]	282588	1			T4	1		T5	3		T8	72
valid_sources[0x23]	303975	1			T3	8		T4	1		T5	5
valid_sources[0x24]	553341	1			T1	1		T3	1		T4	2
valid_sources[0x25]	310566	1			T3	6		T4	1		T5	3
valid_sources[0x26]	279810	1			T1	1		T3	5		T4	3
valid_sources[0x27]	313684	1			T3	2		T4	4		T5	1
valid_sources[0x28]	351039	1			T3	4		T4	1		T5	2
valid_sources[0x29]	299844	1			T1	1		T3	15		T4	2
valid_sources[0x2a]	317926	1			T1	3		T3	7		T4	2
valid_sources[0x2b]	387224	1			T1	1		T3	13		T4	2
valid_sources[0x2c]	303743	1			T1	3		T3	16		T4	1
valid_sources[0x2d]	331551	1			T3	7		T4	1		T5	4
valid_sources[0x2e]	274935	1			T1	1		T3	8		T4	1
valid_sources[0x2f]	349220	1			T1	5		T3	13		T4	1
valid_sources[0x30]	304477	1			T3	11		T4	4		T5	3
valid_sources[0x31]	277069	1			T1	3		T3	15		T4	1
valid_sources[0x32]	302344	1			T3	7		T4	2		T5	5
valid_sources[0x33]	296214	1			T3	17		T5	3		T8	55
valid_sources[0x34]	351168	1			T1	1		T3	3		T4	1
valid_sources[0x35]	339508	1			T3	4		T4	1		T5	1
valid_sources[0x36]	304544	1			T3	6		T4	1		T5	5
valid_sources[0x37]	306532	1			T3	2		T5	1		T8	69
valid_sources[0x38]	294798	1			T1	1		T3	3		T5	1
valid_sources[0x39]	300519	1			T1	1		T3	8		T4	1
valid_sources[0x3a]	300067	1			T1	4		T3	11		T4	1
valid_sources[0x3b]	295944	1			T1	1		T3	9		T4	2
valid_sources[0x3c]	282340	1			T3	6		T4	3		T5	1
valid_sources[0x3d]	330516	1			T1	3		T3	7		T5	5
valid_sources[0x3e]	316928	1			T3	4		T4	1		T5	2
valid_sources[0x3f]	287611	1			T3	8		T5	2		T8	62
valid_sources[0x40]	300552	1			T3	14		T4	1		T5	3
valid_sources[0x41]	300439	1			T1	2		T2	5		T3	1
valid_sources[0x42]	281351	1			T3	6		T4	2		T5	5
valid_sources[0x43]	306367	1			T1	9		T3	12		T4	2
valid_sources[0x44]	298224	1			T1	2		T3	1		T4	4
valid_sources[0x45]	303585	1			T3	3		T5	4		T8	60
valid_sources[0x46]	330835	1			T3	4		T5	4		T8	56
valid_sources[0x47]	303478	1			T1	2		T3	6		T4	1
valid_sources[0x48]	290117	1			T1	3		T3	4		T4	1
valid_sources[0x49]	319696	1			T3	6		T5	1		T8	56
valid_sources[0x4a]	292512	1			T1	6		T3	5		T4	3
valid_sources[0x4b]	295529	1			T1	1		T3	12		T5	5
valid_sources[0x4c]	329533	1			T1	1		T3	5		T4	2
valid_sources[0x4d]	295697	1			T3	3		T4	1		T5	7
valid_sources[0x4e]	293389	1			T1	7		T3	5		T4	2
valid_sources[0x4f]	291716	1			T1	1		T3	20		T4	1
valid_sources[0x50]	308360	1			T3	2		T4	3		T5	1
valid_sources[0x51]	351976	1			T1	3		T3	8		T5	2
valid_sources[0x52]	311390	1			T3	3		T5	6		T8	44
valid_sources[0x53]	306823	1			T1	2		T3	7		T4	2
valid_sources[0x54]	286175	1			T3	11		T4	3		T5	2
valid_sources[0x55]	288569	1			T3	6		T4	1		T5	4
valid_sources[0x56]	308806	1			T1	6		T3	20		T4	2
valid_sources[0x57]	473401	1			T1	3		T3	7		T4	2
valid_sources[0x58]	290602	1			T3	10		T5	2		T8	43
valid_sources[0x59]	287181	1			T3	4		T5	2		T8	58
valid_sources[0x5a]	282209	1			T3	9		T4	2		T5	2
valid_sources[0x5b]	294407	1			T3	4		T4	3		T5	5
valid_sources[0x5c]	380321	1			T3	1		T4	2		T5	2
valid_sources[0x5d]	328204	1			T3	13		T4	1		T5	5
valid_sources[0x5e]	285760	1			T1	1		T3	5		T5	2
valid_sources[0x5f]	306476	1			T1	1		T3	10		T5	3
valid_sources[0x60]	281322	1			T3	9		T4	2		T5	2
valid_sources[0x61]	304595	1			T1	6		T3	12		T4	1
valid_sources[0x62]	343929	1			T3	6		T4	1		T5	4
valid_sources[0x63]	294984	1			T3	6		T4	1		T5	1
valid_sources[0x64]	298343	1			T3	3		T5	1		T8	56
valid_sources[0x65]	275903	1			T1	5		T3	8		T4	2
valid_sources[0x66]	276649	1			T3	8		T4	1		T5	3
valid_sources[0x67]	282935	1			T3	14		T5	5		T8	65
valid_sources[0x68]	303857	1			T1	3		T3	16		T4	1
valid_sources[0x69]	353894	1			T1	1		T3	1		T5	1
valid_sources[0x6a]	349113	1			T1	2		T3	10		T5	1
valid_sources[0x6b]	300752	1			T3	7		T4	1		T5	3
valid_sources[0x6c]	292933	1			T1	3		T3	11		T4	4
valid_sources[0x6d]	301193	1			T1	1		T3	7		T4	1
valid_sources[0x6e]	345811	1			T3	12		T4	1		T5	2
valid_sources[0x6f]	306110	1			T3	3		T4	1		T5	1
valid_sources[0x70]	281512	1			T1	8		T3	14		T4	3
valid_sources[0x71]	304793	1			T3	6		T5	3		T8	70
valid_sources[0x72]	492530	1			T3	6		T4	2		T5	1
valid_sources[0x73]	316663	1			T1	1		T3	4		T4	3
valid_sources[0x74]	278065	1			T1	2		T3	20		T4	2
valid_sources[0x75]	299000	1			T1	1		T2	2		T3	8
valid_sources[0x76]	307622	1			T3	14		T5	3		T8	55
valid_sources[0x77]	349250	1			T1	5		T3	9		T4	1
valid_sources[0x78]	283241	1			T1	1		T3	3		T5	3
valid_sources[0x79]	290116	1			T3	3		T8	48		T9	12
valid_sources[0x7a]	326207	1			T3	5		T4	1		T5	4
valid_sources[0x7b]	284035	1			T3	4		T4	2		T5	1
valid_sources[0x7c]	374969	1			T1	2		T3	13		T4	4
valid_sources[0x7d]	310815	1			T1	1		T3	3		T4	2
valid_sources[0x7e]	307428	1			T1	2		T3	10		T4	1
valid_sources[0x7f]	293505	1			T1	1		T3	17		T4	1
valid_sources[0x80]	360327	1			T3	1		T5	1		T8	63

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

13591061

1

T1

6

T2

6

T3

6

values[0x0]

all_enables

biggest_size

425836

1

T1

4

T2

3

T3

9

values[0x1]

all_enables

biggest_size

376310

1

T2

1

T3

17

T4

9