Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1033706	0	0
ctrl_rd_A	2147483647	14920	0	0
intr_enable_rd_A	2147483647	14174	0	0
ovrd_rd_A	2147483647	13891	0	0
timeout_ctrl_rd_A	2147483647	13914	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1033706	0	0
T18	259145	10022	0	0
T19	0	15406	0	0
T20	644417	0	0	0
T21	228724	0	0	0
T23	21697	0	0	0
T27	0	2712	0	0
T28	0	15386	0	0
T31	887	0	0	0
T32	3121	0	0	0
T33	0	9104	0	0
T34	0	16915	0	0
T35	0	20475	0	0
T36	0	5930	0	0
T37	0	10931	0	0
T38	0	3578	0	0
T39	214662	0	0	0
T40	597202	0	0	0
T41	1116	0	0	0
T42	39868	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14920	0	0
T89	500328	964	0	0
T90	0	555	0	0
T91	0	1050	0	0
T92	0	459	0	0
T93	0	999	0	0
T94	0	594	0	0
T95	0	388	0	0
T96	0	358	0	0
T97	0	233	0	0
T98	0	1094	0	0
T99	389227	0	0	0
T100	405297	0	0	0
T101	555691	0	0	0
T102	945	0	0	0
T103	146136	0	0	0
T104	278838	0	0	0
T105	127333	0	0	0
T106	113706	0	0	0
T107	902820	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14174	0	0
T89	500328	803	0	0
T90	0	465	0	0
T91	0	917	0	0
T92	0	264	0	0
T93	0	963	0	0
T94	0	524	0	0
T95	0	359	0	0
T96	0	361	0	0
T97	0	177	0	0
T98	0	1015	0	0
T99	389227	0	0	0
T100	405297	0	0	0
T101	555691	0	0	0
T102	945	0	0	0
T103	146136	0	0	0
T104	278838	0	0	0
T105	127333	0	0	0
T106	113706	0	0	0
T107	902820	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13891	0	0
T89	500328	942	0	0
T90	0	616	0	0
T91	0	1093	0	0
T92	0	499	0	0
T93	0	1040	0	0
T94	0	554	0	0
T95	0	233	0	0
T96	0	383	0	0
T97	0	194	0	0
T98	0	1307	0	0
T99	389227	0	0	0
T100	405297	0	0	0
T101	555691	0	0	0
T102	945	0	0	0
T103	146136	0	0	0
T104	278838	0	0	0
T105	127333	0	0	0
T106	113706	0	0	0
T107	902820	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13914	0	0
T89	500328	1005	0	0
T90	0	515	0	0
T91	0	1080	0	0
T92	0	449	0	0
T93	0	1075	0	0
T94	0	508	0	0
T95	0	247	0	0
T96	0	333	0	0
T97	0	187	0	0
T98	0	1429	0	0
T99	389227	0	0	0
T100	405297	0	0	0
T101	555691	0	0	0
T102	945	0	0	0
T103	146136	0	0	0
T104	278838	0	0	0
T105	127333	0	0	0
T106	113706	0	0	0
T107	902820	0	0	0