USBDEV Simulation Results

Thursday May 18 2023 07:04:58 UTC

GitHub Revision: ac0bef2ce

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2907120974

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 0.610s 12.542us 0 50 0.00
V1 csr_hw_reset usbdev_csr_hw_reset 0.820s 61.286us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.040s 75.333us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 9.810s 1.756ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.120s 104.122us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.580s 102.032us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.040s 75.333us 20 20 100.00
usbdev_csr_aliasing 3.120s 104.122us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.630s 692.006us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.320s 177.202us 5 5 100.00
V1 TOTAL 65 115 56.52
V2 intr_test usbdev_intr_test 0.690s 19.958us 50 50 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 3.100s 219.888us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.100s 219.888us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 0.820s 61.286us 5 5 100.00
usbdev_csr_rw 1.040s 75.333us 20 20 100.00
usbdev_csr_aliasing 3.120s 104.122us 5 5 100.00
usbdev_same_csr_outstanding 1.670s 153.702us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 0.820s 61.286us 5 5 100.00
usbdev_csr_rw 1.040s 75.333us 20 20 100.00
usbdev_csr_aliasing 3.120s 104.122us 5 5 100.00
usbdev_same_csr_outstanding 1.670s 153.702us 20 20 100.00
V2 TOTAL 90 90 100.00
V2S tl_intg_err usbdev_sec_cm 9.920s 10.012ms 0 5 0.00
usbdev_tl_intg_err 9.870s 10.016ms 1 20 5.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 9.870s 10.016ms 1 20 5.00
V2S TOTAL 1 25 4.00
V3 TOTAL 0 0 --
Unmapped tests usbdev_stress_all_with_rand_reset 0.640s 3.278us 0 50 0.00
usbdev_stress_all 0.600s 0 50 0.00
TOTAL 156 330 47.27

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 7 87.50
V2 3 3 3 100.00
V2S 2 2 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
69.67 69.41 63.91 87.42 0.00 74.05 97.77 95.17

Failure Buckets

Past Results