Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43259	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	56450	1		T1	2		T2	3		T3	2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	57827	1		T1	2		T2	2		T3	2
values[0x0]	20537	1		T1	1		T2	1		T3	1
values[0x1]	21345	1		T4	6		T5	235		T6	14

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	30327	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	69382	1		T1	2		T2	3		T3	2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	332	1		T5	3		T7	16		T8	1
valid_sources[0x01]	370	1		T5	3		T7	9		T22	7
valid_sources[0x02]	815	1		T5	2		T8	10		T18	356
valid_sources[0x03]	409	1		T5	1		T8	4		T11	1
valid_sources[0x04]	430	1		T5	6		T6	3		T8	10
valid_sources[0x05]	379	1		T5	1		T7	3		T8	5
valid_sources[0x06]	499	1		T7	14		T8	7		T22	7
valid_sources[0x07]	353	1		T5	5		T7	3		T8	9
valid_sources[0x08]	309	1		T5	5		T7	1		T8	1
valid_sources[0x09]	342	1		T5	2		T7	9		T8	1
valid_sources[0x0a]	421	1		T5	2		T8	9		T12	4
valid_sources[0x0b]	561	1		T5	3		T7	15		T8	2
valid_sources[0x0c]	589	1		T5	3		T7	2		T8	1
valid_sources[0x0d]	295	1		T5	1		T7	4		T8	5
valid_sources[0x0e]	436	1		T8	6		T10	1		T11	1
valid_sources[0x0f]	292	1		T5	1		T7	1		T8	3
valid_sources[0x10]	321	1		T5	7		T7	7		T8	14
valid_sources[0x11]	334	1		T5	5		T8	5		T18	11
valid_sources[0x12]	336	1		T5	6		T7	6		T8	5
valid_sources[0x13]	808	1		T5	2		T7	2		T13	8
valid_sources[0x14]	405	1		T5	3		T7	3		T8	7
valid_sources[0x15]	399	1		T5	8		T7	8		T8	3
valid_sources[0x16]	464	1		T5	8		T7	1		T8	9
valid_sources[0x17]	477	1		T5	4		T6	6		T7	5
valid_sources[0x18]	345	1		T5	1		T7	5		T8	3
valid_sources[0x19]	329	1		T5	1		T6	3		T8	8
valid_sources[0x1a]	320	1		T5	2		T7	18		T8	2
valid_sources[0x1b]	346	1		T6	4		T7	7		T8	4
valid_sources[0x1c]	375	1		T11	3		T12	1		T13	4
valid_sources[0x1d]	498	1		T5	8		T7	7		T8	1
valid_sources[0x1e]	348	1		T5	4		T7	4		T8	3
valid_sources[0x1f]	333	1		T5	5		T8	2		T22	2
valid_sources[0x20]	401	1		T5	2		T7	11		T8	3
valid_sources[0x21]	358	1		T22	20		T12	1		T13	6
valid_sources[0x22]	421	1		T5	6		T7	4		T12	2
valid_sources[0x23]	398	1		T5	4		T8	9		T11	1
valid_sources[0x24]	551	1		T5	2		T8	12		T11	1
valid_sources[0x25]	341	1		T5	3		T8	5		T22	13
valid_sources[0x26]	300	1		T5	1		T7	12		T8	4
valid_sources[0x27]	424	1		T5	3		T8	5		T18	17
valid_sources[0x28]	391	1		T5	7		T7	9		T8	1
valid_sources[0x29]	617	1		T5	2		T7	5		T8	7
valid_sources[0x2a]	364	1		T5	3		T8	1		T11	1
valid_sources[0x2b]	453	1		T5	1		T7	4		T8	5
valid_sources[0x2c]	295	1		T5	2		T7	3		T8	2
valid_sources[0x2d]	487	1		T5	8		T8	4		T12	6
valid_sources[0x2e]	356	1		T5	2		T6	1		T8	1
valid_sources[0x2f]	426	1		T5	3		T7	5		T8	7
valid_sources[0x30]	511	1		T5	2		T7	18		T8	2
valid_sources[0x31]	336	1		T4	22		T5	4		T7	9
valid_sources[0x32]	313	1		T5	4		T7	2		T8	7
valid_sources[0x33]	324	1		T5	3		T8	2		T12	1
valid_sources[0x34]	373	1		T5	6		T7	1		T8	3
valid_sources[0x35]	314	1		T5	1		T7	8		T8	1
valid_sources[0x36]	523	1		T5	2		T7	6		T8	3
valid_sources[0x37]	484	1		T5	6		T7	6		T8	13
valid_sources[0x38]	603	1		T2	2		T5	6		T7	2
valid_sources[0x39]	389	1		T7	4		T8	1		T22	21
valid_sources[0x3a]	488	1		T5	3		T8	3		T18	91
valid_sources[0x3b]	333	1		T5	6		T8	6		T10	1
valid_sources[0x3c]	486	1		T5	2		T7	2		T8	7
valid_sources[0x3d]	438	1		T5	1		T7	1		T8	3
valid_sources[0x3e]	404	1		T5	3		T7	4		T8	8
valid_sources[0x3f]	362	1		T5	4		T7	5		T8	4
valid_sources[0x40]	493	1		T5	2		T8	3		T11	2
valid_sources[0x41]	451	1		T5	3		T7	19		T8	2
valid_sources[0x42]	230	1		T1	1		T5	4		T7	1
valid_sources[0x43]	435	1		T5	2		T6	2		T8	4
valid_sources[0x44]	295	1		T7	2		T8	3		T11	3
valid_sources[0x45]	499	1		T5	5		T7	1		T8	2
valid_sources[0x46]	350	1		T5	6		T8	6		T11	2
valid_sources[0x47]	330	1		T5	2		T7	15		T8	2
valid_sources[0x48]	327	1		T5	1		T7	8		T8	2
valid_sources[0x49]	503	1		T5	2		T8	5		T22	10
valid_sources[0x4a]	433	1		T5	7		T6	3		T7	14
valid_sources[0x4b]	327	1		T5	1		T7	5		T8	5
valid_sources[0x4c]	305	1		T5	3		T8	3		T18	5
valid_sources[0x4d]	356	1		T5	1		T6	5		T7	6
valid_sources[0x4e]	355	1		T8	3		T13	8		T15	1
valid_sources[0x4f]	330	1		T5	4		T8	1		T22	18
valid_sources[0x50]	377	1		T5	1		T8	15		T18	35
valid_sources[0x51]	384	1		T7	4		T8	2		T18	11
valid_sources[0x52]	320	1		T5	5		T7	6		T8	6
valid_sources[0x53]	298	1		T5	4		T8	1		T11	1
valid_sources[0x54]	463	1		T5	7		T7	3		T8	3
valid_sources[0x55]	238	1		T5	1		T18	9		T22	1
valid_sources[0x56]	256	1		T5	2		T8	7		T11	1
valid_sources[0x57]	355	1		T5	1		T7	1		T8	3
valid_sources[0x58]	374	1		T5	4		T7	17		T8	2
valid_sources[0x59]	325	1		T5	1		T8	8		T12	2
valid_sources[0x5a]	555	1		T5	6		T8	3		T11	2
valid_sources[0x5b]	311	1		T5	11		T7	4		T8	11
valid_sources[0x5c]	389	1		T5	1		T7	13		T8	3
valid_sources[0x5d]	393	1		T5	2		T7	2		T8	3
valid_sources[0x5e]	386	1		T7	10		T8	10		T10	1
valid_sources[0x5f]	304	1		T5	5		T7	9		T18	10
valid_sources[0x60]	431	1		T5	6		T7	1		T8	6
valid_sources[0x61]	301	1		T3	1		T5	4		T7	18
valid_sources[0x62]	348	1		T5	2		T7	5		T8	8
valid_sources[0x63]	715	1		T5	3		T7	1		T8	5
valid_sources[0x64]	396	1		T5	2		T7	3		T8	2
valid_sources[0x65]	324	1		T7	6		T8	1		T11	2
valid_sources[0x66]	377	1		T5	3		T8	1		T13	5
valid_sources[0x67]	497	1		T5	3		T8	1		T10	1
valid_sources[0x68]	541	1		T5	4		T6	4		T7	12
valid_sources[0x69]	374	1		T5	1		T7	1		T8	6
valid_sources[0x6a]	642	1		T5	1		T7	4		T8	4
valid_sources[0x6b]	545	1		T5	7		T7	14		T8	2
valid_sources[0x6c]	461	1		T5	8		T6	2		T8	1
valid_sources[0x6d]	451	1		T6	5		T7	8		T8	3
valid_sources[0x6e]	449	1		T5	1		T8	2		T22	1
valid_sources[0x6f]	397	1		T5	1		T7	8		T8	4
valid_sources[0x70]	333	1		T5	2		T7	6		T8	1
valid_sources[0x71]	328	1		T5	2		T7	1		T8	4
valid_sources[0x72]	230	1		T5	2		T18	3		T11	1
valid_sources[0x73]	320	1		T5	2		T7	1		T8	7
valid_sources[0x74]	336	1		T5	5		T6	4		T7	6
valid_sources[0x75]	326	1		T5	6		T7	3		T8	8
valid_sources[0x76]	378	1		T5	2		T7	8		T8	3
valid_sources[0x77]	349	1		T5	2		T7	4		T8	6
valid_sources[0x78]	374	1		T7	11		T8	7		T13	5
valid_sources[0x79]	413	1		T5	7		T7	4		T8	8
valid_sources[0x7a]	355	1		T5	3		T6	3		T8	4
valid_sources[0x7b]	386	1		T5	3		T6	1		T7	12
valid_sources[0x7c]	335	1		T5	3		T7	2		T8	2
valid_sources[0x7d]	304	1		T8	9		T18	9		T12	2
valid_sources[0x7e]	357	1		T5	2		T8	4		T11	4
valid_sources[0x7f]	378	1		T7	3		T8	4		T22	29
valid_sources[0x80]	340	1		T8	7		T11	1		T13	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

21787

1

T1

1

T2

2

T3

1

values[0x0]

all_enables

biggest_size

18049

1

T1

1

T2

1

T3

1

values[0x1]

all_enables

biggest_size

16614

1

T4

4

T5

216

T6

8