SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[usbdev_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 90929 | 1 | T1 | 3 | T2 | 3 | T3 | 3 | |||
auto[1] | 22573 | 1 | T5 | 520 | T8 | 978 | T9 | 125 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 113376 | 1 | T1 | 3 | T2 | 3 | T3 | 3 | |||
values[1] | 10 | 1 | T18 | 1 | T29 | 2 | T37 | 2 | |||
values[2] | 1 | 1 | T26 | 1 | - | - | - | - | |||
values[3] | 61 | 1 | T18 | 6 | T22 | 3 | T26 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 113393 | 1 | T1 | 3 | T2 | 3 | T3 | 3 | |||
values[1] | 9 | 1 | T18 | 1 | T29 | 2 | T39 | 1 | |||
values[2] | 2 | 1 | T18 | 1 | T39 | 1 | - | - | |||
values[3] | 55 | 1 | T22 | 5 | T26 | 7 | T29 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 113332 | 1 | T1 | 3 | T2 | 3 | T3 | 3 | |||
auto[TlIntgErrCmd] | 61 | 1 | T18 | 5 | T22 | 2 | T26 | 8 | |||
auto[TlIntgErrData] | 44 | 1 | T18 | 2 | T22 | 6 | T26 | 4 | |||
auto[TlIntgErrBoth] | 65 | 1 | T18 | 3 | T22 | 2 | T26 | 8 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |