Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	56075	1		T1	1		T3	1		T4	6
full_word	57427	1		T1	2		T2	3		T3	2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	113332	1		T1	3		T2	3		T3	3
auto[TlIntgErrCmd]	61	1		T18	5		T22	2		T26	8
auto[TlIntgErrData]	44	1		T18	2		T22	6		T26	4
auto[TlIntgErrBoth]	65	1		T18	3		T22	2		T26	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	59537	1		T1	2		T2	2		T3	2
auto[1]	53965	1		T1	1		T2	1		T3	1

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrData]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	37491	1		T1	1		T3	1		T4	4
auto[TlIntgErrNone]	partial	auto[1]	18423	1		T4	2		T5	25		T6	11
auto[TlIntgErrNone]	full_word	auto[0]	21959	1		T1	1		T2	2		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	35459	1		T1	1		T2	1		T3	1
auto[TlIntgErrCmd]	partial	auto[0]	27	1		T18	3		T22	1		T26	4
auto[TlIntgErrCmd]	partial	auto[1]	29	1		T18	2		T22	1		T26	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T64	1		T65	1		T66	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T39	1		T65	1		-	-
auto[TlIntgErrData]	partial	auto[0]	24	1		T18	2		T22	3		T26	3
auto[TlIntgErrData]	partial	auto[1]	19	1		T22	2		T26	1		T29	3
auto[TlIntgErrData]	full_word	auto[0]	1	1		T22	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	30	1		T18	2		T22	1		T26	3
auto[TlIntgErrBoth]	partial	auto[1]	32	1		T18	1		T22	1		T26	4
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T26	1		T67	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	1	1		T67	1		-	-		-	-