Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
72.77	83.19	35.82	89.69		55.17	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	724245	10893	0	0
ep_in_enable_rd_A	724245	786	0	0
ep_out_enable_rd_A	724245	843	0	0
in_iso_rd_A	724245	851	0	0
intr_enable_rd_A	724245	1317	0	0
out_iso_rd_A	724245	925	0	0
phy_config_rd_A	724245	554	0	0
phy_pins_drive_rd_A	724245	854	0	0
rxenable_setup_rd_A	724245	918	0	0
set_nak_out_rd_A	724245	1045	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724245	10893	0	0
T5	2587	4	0	0
T9	2628	3	0	0
T11	3415	597	0	0
T12	2909	7	0	0
T14	2451	6	0	0
T15	4119	638	0	0
T16	4334	679	0	0
T18	13144	6	0	0
T22	9318	1	0	0
T26	12369	5	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724245	786	0	0
T17	1811	0	0	0
T19	0	4	0	0
T20	0	5	0	0
T24	1850	0	0	0
T25	1273	0	0	0
T27	2860	0	0	0
T28	2184	0	0	0
T33	21241	0	0	0
T34	1109	0	0	0
T35	1231	0	0	0
T36	9759	11	0	0
T38	0	89	0	0
T40	0	7	0	0
T41	2404	7	0	0
T44	0	1	0	0
T45	0	38	0	0
T47	0	11	0	0
T59	0	6	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724245	843	0	0
T17	1811	0	0	0
T19	0	3	0	0
T24	1850	0	0	0
T25	1273	0	0	0
T27	2860	0	0	0
T28	2184	0	0	0
T33	21241	0	0	0
T34	1109	0	0	0
T35	1231	0	0	0
T36	9759	16	0	0
T38	0	44	0	0
T40	0	5	0	0
T41	2404	14	0	0
T44	0	2	0	0
T45	0	77	0	0
T47	0	6	0	0
T59	0	8	0	0
T60	0	44	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724245	851	0	0
T17	1811	0	0	0
T19	0	2	0	0
T20	0	2	0	0
T24	1850	0	0	0
T25	1273	0	0	0
T27	2860	0	0	0
T28	2184	0	0	0
T33	21241	0	0	0
T34	1109	0	0	0
T35	1231	0	0	0
T36	9759	45	0	0
T38	0	108	0	0
T40	0	7	0	0
T41	2404	19	0	0
T44	0	5	0	0
T45	0	16	0	0
T47	0	44	0	0
T59	0	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724245	1317	0	0
T17	1811	0	0	0
T19	0	12	0	0
T20	0	3	0	0
T24	1850	14	0	0
T25	1273	0	0	0
T27	2860	0	0	0
T28	2184	0	0	0
T33	21241	0	0	0
T34	1109	0	0	0
T35	1231	0	0	0
T36	9759	17	0	0
T40	0	63	0	0
T41	2404	20	0	0
T44	0	1	0	0
T45	0	48	0	0
T59	0	3	0	0
T61	0	3	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724245	925	0	0
T17	1811	0	0	0
T19	0	12	0	0
T20	0	5	0	0
T24	1850	0	0	0
T25	1273	0	0	0
T27	2860	0	0	0
T28	2184	0	0	0
T33	21241	0	0	0
T34	1109	0	0	0
T35	1231	0	0	0
T36	9759	21	0	0
T38	0	111	0	0
T40	0	2	0	0
T41	2404	32	0	0
T44	0	3	0	0
T45	0	14	0	0
T47	0	44	0	0
T59	0	5	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724245	554	0	0
T17	1811	0	0	0
T19	0	15	0	0
T20	0	2	0	0
T24	1850	0	0	0
T25	1273	0	0	0
T27	2860	0	0	0
T28	2184	0	0	0
T33	21241	0	0	0
T34	1109	0	0	0
T35	1231	0	0	0
T36	9759	11	0	0
T38	0	32	0	0
T40	0	17	0	0
T41	2404	3	0	0
T44	0	7	0	0
T45	0	36	0	0
T47	0	4	0	0
T59	0	9	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724245	854	0	0
T19	6915	5	0	0
T20	0	1	0	0
T36	9759	28	0	0
T38	0	78	0	0
T40	3093	6	0	0
T42	2804	0	0	0
T43	2715	0	0	0
T44	2122	25	0	0
T45	0	68	0	0
T47	0	26	0	0
T54	1913	0	0	0
T55	5099	0	0	0
T59	0	3	0	0
T60	0	40	0	0
T62	1191	0	0	0
T63	17491	0	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724245	918	0	0
T17	1811	0	0	0
T19	0	7	0	0
T20	0	3	0	0
T24	1850	0	0	0
T25	1273	0	0	0
T27	2860	0	0	0
T28	2184	0	0	0
T33	21241	0	0	0
T34	1109	0	0	0
T35	1231	0	0	0
T36	9759	27	0	0
T38	0	160	0	0
T40	0	31	0	0
T41	2404	5	0	0
T45	0	44	0	0
T47	0	52	0	0
T59	0	7	0	0
T60	0	2	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724245	1045	0	0
T17	1811	0	0	0
T19	0	10	0	0
T20	0	1	0	0
T24	1850	0	0	0
T25	1273	0	0	0
T27	2860	0	0	0
T28	2184	0	0	0
T30	0	3	0	0
T33	21241	0	0	0
T34	1109	0	0	0
T35	1231	0	0	0
T36	9759	42	0	0
T38	0	174	0	0
T40	0	1	0	0
T41	2404	2	0	0
T44	0	7	0	0
T45	0	43	0	0
T47	0	46	0	0