Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
72.77	83.19	35.82	89.69		55.17	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	758019	10515	0	0
ep_in_enable_rd_A	758019	925	0	0
ep_out_enable_rd_A	758019	905	0	0
in_iso_rd_A	758019	1141	0	0
intr_enable_rd_A	758019	1205	0	0
out_iso_rd_A	758019	869	0	0
phy_config_rd_A	758019	581	0	0
phy_pins_drive_rd_A	758019	962	0	0
rxenable_setup_rd_A	758019	762	0	0
set_nak_out_rd_A	758019	967	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758019	10515	0	0
T8	12284	7	0	0
T11	6345	361	0	0
T12	1865	194	0	0
T16	2204	7	0	0
T17	2864	474	0	0
T18	2107	4	0	0
T19	2257	1	0	0
T20	0	267	0	0
T21	7497	0	0	0
T22	1852	0	0	0
T41	1938	0	0	0
T42	0	4	0	0
T44	0	3	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758019	925	0	0
T17	2864	0	0	0
T18	2107	0	0	0
T19	2257	0	0	0
T21	7497	61	0	0
T22	1852	0	0	0
T33	1424	0	0	0
T34	1346	0	0	0
T41	1938	0	0	0
T44	0	156	0	0
T45	5905	0	0	0
T56	0	13	0	0
T63	0	318	0	0
T64	0	10	0	0
T65	0	16	0	0
T66	0	5	0	0
T67	0	55	0	0
T68	0	34	0	0
T69	0	5	0	0
T70	17758	0	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758019	905	0	0
T10	3652	44	0	0
T17	2864	0	0	0
T18	2107	0	0	0
T19	2257	0	0	0
T21	7497	47	0	0
T22	1852	0	0	0
T33	1424	0	0	0
T34	1346	0	0	0
T41	1938	0	0	0
T44	0	127	0	0
T56	0	44	0	0
T63	0	224	0	0
T64	0	18	0	0
T65	0	31	0	0
T66	0	1	0	0
T67	0	8	0	0
T68	0	55	0	0
T70	17758	0	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758019	1141	0	0
T10	3652	8	0	0
T17	2864	0	0	0
T18	2107	0	0	0
T19	2257	0	0	0
T21	7497	34	0	0
T22	1852	0	0	0
T28	0	1	0	0
T33	1424	0	0	0
T34	1346	0	0	0
T35	2873	6	0	0
T41	1938	0	0	0
T44	0	175	0	0
T56	0	77	0	0
T63	0	353	0	0
T65	0	32	0	0
T66	0	4	0	0
T67	0	65	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758019	1205	0	0
T10	3652	3	0	0
T16	2204	0	0	0
T17	2864	0	0	0
T18	2107	0	0	0
T19	2257	0	0	0
T21	7497	29	0	0
T22	1852	0	0	0
T32	1431	21	0	0
T33	1424	8	0	0
T41	1938	0	0	0
T44	0	113	0	0
T56	0	41	0	0
T63	0	290	0	0
T64	0	50	0	0
T71	0	9	0	0
T72	0	9	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758019	869	0	0
T10	3652	6	0	0
T17	2864	0	0	0
T18	2107	0	0	0
T19	2257	0	0	0
T21	7497	32	0	0
T22	1852	0	0	0
T28	0	4	0	0
T33	1424	0	0	0
T34	1346	0	0	0
T35	2873	25	0	0
T41	1938	0	0	0
T44	0	88	0	0
T56	0	47	0	0
T63	0	260	0	0
T64	0	35	0	0
T65	0	6	0	0
T66	0	5	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758019	581	0	0
T10	3652	10	0	0
T17	2864	0	0	0
T18	2107	0	0	0
T19	2257	0	0	0
T21	7497	30	0	0
T22	1852	0	0	0
T33	1424	0	0	0
T34	1346	0	0	0
T35	2873	3	0	0
T36	0	9	0	0
T40	0	2	0	0
T41	1938	0	0	0
T44	0	38	0	0
T56	0	93	0	0
T63	0	104	0	0
T64	0	31	0	0
T65	0	20	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758019	962	0	0
T10	3652	45	0	0
T17	2864	0	0	0
T18	2107	0	0	0
T19	2257	0	0	0
T21	7497	30	0	0
T22	1852	0	0	0
T33	1424	0	0	0
T34	1346	0	0	0
T41	1938	0	0	0
T44	0	137	0	0
T56	0	84	0	0
T63	0	252	0	0
T64	0	44	0	0
T65	0	10	0	0
T66	0	6	0	0
T67	0	4	0	0
T68	0	67	0	0
T70	17758	0	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758019	762	0	0
T10	3652	7	0	0
T17	2864	0	0	0
T18	2107	0	0	0
T19	2257	0	0	0
T21	7497	51	0	0
T22	1852	0	0	0
T33	1424	0	0	0
T34	1346	0	0	0
T35	2873	24	0	0
T41	1938	0	0	0
T44	0	118	0	0
T56	0	39	0	0
T63	0	101	0	0
T64	0	12	0	0
T65	0	32	0	0
T66	0	5	0	0
T67	0	2	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	758019	967	0	0
T10	3652	4	0	0
T17	2864	0	0	0
T18	2107	0	0	0
T19	2257	0	0	0
T21	7497	54	0	0
T22	1852	0	0	0
T33	1424	0	0	0
T34	1346	0	0	0
T36	0	2	0	0
T41	1938	0	0	0
T44	0	149	0	0
T56	0	54	0	0
T63	0	299	0	0
T64	0	10	0	0
T65	0	26	0	0
T66	0	6	0	0
T67	0	5	0	0
T70	17758	0	0	0