Unified Coverage Report :: Module :: usbdev

Module : usbdev

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.77	83.19	35.82	89.69		55.17	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	72.77	83.19	35.82	89.69		55.17	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.77	83.19	35.82	89.69		55.17	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.86	90.01	75.82	95.05	3.12	87.16	92.01

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_event	100.00	100.00				100.00
gen_no_stubbed_memory.u_memory_2p	41.00	59.57	33.33			60.00	11.11
gen_no_stubbed_memory.u_tlul2sram	59.32	72.69	42.74			50.00	71.88
i_usbdev_iomux	48.61	88.89	22.22			83.33	0.00
intr_av_empty	81.25	100.00	25.00			100.00	100.00
intr_av_overflow	81.25	100.00	25.00			100.00	100.00
intr_disconnected	89.58	100.00	58.33			100.00	100.00
intr_frame	81.25	100.00	25.00			100.00	100.00
intr_host_lost	81.25	100.00	25.00			100.00	100.00
intr_hw_pkt_received	81.25	100.00	25.00			100.00	100.00
intr_hw_pkt_sent	81.25	100.00	25.00			100.00	100.00
intr_link_in_err	81.25	100.00	25.00			100.00	100.00
intr_link_out_err	81.25	100.00	25.00			100.00	100.00
intr_link_reset	81.25	100.00	25.00			100.00	100.00
intr_link_resume	81.25	100.00	25.00			100.00	100.00
intr_link_suspend	81.25	100.00	25.00			100.00	100.00
intr_powered	89.58	100.00	58.33			100.00	100.00
intr_rx_bitstuff_err	81.25	100.00	25.00			100.00	100.00
intr_rx_crc_err	81.25	100.00	25.00			100.00	100.00
intr_rx_full	81.25	100.00	25.00			100.00	100.00
intr_rx_pid_err	81.25	100.00	25.00			100.00	100.00
tlul_assert_device	95.24	100.00				85.71	100.00
u_reg	95.52	98.33	93.82	100.00		98.34	87.10
usbdev_avfifo	60.10	82.50	41.67			56.25	60.00
usbdev_csr_assert	100.00						100.00
usbdev_impl	49.73	63.04	35.12		3.12	47.38	100.00
usbdev_rxfifo	60.72	85.00	42.31			55.56	60.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : usbdev

	Line No.	Total	Covered	Percent
TOTAL		113	94	83.19
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	190	1	1	100.00
ALWAYS	192	5	5	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	220	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	245	1	0	0.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	278	1	0	0.00
ALWAYS	301	0	0
ALWAYS	301	3	3	100.00
ALWAYS	309	0	0
ALWAYS	309	4	4	100.00
ALWAYS	318	0	0
ALWAYS	318	3	3	100.00
ALWAYS	325	0	0
ALWAYS	325	3	3	100.00
ALWAYS	332	0	0
ALWAYS	332	3	3	100.00
ALWAYS	339	0	0
ALWAYS	339	2	2	100.00
ALWAYS	345	3	3	100.00
ALWAYS	352	3	2	66.67
ALWAYS	359	0	0
ALWAYS	359	3	0	0.00
ALWAYS	368	3	3	100.00
ALWAYS	380	3	2	66.67
ALWAYS	387	0	0
ALWAYS	387	3	0	0.00
ALWAYS	394	10	5	50.00
ALWAYS	412	0	0
ALWAYS	412	3	3	100.00
ALWAYS	420	0	0
ALWAYS	420	3	3	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	530	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	533	1	1	100.00
CONT_ASSIGN	534	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	555	1	1	100.00
ALWAYS	561	0	0
ALWAYS	561	8	6	75.00
CONT_ASSIGN	692	1	1	100.00
CONT_ASSIGN	693	1	1	100.00
CONT_ASSIGN	697	1	1	100.00
CONT_ASSIGN	947	1	1	100.00
CONT_ASSIGN	948	1	1	100.00
CONT_ASSIGN	949	1	1	100.00
CONT_ASSIGN	950	1	1	100.00
CONT_ASSIGN	990	1	1	100.00
CONT_ASSIGN	993	1	1	100.00
CONT_ASSIGN	1002	1	1	100.00
ALWAYS	1005	5	3	60.00
ALWAYS	1014	3	3	100.00
CONT_ASSIGN	1027	1	1	100.00
CONT_ASSIGN	1030	1	1	100.00
CONT_ASSIGN	1037	1	1	100.00
ALWAYS	1041	3	3	100.00
CONT_ASSIGN	1048	1	1	100.00
CONT_ASSIGN	1053	1	1	100.00
CONT_ASSIGN	1055	1	1	100.00
CONT_ASSIGN	1063	0	0
CONT_ASSIGN	1065	0	0
CONT_ASSIGN	1067	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
118	1	1
190	1	1
192	1	1
193	1	1
195	1	1
196	1	1
198	1	1
219	1	1
220	1	1
221	1	1
245	0	1
270	1	1
271	1	1
272	1	1
273	1	1
274	1	1
278	0	1
301	1	1
302	1	1
303	1	1
309	1	1
310	1	1
311	1	1
312	1	1
318	1	1
319	1	1
320	1	1
325	1	1
326	1	1
327	1	1
332	1	1
333	1	1
334	1	1
339	1	1
340	1	1
345	1	1
346	1	1
347	1	1
352	1	1
353	1	1
354	0	1
			MISSING_ELSE
359	0	1
360	0	1
361	0	1
368	1	1
369	1	1
370	1	1
380	1	1
381	1	1
382	0	1
			MISSING_ELSE
387	0	1
388	0	1
389	0	1
394	1	1
395	1	1
396	1	1
397	0	1
398	0	1
400	1	1
402	0	1
403	0	1
404	1	1
406	0	1
			MISSING_ELSE
412	1	1
413	1	1
414	1	1
420	1	1
421	1	1
422	1	1
429	1	1
430	1	1
431	1	1
530	1	1
531	1	1
533	1	1
534	1	1
552	1	1
555	1	1
561	1	1
562	1	1
563	1	1
564	1	1
565	0	1
566	0	1
568	1	1
569	1	1
692	1	1
693	1	1
697	1	1
947	1	1
948	1	1
949	1	1
950	1	1
990	1	1
993	1	1
1002	1	1
1005	1	1
1006	1	1
1007	0	1
1008	1	1
1009	0	1
			MISSING_ELSE
1014	1	1
1015	1	1
1017	1	1
1027	1	1
1030	1	1
1037	1	1
1041	1	1
1042	1	1
1044	1	1
1048	1	1
1053	1	1
1055	1	1
1063		unreachable
1065		unreachable
1067		unreachable

---

Cond Coverage for Module : usbdev

	Total	Covered	Percent
Conditions	67	24	35.82
Logical	67	24	35.82
Non-Logical	0	0
Event	0	0

 LINE       190
 EXPRESSION (ns_cnt == 6'd47)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       219
 EXPRESSION (connect_en & ((~av_rvalid)))
             -----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       220
 EXPRESSION (reg2hw.avbuffer.qe & ((~av_fifo_wready)))
             ---------1--------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       221
 EXPRESSION (connect_en & ((~rx_fifo_rvalid)))
             -----1----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       245
 EXPRESSION (reg2hw.rxfifo.ep.re | reg2hw.rxfifo.setup.re | reg2hw.rxfifo.size.re | reg2hw.rxfifo.buffer.re)
             ---------1---------   -----------2----------   ----------3----------   -----------4-----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Not Covered

 LINE       347
 EXPRESSION (reg2hw.data_toggle_clear[i].q & reg2hw.data_toggle_clear[i].qe)
             --------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       353
 EXPRESSION (in_ep_xact_end && in_endpoint_val)
             -------1------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Not Covered

 LINE       381
 EXPRESSION (rx_wvalid && out_endpoint_val)
             ----1----    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Not Covered

 LINE       400
 EXPRESSION (setup_received & out_endpoint_val)
             -------1------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Not Covered

 LINE       404
 EXPRESSION (in_ep_xact_end & in_endpoint_val)
             -------1------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Not Covered

 LINE       422
 EXPRESSION (reg2hw.configin[i].rdy.q | reg2hw.configin[i].pend.q)
             ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       430
 EXPRESSION (cfg_pinflip ? 1'b0 : usb_pullup_en)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       431
 EXPRESSION (((!cfg_pinflip)) ? 1'b0 : usb_pullup_en)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       534
 EXPRESSION (reg2hw.usbctrl.resume_link_active.qe & reg2hw.usbctrl.resume_link_active.q)
             ------------------1-----------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       697
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       993
 EXPRESSION (use_diff_rcvr & ((~link_suspend)))
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       1002
 EXPRESSION (usb_rcvr_ok_counter_q == '0)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1006
 EXPRESSION (use_diff_rcvr & ((!usb_rx_enable_o)))
             ------1------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       1008
 EXPRESSION (us_tick && (usb_rcvr_ok_counter_q > '0))
             ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       1030
 EXPRESSION (usb_ref_disable ? 1'b0 : event_sof)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       1037
 EXPRESSION (usb_ref_pulse_o ? 1'b1 : ((((!link_active)) || host_lost || usb_ref_disable) ? 1'b0 : usb_ref_val_q))
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       1037
 SUB-EXPRESSION ((((!link_active)) || host_lost || usb_ref_disable) ? 1'b0 : usb_ref_val_q)
                 -------------------------1------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       1037
 SUB-EXPRESSION (((!link_active)) || host_lost || usb_ref_disable)
                 --------1-------    ----2----    -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Covered	T1,T2,T3

 LINE       1053
 EXPRESSION (reg2hw.wake_control.suspend_req.qe & reg2hw.wake_control.suspend_req.q)
             -----------------1----------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1055
 EXPRESSION (reg2hw.wake_control.wake_ack.qe & reg2hw.wake_control.wake_ack.q)
             ---------------1---------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Toggle Coverage for Module : usbdev

	Total	Covered	Percent
Totals	71	60	84.51
Total Bits	446	400	89.69
Total Bits 0->1	223	200	89.69
Total Bits 1->0	223	200	89.69

Ports	71	60	84.51
Port Bits	446	400	89.69
Port Bits 0->1	223	200	89.69
Port Bits 1->0	223	200	89.69

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_aon_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_aon_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T3,T6	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T3,T6	Yes	T1,T3,T6	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T5	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T5	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T8,T11,T12	Yes	T8,T11,T12	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T6,T7,T8	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T4,T6	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cio_usb_dp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_usb_dn_i	Yes	Yes	T1,T2,T3	Yes	T7,T8,T9	INPUT
usb_rx_d_i	No	No		No		INPUT
cio_usb_dp_o	Yes	Yes	T6,T7,T8	Yes	T7,T8,T9	OUTPUT
cio_usb_dp_en_o	Yes	Yes	T8,T23,T16	Yes	T7,T8,T9	OUTPUT
cio_usb_dn_o	Yes	Yes	T7,T8,T9	Yes	T6,T7,T8	OUTPUT
cio_usb_dn_en_o	Yes	Yes	T8,T23,T16	Yes	T7,T8,T9	OUTPUT
usb_tx_se0_o	Yes	Yes	T24,T25	Yes	T24,T25	OUTPUT
usb_tx_d_o	Yes	Yes	T6,T7,T8	Yes	T7,T8,T9	OUTPUT
cio_sense_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
usb_dp_pullup_o	Yes	Yes	T26,T24,T25	Yes	T26,T24,T25	OUTPUT
usb_dn_pullup_o	Yes	Yes	T27,T28,T24	Yes	T27,T28,T24	OUTPUT
usb_rx_enable_o	Yes	Yes	T8,T10,T29	Yes	T6,T7,T8	OUTPUT
usb_tx_use_d_se0_o	Yes	Yes	T8,T30,T23	Yes	T8,T9,T10	OUTPUT
usb_aon_suspend_req_o	Yes	Yes	T27,T26,T24	Yes	T27,T26,T24	OUTPUT
usb_aon_wake_ack_o	Yes	Yes	T7,T8,T10	Yes	T7,T8,T10	OUTPUT
usb_aon_bus_reset_i	Unreachable	Unreachable		Unreachable		INPUT
usb_aon_sense_lost_i	Unreachable	Unreachable		Unreachable		INPUT
usb_aon_wake_detect_active_i	Unreachable	Unreachable		Unreachable		INPUT
usb_ref_val_o	No	No		No		OUTPUT
usb_ref_pulse_o	No	No		No		OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.b_ram_lcfg.cfg_en	No	No		No		INPUT
ram_cfg_i.a_ram_lcfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.a_ram_lcfg.cfg_en	No	No		No		INPUT
ram_cfg_i.b_ram_fcfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.b_ram_fcfg.cfg_en	No	No		No		INPUT
ram_cfg_i.a_ram_fcfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.a_ram_fcfg.cfg_en	No	No		No		INPUT
intr_pkt_received_o	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
intr_pkt_sent_o	Yes	Yes	T31,T32,T22	Yes	T31,T32,T22	OUTPUT
intr_powered_o	Yes	Yes	T8,T29,T23	Yes	T6,T7,T8	OUTPUT
intr_disconnected_o	Yes	Yes	T8,T23,T32	Yes	T7,T8,T29	OUTPUT
intr_host_lost_o	Yes	Yes	T31,T33,T34	Yes	T31,T33,T34	OUTPUT
intr_link_reset_o	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
intr_link_suspend_o	Yes	Yes	T31,T32,T22	Yes	T31,T32,T22	OUTPUT
intr_link_resume_o	Yes	Yes	T32,T22,T33	Yes	T32,T22,T33	OUTPUT
intr_av_empty_o	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
intr_rx_full_o	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
intr_av_overflow_o	Yes	Yes	T31,T33,T34	Yes	T31,T33,T34	OUTPUT
intr_link_in_err_o	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	OUTPUT
intr_link_out_err_o	Yes	Yes	T31,T32,T34	Yes	T31,T32,T34	OUTPUT
intr_rx_crc_err_o	Yes	Yes	T31,T32,T34	Yes	T31,T32,T34	OUTPUT
intr_rx_pid_err_o	Yes	Yes	T31,T32,T22	Yes	T31,T32,T22	OUTPUT
intr_rx_bitstuff_err_o	Yes	Yes	T31,T32,T22	Yes	T31,T32,T22	OUTPUT
intr_frame_o	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : usbdev

	Line No.	Total	Covered	Percent
Branches		29	16	55.17
TERNARY	430	2	1	50.00
TERNARY	431	2	1	50.00
TERNARY	1030	2	1	50.00
TERNARY	1037	3	1	33.33
IF	192	3	3	100.00
IF	353	2	1	50.00
IF	381	2	1	50.00
IF	396	4	1	25.00
IF	564	2	1	50.00
IF	1006	3	1	33.33
IF	1014	2	2	100.00
IF	1041	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	430	(cfg_pinflip) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	431	((!cfg_pinflip)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	1030	(usb_ref_disable) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1037	(usb_ref_pulse_o) ? 
-2-:	1037	((((!link_active) || host_lost) || usb_ref_disable)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	192	if ((!rst_n))
-2-:	195	if (us_tick)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	353	if ((in_ep_xact_end && in_endpoint_val))

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	381	if ((rx_wvalid && out_endpoint_val))

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	if (event_link_reset)
-2-:	400	if ((setup_received & out_endpoint_val))
-3-:	404	if ((in_ep_xact_end & in_endpoint_val))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	564	if (((setup_received && out_endpoint_val) && (out_endpoint == 4'((unsigned'(i))))))

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1006	if ((use_diff_rcvr & (!usb_rx_enable_o)))
-2-:	1008	if ((us_tick && (usb_rcvr_ok_counter_q > '0)))

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1014	if ((!rst_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1041	if ((!rst_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : usbdev

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	34	34	100.00	34	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	34	34	100.00	34	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertsKnown_A	41333	34298	0	0
CIODnEnKnown_A	41333	34298	0	0
CIODnKnown_A	41333	34298	0	0
CIODpEnKnown_A	41333	34298	0	0
CIODpKnown_A	41333	34298	0	0
FpvSecCmRegWeOnehotCheck_A	41333	90	0	0
TlOAReadyKnown_A	41333	34298	0	0
TlODValidKnown_A	41333	34298	0	0
USBAonSuspendReqKnown_A	41333	34298	0	0
USBAonWakeAckKnown_A	41333	34298	0	0
USBDnPUKnown_A	41333	34298	0	0
USBDpPUKnown_A	41333	34298	0	0
USBIntrAvEmptyKnown_A	41333	34298	0	0
USBIntrAvOverKnown_A	41333	34298	0	0
USBIntrDisConKnown_A	41333	34298	0	0
USBIntrFrameKnown_A	41333	34298	0	0
USBIntrHostLostKnown_A	41333	34298	0	0
USBIntrLinkInErrKnown_A	41333	34298	0	0
USBIntrLinkOutErrKnown_A	41333	34298	0	0
USBIntrLinkResKnown_A	41333	34298	0	0
USBIntrLinkRstKnown_A	41333	34298	0	0
USBIntrLinkSusKnown_A	41333	34298	0	0
USBIntrPktRcvdKnown_A	41333	34298	0	0
USBIntrPktSentKnown_A	41333	34298	0	0
USBIntrPwrdKnown_A	41333	34298	0	0
USBIntrRxBitstuffErrKnown_A	41333	34298	0	0
USBIntrRxCrCErrKnown_A	41333	34298	0	0
USBIntrRxFullKnown_A	41333	34298	0	0
USBIntrRxPidErrKnown_A	41333	34298	0	0
USBRefPulseKnown_A	41333	34298	0	0
USBRefValKnown_A	41333	34298	0	0
USBRxEnableKnown_A	41333	34298	0	0
USBTxDKnown_A	41333	34298	0	0
USBTxSe0Known_A	41333	34298	0	0

AlertsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41333	34298	0	0
T1	8021	6471	0	0
T2	8364	6881	0	0
T3	7523	6055	0	0
T4	8651	7779	0	0
T5	8774	7112	0	0

CIODnEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41333	34298	0	0
T1	8021	6471	0	0
T2	8364	6881	0	0
T3	7523	6055	0	0
T4	8651	7779	0	0
T5	8774	7112	0	0

CIODnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41333	34298	0	0
T1	8021	6471	0	0
T2	8364	6881	0	0
T3	7523	6055	0	0
T4	8651	7779	0	0
T5	8774	7112	0	0

CIODpEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41333	34298	0	0
T1	8021	6471	0	0
T2	8364	6881	0	0
T3	7523	6055	0	0
T4	8651	7779	0	0
T5	8774	7112	0	0

CIODpKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41333	34298	0	0
T1	8021	6471	0	0
T2	8364	6881	0	0
T3	7523	6055	0	0
T4	8651	7779	0	0
T5	8774	7112	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41333	90	0	0
T1	8021	20	0	0
T2	8364	20	0	0
T3	7523	20	0	0
T4	8651	10	0	0
T5	8774	20	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41333	34298	0	0
T1	8021	6471	0	0
T2	8364	6881	0	0
T3	7523	6055	0	0
T4	8651	7779	0	0
T5	8774	7112	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41333	34298	0	0
T1	8021	6471	0	0
T2	8364	6881	0	0
T3	7523	6055	0	0
T4	8651	7779	0	0
T5	8774	7112	0	0

USBAonSuspendReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41333	34298	0	0
T1	8021	6471	0	0
T2	8364	6881	0	0
T3	7523	6055	0	0
T4	8651	7779	0	0
T5	8774	7112	0	0

USBAonWakeAckKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41333	34298	0	0
T1	8021	6471	0	0
T2	8364	6881	0	0
T3	7523	6055	0	0
T4	8651	7779	0	0
T5	8774	7112	0	0

USBDnPUKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41333	34298	0	0
T1	8021	6471	0	0
T2	8364	6881	0	0
T3	7523	6055	0	0
T4	8651	7779	0	0
T5	8774	7112	0	0

USBDpPUKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41333	34298	0	0
T1	8021	6471	0	0
T2	8364	6881	0	0
T3	7523	6055	0	0
T4	8651	7779	0	0
T5	8774	7112	0	0

USBIntrAvEmptyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41333	34298	0	0
T1	8021	6471	0	0
T2	8364	6881	0	0
T3	7523	6055	0	0
T4	8651	7779	0	0
T5	8774	7112	0	0

USBIntrAvOverKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41333	34298	0	0
T1	8021	6471	0	0
T2	8364	6881	0	0
T3	7523	6055	0	0
T4	8651	7779	0	0
T5	8774	7112	0	0

USBIntrDisConKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41333	34298	0	0
T1	8021	6471	0	0
T2	8364	6881	0	0
T3	7523	6055	0	0
T4	8651	7779	0	0
T5	8774	7112	0	0

USBIntrFrameKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41333	34298	0	0
T1	8021	6471	0	0
T2	8364	6881	0	0
T3	7523	6055	0	0
T4	8651	7779	0	0
T5	8774	7112	0	0

USBIntrHostLostKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41333	34298	0	0
T1	8021	6471	0	0
T2	8364	6881	0	0
T3	7523	6055	0	0
T4	8651	7779	0	0
T5	8774	7112	0	0

USBIntrLinkInErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41333	34298	0	0
T1	8021	6471	0	0
T2	8364	6881	0	0
T3	7523	6055	0	0
T4	8651	7779	0	0
T5	8774	7112	0	0

USBIntrLinkOutErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41333	34298	0	0
T1	8021	6471	0	0
T2	8364	6881	0	0
T3	7523	6055	0	0
T4	8651	7779	0	0
T5	8774	7112	0	0

USBIntrLinkResKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41333	34298	0	0
T1	8021	6471	0	0
T2	8364	6881	0	0
T3	7523	6055	0	0
T4	8651	7779	0	0
T5	8774	7112	0	0

USBIntrLinkRstKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41333	34298	0	0
T1	8021	6471	0	0
T2	8364	6881	0	0
T3	7523	6055	0	0
T4	8651	7779	0	0
T5	8774	7112	0	0

USBIntrLinkSusKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41333	34298	0	0
T1	8021	6471	0	0
T2	8364	6881	0	0
T3	7523	6055	0	0
T4	8651	7779	0	0
T5	8774	7112	0	0

USBIntrPktRcvdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41333	34298	0	0
T1	8021	6471	0	0
T2	8364	6881	0	0
T3	7523	6055	0	0
T4	8651	7779	0	0
T5	8774	7112	0	0

USBIntrPktSentKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41333	34298	0	0
T1	8021	6471	0	0
T2	8364	6881	0	0
T3	7523	6055	0	0
T4	8651	7779	0	0
T5	8774	7112	0	0

USBIntrPwrdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41333	34298	0	0
T1	8021	6471	0	0
T2	8364	6881	0	0
T3	7523	6055	0	0
T4	8651	7779	0	0
T5	8774	7112	0	0

USBIntrRxBitstuffErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41333	34298	0	0
T1	8021	6471	0	0
T2	8364	6881	0	0
T3	7523	6055	0	0
T4	8651	7779	0	0
T5	8774	7112	0	0

USBIntrRxCrCErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41333	34298	0	0
T1	8021	6471	0	0
T2	8364	6881	0	0
T3	7523	6055	0	0
T4	8651	7779	0	0
T5	8774	7112	0	0

USBIntrRxFullKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41333	34298	0	0
T1	8021	6471	0	0
T2	8364	6881	0	0
T3	7523	6055	0	0
T4	8651	7779	0	0
T5	8774	7112	0	0

USBIntrRxPidErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41333	34298	0	0
T1	8021	6471	0	0
T2	8364	6881	0	0
T3	7523	6055	0	0
T4	8651	7779	0	0
T5	8774	7112	0	0

USBRefPulseKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41333	34298	0	0
T1	8021	6471	0	0
T2	8364	6881	0	0
T3	7523	6055	0	0
T4	8651	7779	0	0
T5	8774	7112	0	0

USBRefValKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41333	34298	0	0
T1	8021	6471	0	0
T2	8364	6881	0	0
T3	7523	6055	0	0
T4	8651	7779	0	0
T5	8774	7112	0	0

USBRxEnableKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41333	34298	0	0
T1	8021	6471	0	0
T2	8364	6881	0	0
T3	7523	6055	0	0
T4	8651	7779	0	0
T5	8774	7112	0	0

USBTxDKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41333	34298	0	0
T1	8021	6471	0	0
T2	8364	6881	0	0
T3	7523	6055	0	0
T4	8651	7779	0	0
T5	8774	7112	0	0

USBTxSe0Known_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41333	34298	0	0
T1	8021	6471	0	0
T2	8364	6881	0	0
T3	7523	6055	0	0
T4	8651	7779	0	0
T5	8774	7112	0	0