Unified Coverage Report :: Module :: usbdev_reg_top

Module : usbdev_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.60	99.72	98.70			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	99.60	99.72	98.70			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.60	99.72	98.70			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.47	98.33	93.60	100.00		98.34	87.10

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
72.77	83.19	35.82	89.69		55.17	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_avbuffer	100.00	100.00	100.00			100.00
u_avbuffer0_qe	100.00	100.00				100.00
u_chk	100.00	100.00		100.00			100.00
u_configin_0_buffer_0	100.00	100.00	100.00			100.00
u_configin_0_pend_0	94.44	100.00	83.33			100.00
u_configin_0_rdy_0	100.00	100.00	100.00			100.00
u_configin_0_size_0	100.00	100.00	100.00			100.00
u_configin_10_buffer_10	100.00	100.00	100.00			100.00
u_configin_10_pend_10	94.44	100.00	83.33			100.00
u_configin_10_rdy_10	100.00	100.00	100.00			100.00
u_configin_10_size_10	100.00	100.00	100.00			100.00
u_configin_11_buffer_11	100.00	100.00	100.00			100.00
u_configin_11_pend_11	94.44	100.00	83.33			100.00
u_configin_11_rdy_11	100.00	100.00	100.00			100.00
u_configin_11_size_11	100.00	100.00	100.00			100.00
u_configin_1_buffer_1	100.00	100.00	100.00			100.00
u_configin_1_pend_1	94.44	100.00	83.33			100.00
u_configin_1_rdy_1	100.00	100.00	100.00			100.00
u_configin_1_size_1	100.00	100.00	100.00			100.00
u_configin_2_buffer_2	100.00	100.00	100.00			100.00
u_configin_2_pend_2	94.44	100.00	83.33			100.00
u_configin_2_rdy_2	100.00	100.00	100.00			100.00
u_configin_2_size_2	100.00	100.00	100.00			100.00
u_configin_3_buffer_3	100.00	100.00	100.00			100.00
u_configin_3_pend_3	94.44	100.00	83.33			100.00
u_configin_3_rdy_3	100.00	100.00	100.00			100.00
u_configin_3_size_3	100.00	100.00	100.00			100.00
u_configin_4_buffer_4	100.00	100.00	100.00			100.00
u_configin_4_pend_4	94.44	100.00	83.33			100.00
u_configin_4_rdy_4	100.00	100.00	100.00			100.00
u_configin_4_size_4	100.00	100.00	100.00			100.00
u_configin_5_buffer_5	100.00	100.00	100.00			100.00
u_configin_5_pend_5	94.44	100.00	83.33			100.00
u_configin_5_rdy_5	100.00	100.00	100.00			100.00
u_configin_5_size_5	100.00	100.00	100.00			100.00
u_configin_6_buffer_6	100.00	100.00	100.00			100.00
u_configin_6_pend_6	94.44	100.00	83.33			100.00
u_configin_6_rdy_6	100.00	100.00	100.00			100.00
u_configin_6_size_6	100.00	100.00	100.00			100.00
u_configin_7_buffer_7	100.00	100.00	100.00			100.00
u_configin_7_pend_7	94.44	100.00	83.33			100.00
u_configin_7_rdy_7	100.00	100.00	100.00			100.00
u_configin_7_size_7	100.00	100.00	100.00			100.00
u_configin_8_buffer_8	100.00	100.00	100.00			100.00
u_configin_8_pend_8	94.44	100.00	83.33			100.00
u_configin_8_rdy_8	100.00	100.00	100.00			100.00
u_configin_8_size_8	100.00	100.00	100.00			100.00
u_configin_9_buffer_9	100.00	100.00	100.00			100.00
u_configin_9_pend_9	94.44	100.00	83.33			100.00
u_configin_9_rdy_9	100.00	100.00	100.00			100.00
u_configin_9_size_9	100.00	100.00	100.00			100.00
u_data_toggle_clear0_qe	100.00	100.00				100.00
u_data_toggle_clear_clear_0	100.00	100.00	100.00			100.00
u_data_toggle_clear_clear_1	100.00	100.00	100.00			100.00
u_data_toggle_clear_clear_10	100.00	100.00	100.00			100.00
u_data_toggle_clear_clear_11	100.00	100.00	100.00			100.00
u_data_toggle_clear_clear_2	100.00	100.00	100.00			100.00
u_data_toggle_clear_clear_3	100.00	100.00	100.00			100.00
u_data_toggle_clear_clear_4	100.00	100.00	100.00			100.00
u_data_toggle_clear_clear_5	100.00	100.00	100.00			100.00
u_data_toggle_clear_clear_6	100.00	100.00	100.00			100.00
u_data_toggle_clear_clear_7	100.00	100.00	100.00			100.00
u_data_toggle_clear_clear_8	100.00	100.00	100.00			100.00
u_data_toggle_clear_clear_9	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_0	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_1	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_10	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_11	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_2	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_3	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_4	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_5	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_6	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_7	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_8	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_9	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_0	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_1	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_10	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_11	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_2	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_3	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_4	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_5	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_6	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_7	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_8	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_9	100.00	100.00	100.00			100.00
u_in_iso_iso_0	100.00	100.00	100.00			100.00
u_in_iso_iso_1	100.00	100.00	100.00			100.00
u_in_iso_iso_10	100.00	100.00	100.00			100.00
u_in_iso_iso_11	100.00	100.00	100.00			100.00
u_in_iso_iso_2	100.00	100.00	100.00			100.00
u_in_iso_iso_3	100.00	100.00	100.00			100.00
u_in_iso_iso_4	100.00	100.00	100.00			100.00
u_in_iso_iso_5	100.00	100.00	100.00			100.00
u_in_iso_iso_6	100.00	100.00	100.00			100.00
u_in_iso_iso_7	100.00	100.00	100.00			100.00
u_in_iso_iso_8	100.00	100.00	100.00			100.00
u_in_iso_iso_9	100.00	100.00	100.00			100.00
u_in_sent_sent_0	88.89	100.00	66.67			100.00
u_in_sent_sent_1	88.89	100.00	66.67			100.00
u_in_sent_sent_10	88.89	100.00	66.67			100.00
u_in_sent_sent_11	88.89	100.00	66.67			100.00
u_in_sent_sent_2	88.89	100.00	66.67			100.00
u_in_sent_sent_3	88.89	100.00	66.67			100.00
u_in_sent_sent_4	88.89	100.00	66.67			100.00
u_in_sent_sent_5	88.89	100.00	66.67			100.00
u_in_sent_sent_6	88.89	100.00	66.67			100.00
u_in_sent_sent_7	88.89	100.00	66.67			100.00
u_in_sent_sent_8	88.89	100.00	66.67			100.00
u_in_sent_sent_9	88.89	100.00	66.67			100.00
u_in_stall_endpoint_0	96.30	100.00	88.89			100.00
u_in_stall_endpoint_1	96.30	100.00	88.89			100.00
u_in_stall_endpoint_10	96.30	100.00	88.89			100.00
u_in_stall_endpoint_11	96.30	100.00	88.89			100.00
u_in_stall_endpoint_2	96.30	100.00	88.89			100.00
u_in_stall_endpoint_3	96.30	100.00	88.89			100.00
u_in_stall_endpoint_4	96.30	100.00	88.89			100.00
u_in_stall_endpoint_5	96.30	100.00	88.89			100.00
u_in_stall_endpoint_6	96.30	100.00	88.89			100.00
u_in_stall_endpoint_7	96.30	100.00	88.89			100.00
u_in_stall_endpoint_8	96.30	100.00	88.89			100.00
u_in_stall_endpoint_9	96.30	100.00	88.89			100.00
u_intr_enable_av_empty	100.00	100.00	100.00			100.00
u_intr_enable_av_overflow	100.00	100.00	100.00			100.00
u_intr_enable_disconnected	100.00	100.00	100.00			100.00
u_intr_enable_frame	100.00	100.00	100.00			100.00
u_intr_enable_host_lost	100.00	100.00	100.00			100.00
u_intr_enable_link_in_err	100.00	100.00	100.00			100.00
u_intr_enable_link_out_err	100.00	100.00	100.00			100.00
u_intr_enable_link_reset	100.00	100.00	100.00			100.00
u_intr_enable_link_resume	100.00	100.00	100.00			100.00
u_intr_enable_link_suspend	100.00	100.00	100.00			100.00
u_intr_enable_pkt_received	100.00	100.00	100.00			100.00
u_intr_enable_pkt_sent	100.00	100.00	100.00			100.00
u_intr_enable_powered	100.00	100.00	100.00			100.00
u_intr_enable_rx_bitstuff_err	100.00	100.00	100.00			100.00
u_intr_enable_rx_crc_err	100.00	100.00	100.00			100.00
u_intr_enable_rx_full	100.00	100.00	100.00			100.00
u_intr_enable_rx_pid_err	100.00	100.00	100.00			100.00
u_intr_state_av_empty	100.00	100.00	100.00			100.00
u_intr_state_av_overflow	100.00	100.00	100.00			100.00
u_intr_state_disconnected	100.00	100.00	100.00			100.00
u_intr_state_frame	100.00	100.00	100.00			100.00
u_intr_state_host_lost	100.00	100.00	100.00			100.00
u_intr_state_link_in_err	100.00	100.00	100.00			100.00
u_intr_state_link_out_err	100.00	100.00	100.00			100.00
u_intr_state_link_reset	100.00	100.00	100.00			100.00
u_intr_state_link_resume	100.00	100.00	100.00			100.00
u_intr_state_link_suspend	100.00	100.00	100.00			100.00
u_intr_state_pkt_received	100.00	100.00	100.00			100.00
u_intr_state_pkt_sent	100.00	100.00	100.00			100.00
u_intr_state_powered	100.00	100.00	100.00			100.00
u_intr_state_rx_bitstuff_err	100.00	100.00	100.00			100.00
u_intr_state_rx_crc_err	100.00	100.00	100.00			100.00
u_intr_state_rx_full	100.00	100.00	100.00			100.00
u_intr_state_rx_pid_err	100.00	100.00	100.00			100.00
u_intr_test_av_empty	100.00	100.00
u_intr_test_av_overflow	100.00	100.00
u_intr_test_disconnected	100.00	100.00
u_intr_test_frame	100.00	100.00
u_intr_test_host_lost	100.00	100.00
u_intr_test_link_in_err	100.00	100.00
u_intr_test_link_out_err	100.00	100.00
u_intr_test_link_reset	100.00	100.00
u_intr_test_link_resume	100.00	100.00
u_intr_test_link_suspend	100.00	100.00
u_intr_test_pkt_received	100.00	100.00
u_intr_test_pkt_sent	100.00	100.00
u_intr_test_powered	100.00	100.00
u_intr_test_rx_bitstuff_err	100.00	100.00
u_intr_test_rx_crc_err	100.00	100.00
u_intr_test_rx_full	100.00	100.00
u_intr_test_rx_pid_err	100.00	100.00
u_out_iso_iso_0	100.00	100.00	100.00			100.00
u_out_iso_iso_1	100.00	100.00	100.00			100.00
u_out_iso_iso_10	100.00	100.00	100.00			100.00
u_out_iso_iso_11	100.00	100.00	100.00			100.00
u_out_iso_iso_2	100.00	100.00	100.00			100.00
u_out_iso_iso_3	100.00	100.00	100.00			100.00
u_out_iso_iso_4	100.00	100.00	100.00			100.00
u_out_iso_iso_5	100.00	100.00	100.00			100.00
u_out_iso_iso_6	100.00	100.00	100.00			100.00
u_out_iso_iso_7	100.00	100.00	100.00			100.00
u_out_iso_iso_8	100.00	100.00	100.00			100.00
u_out_iso_iso_9	100.00	100.00	100.00			100.00
u_out_stall_endpoint_0	96.30	100.00	88.89			100.00
u_out_stall_endpoint_1	96.30	100.00	88.89			100.00
u_out_stall_endpoint_10	96.30	100.00	88.89			100.00
u_out_stall_endpoint_11	96.30	100.00	88.89			100.00
u_out_stall_endpoint_2	96.30	100.00	88.89			100.00
u_out_stall_endpoint_3	96.30	100.00	88.89			100.00
u_out_stall_endpoint_4	96.30	100.00	88.89			100.00
u_out_stall_endpoint_5	96.30	100.00	88.89			100.00
u_out_stall_endpoint_6	96.30	100.00	88.89			100.00
u_out_stall_endpoint_7	96.30	100.00	88.89			100.00
u_out_stall_endpoint_8	96.30	100.00	88.89			100.00
u_out_stall_endpoint_9	96.30	100.00	88.89			100.00
u_phy_config_eop_single_bit	100.00	100.00	100.00			100.00
u_phy_config_pinflip	100.00	100.00	100.00			100.00
u_phy_config_tx_osc_test_mode	100.00	100.00	100.00			100.00
u_phy_config_tx_use_d_se0	100.00	100.00	100.00			100.00
u_phy_config_usb_ref_disable	100.00	100.00	100.00			100.00
u_phy_config_use_diff_rcvr	100.00	100.00	100.00			100.00
u_phy_pins_drive_d_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_dn_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_dn_pullup_en_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_dp_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_dp_pullup_en_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_en	100.00	100.00	100.00			100.00
u_phy_pins_drive_oe_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_rx_enable_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_se0_o	100.00	100.00	100.00			100.00
u_phy_pins_sense_pwr_sense	66.67	66.67
u_phy_pins_sense_rx_d_i	66.67	66.67
u_phy_pins_sense_rx_dn_i	66.67	66.67
u_phy_pins_sense_rx_dp_i	66.67	66.67
u_phy_pins_sense_tx_d_o	66.67	66.67
u_phy_pins_sense_tx_dn_o	66.67	66.67
u_phy_pins_sense_tx_dp_o	66.67	66.67
u_phy_pins_sense_tx_oe_o	66.67	66.67
u_phy_pins_sense_tx_se0_o	66.67	66.67
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.39	97.14	96.43			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_rxenable_out_out_0	96.30	100.00	88.89			100.00
u_rxenable_out_out_1	96.30	100.00	88.89			100.00
u_rxenable_out_out_10	96.30	100.00	88.89			100.00
u_rxenable_out_out_11	96.30	100.00	88.89			100.00
u_rxenable_out_out_2	96.30	100.00	88.89			100.00
u_rxenable_out_out_3	96.30	100.00	88.89			100.00
u_rxenable_out_out_4	96.30	100.00	88.89			100.00
u_rxenable_out_out_5	96.30	100.00	88.89			100.00
u_rxenable_out_out_6	96.30	100.00	88.89			100.00
u_rxenable_out_out_7	96.30	100.00	88.89			100.00
u_rxenable_out_out_8	96.30	100.00	88.89			100.00
u_rxenable_out_out_9	96.30	100.00	88.89			100.00
u_rxenable_setup_setup_0	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_1	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_10	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_11	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_2	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_3	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_4	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_5	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_6	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_7	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_8	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_9	100.00	100.00	100.00			100.00
u_rxfifo_buffer	100.00	100.00
u_rxfifo_ep	100.00	100.00
u_rxfifo_setup	100.00	100.00
u_rxfifo_size	100.00	100.00
u_set_nak_out_enable_0	100.00	100.00	100.00			100.00
u_set_nak_out_enable_1	100.00	100.00	100.00			100.00
u_set_nak_out_enable_10	100.00	100.00	100.00			100.00
u_set_nak_out_enable_11	100.00	100.00	100.00			100.00
u_set_nak_out_enable_2	100.00	100.00	100.00			100.00
u_set_nak_out_enable_3	100.00	100.00	100.00			100.00
u_set_nak_out_enable_4	100.00	100.00	100.00			100.00
u_set_nak_out_enable_5	100.00	100.00	100.00			100.00
u_set_nak_out_enable_6	100.00	100.00	100.00			100.00
u_set_nak_out_enable_7	100.00	100.00	100.00			100.00
u_set_nak_out_enable_8	100.00	100.00	100.00			100.00
u_set_nak_out_enable_9	100.00	100.00	100.00			100.00
u_socket	98.24	98.75	98.21			96.00	100.00
u_usbctrl0_qe	100.00	100.00				100.00
u_usbctrl_device_address	96.30	100.00	88.89			100.00
u_usbctrl_enable	100.00	100.00	100.00			100.00
u_usbctrl_resume_link_active	100.00	100.00	100.00			100.00
u_usbstat_av_depth	100.00	100.00
u_usbstat_av_full	100.00	100.00
u_usbstat_frame	100.00	100.00
u_usbstat_host_lost	100.00	100.00
u_usbstat_link_state	100.00	100.00
u_usbstat_rx_depth	100.00	100.00
u_usbstat_rx_empty	100.00	100.00
u_usbstat_sense	100.00	100.00
u_wake_control_cdc	98.13	96.08	96.43			100.00	100.00
u_wake_control_suspend_req	100.00	100.00
u_wake_control_wake_ack	100.00	100.00
u_wake_events_bus_reset	58.89	66.67	50.00			60.00
u_wake_events_cdc	45.74	76.56	25.00			61.40	20.00
u_wake_events_disconnected	58.89	66.67	50.00			60.00
u_wake_events_module_active	58.89	66.67	50.00			60.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : usbdev_reg_top

	Line No.	Total	Covered	Percent
TOTAL		707	705	99.72
ALWAYS	78	4	4	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	135	3	3	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	173	1	1	100.00
ALWAYS	717	1	0	0.00
CONT_ASSIGN	744	1	1	100.00
ALWAYS	758	8	8	100.00
CONT_ASSIGN	1719	1	1	100.00
CONT_ASSIGN	1734	1	1	100.00
CONT_ASSIGN	1750	1	1	100.00
CONT_ASSIGN	1766	1	1	100.00
CONT_ASSIGN	1782	1	1	100.00
CONT_ASSIGN	1798	1	1	100.00
CONT_ASSIGN	1814	1	1	100.00
CONT_ASSIGN	1830	1	1	100.00
CONT_ASSIGN	1846	1	1	100.00
CONT_ASSIGN	1862	1	1	100.00
CONT_ASSIGN	1878	1	1	100.00
CONT_ASSIGN	1894	1	1	100.00
CONT_ASSIGN	1910	1	1	100.00
CONT_ASSIGN	1926	1	1	100.00
CONT_ASSIGN	1942	1	1	100.00
CONT_ASSIGN	1958	1	1	100.00
CONT_ASSIGN	1974	1	1	100.00
CONT_ASSIGN	1990	1	1	100.00
CONT_ASSIGN	1996	1	1	100.00
CONT_ASSIGN	2010	1	1	100.00
CONT_ASSIGN	2078	1	1	100.00
CONT_ASSIGN	2921	1	1	100.00
CONT_ASSIGN	6973	1	1	100.00
CONT_ASSIGN	7001	1	1	100.00
CONT_ASSIGN	7029	1	1	100.00
CONT_ASSIGN	7057	1	1	100.00
CONT_ASSIGN	7085	1	1	100.00
CONT_ASSIGN	7113	1	1	100.00
CONT_ASSIGN	7141	1	1	100.00
CONT_ASSIGN	7169	1	1	100.00
CONT_ASSIGN	7197	1	1	100.00
CONT_ASSIGN	7225	1	1	100.00
CONT_ASSIGN	7253	1	1	100.00
CONT_ASSIGN	7281	1	1	100.00
CONT_ASSIGN	7833	1	1	100.00
CONT_ASSIGN	7848	1	1	100.00
CONT_ASSIGN	7864	1	1	100.00
CONT_ASSIGN	7869	1	0	0.00
ALWAYS	7955	37	37	100.00
CONT_ASSIGN	7994	1	1	100.00
ALWAYS	7998	1	1	100.00
CONT_ASSIGN	8038	1	1	100.00
CONT_ASSIGN	8040	1	1	100.00
CONT_ASSIGN	8042	1	1	100.00
CONT_ASSIGN	8044	1	1	100.00
CONT_ASSIGN	8046	1	1	100.00
CONT_ASSIGN	8048	1	1	100.00
CONT_ASSIGN	8050	1	1	100.00
CONT_ASSIGN	8052	1	1	100.00
CONT_ASSIGN	8054	1	1	100.00
CONT_ASSIGN	8056	1	1	100.00
CONT_ASSIGN	8058	1	1	100.00
CONT_ASSIGN	8060	1	1	100.00
CONT_ASSIGN	8062	1	1	100.00
CONT_ASSIGN	8064	1	1	100.00
CONT_ASSIGN	8066	1	1	100.00
CONT_ASSIGN	8068	1	1	100.00
CONT_ASSIGN	8070	1	1	100.00
CONT_ASSIGN	8072	1	1	100.00
CONT_ASSIGN	8073	1	1	100.00
CONT_ASSIGN	8075	1	1	100.00
CONT_ASSIGN	8077	1	1	100.00
CONT_ASSIGN	8079	1	1	100.00
CONT_ASSIGN	8081	1	1	100.00
CONT_ASSIGN	8083	1	1	100.00
CONT_ASSIGN	8085	1	1	100.00
CONT_ASSIGN	8087	1	1	100.00
CONT_ASSIGN	8089	1	1	100.00
CONT_ASSIGN	8091	1	1	100.00
CONT_ASSIGN	8093	1	1	100.00
CONT_ASSIGN	8095	1	1	100.00
CONT_ASSIGN	8097	1	1	100.00
CONT_ASSIGN	8099	1	1	100.00
CONT_ASSIGN	8101	1	1	100.00
CONT_ASSIGN	8103	1	1	100.00
CONT_ASSIGN	8105	1	1	100.00
CONT_ASSIGN	8107	1	1	100.00
CONT_ASSIGN	8108	1	1	100.00
CONT_ASSIGN	8110	1	1	100.00
CONT_ASSIGN	8112	1	1	100.00
CONT_ASSIGN	8114	1	1	100.00
CONT_ASSIGN	8116	1	1	100.00
CONT_ASSIGN	8118	1	1	100.00
CONT_ASSIGN	8120	1	1	100.00
CONT_ASSIGN	8122	1	1	100.00
CONT_ASSIGN	8124	1	1	100.00
CONT_ASSIGN	8126	1	1	100.00
CONT_ASSIGN	8128	1	1	100.00
CONT_ASSIGN	8130	1	1	100.00
CONT_ASSIGN	8132	1	1	100.00
CONT_ASSIGN	8134	1	1	100.00
CONT_ASSIGN	8136	1	1	100.00
CONT_ASSIGN	8138	1	1	100.00
CONT_ASSIGN	8140	1	1	100.00
CONT_ASSIGN	8142	1	1	100.00
CONT_ASSIGN	8143	1	1	100.00
CONT_ASSIGN	8145	1	1	100.00
CONT_ASSIGN	8146	1	1	100.00
CONT_ASSIGN	8148	1	1	100.00
CONT_ASSIGN	8150	1	1	100.00
CONT_ASSIGN	8152	1	1	100.00
CONT_ASSIGN	8153	1	1	100.00
CONT_ASSIGN	8155	1	1	100.00
CONT_ASSIGN	8157	1	1	100.00
CONT_ASSIGN	8159	1	1	100.00
CONT_ASSIGN	8161	1	1	100.00
CONT_ASSIGN	8163	1	1	100.00
CONT_ASSIGN	8165	1	1	100.00
CONT_ASSIGN	8167	1	1	100.00
CONT_ASSIGN	8169	1	1	100.00
CONT_ASSIGN	8171	1	1	100.00
CONT_ASSIGN	8173	1	1	100.00
CONT_ASSIGN	8175	1	1	100.00
CONT_ASSIGN	8177	1	1	100.00
CONT_ASSIGN	8178	1	1	100.00
CONT_ASSIGN	8180	1	1	100.00
CONT_ASSIGN	8182	1	1	100.00
CONT_ASSIGN	8184	1	1	100.00
CONT_ASSIGN	8186	1	1	100.00
CONT_ASSIGN	8188	1	1	100.00
CONT_ASSIGN	8190	1	1	100.00
CONT_ASSIGN	8192	1	1	100.00
CONT_ASSIGN	8194	1	1	100.00
CONT_ASSIGN	8196	1	1	100.00
CONT_ASSIGN	8198	1	1	100.00
CONT_ASSIGN	8200	1	1	100.00
CONT_ASSIGN	8202	1	1	100.00
CONT_ASSIGN	8203	1	1	100.00
CONT_ASSIGN	8204	1	1	100.00
CONT_ASSIGN	8206	1	1	100.00
CONT_ASSIGN	8207	1	1	100.00
CONT_ASSIGN	8208	1	1	100.00
CONT_ASSIGN	8210	1	1	100.00
CONT_ASSIGN	8212	1	1	100.00
CONT_ASSIGN	8214	1	1	100.00
CONT_ASSIGN	8216	1	1	100.00
CONT_ASSIGN	8218	1	1	100.00
CONT_ASSIGN	8220	1	1	100.00
CONT_ASSIGN	8222	1	1	100.00
CONT_ASSIGN	8224	1	1	100.00
CONT_ASSIGN	8226	1	1	100.00
CONT_ASSIGN	8228	1	1	100.00
CONT_ASSIGN	8230	1	1	100.00
CONT_ASSIGN	8232	1	1	100.00
CONT_ASSIGN	8233	1	1	100.00
CONT_ASSIGN	8235	1	1	100.00
CONT_ASSIGN	8237	1	1	100.00
CONT_ASSIGN	8239	1	1	100.00
CONT_ASSIGN	8241	1	1	100.00
CONT_ASSIGN	8243	1	1	100.00
CONT_ASSIGN	8245	1	1	100.00
CONT_ASSIGN	8247	1	1	100.00
CONT_ASSIGN	8249	1	1	100.00
CONT_ASSIGN	8251	1	1	100.00
CONT_ASSIGN	8253	1	1	100.00
CONT_ASSIGN	8255	1	1	100.00
CONT_ASSIGN	8257	1	1	100.00
CONT_ASSIGN	8258	1	1	100.00
CONT_ASSIGN	8260	1	1	100.00
CONT_ASSIGN	8262	1	1	100.00
CONT_ASSIGN	8264	1	1	100.00
CONT_ASSIGN	8266	1	1	100.00
CONT_ASSIGN	8268	1	1	100.00
CONT_ASSIGN	8270	1	1	100.00
CONT_ASSIGN	8272	1	1	100.00
CONT_ASSIGN	8274	1	1	100.00
CONT_ASSIGN	8276	1	1	100.00
CONT_ASSIGN	8278	1	1	100.00
CONT_ASSIGN	8280	1	1	100.00
CONT_ASSIGN	8282	1	1	100.00
CONT_ASSIGN	8283	1	1	100.00
CONT_ASSIGN	8285	1	1	100.00
CONT_ASSIGN	8287	1	1	100.00
CONT_ASSIGN	8289	1	1	100.00
CONT_ASSIGN	8291	1	1	100.00
CONT_ASSIGN	8293	1	1	100.00
CONT_ASSIGN	8295	1	1	100.00
CONT_ASSIGN	8297	1	1	100.00
CONT_ASSIGN	8299	1	1	100.00
CONT_ASSIGN	8301	1	1	100.00
CONT_ASSIGN	8303	1	1	100.00
CONT_ASSIGN	8305	1	1	100.00
CONT_ASSIGN	8307	1	1	100.00
CONT_ASSIGN	8308	1	1	100.00
CONT_ASSIGN	8310	1	1	100.00
CONT_ASSIGN	8312	1	1	100.00
CONT_ASSIGN	8314	1	1	100.00
CONT_ASSIGN	8316	1	1	100.00
CONT_ASSIGN	8318	1	1	100.00
CONT_ASSIGN	8320	1	1	100.00
CONT_ASSIGN	8322	1	1	100.00
CONT_ASSIGN	8324	1	1	100.00
CONT_ASSIGN	8326	1	1	100.00
CONT_ASSIGN	8328	1	1	100.00
CONT_ASSIGN	8330	1	1	100.00
CONT_ASSIGN	8332	1	1	100.00
CONT_ASSIGN	8333	1	1	100.00
CONT_ASSIGN	8335	1	1	100.00
CONT_ASSIGN	8337	1	1	100.00
CONT_ASSIGN	8339	1	1	100.00
CONT_ASSIGN	8341	1	1	100.00
CONT_ASSIGN	8343	1	1	100.00
CONT_ASSIGN	8345	1	1	100.00
CONT_ASSIGN	8347	1	1	100.00
CONT_ASSIGN	8349	1	1	100.00
CONT_ASSIGN	8351	1	1	100.00
CONT_ASSIGN	8353	1	1	100.00
CONT_ASSIGN	8355	1	1	100.00
CONT_ASSIGN	8357	1	1	100.00
CONT_ASSIGN	8358	1	1	100.00
CONT_ASSIGN	8360	1	1	100.00
CONT_ASSIGN	8362	1	1	100.00
CONT_ASSIGN	8364	1	1	100.00
CONT_ASSIGN	8366	1	1	100.00
CONT_ASSIGN	8367	1	1	100.00
CONT_ASSIGN	8369	1	1	100.00
CONT_ASSIGN	8371	1	1	100.00
CONT_ASSIGN	8373	1	1	100.00
CONT_ASSIGN	8375	1	1	100.00
CONT_ASSIGN	8376	1	1	100.00
CONT_ASSIGN	8378	1	1	100.00
CONT_ASSIGN	8380	1	1	100.00
CONT_ASSIGN	8382	1	1	100.00
CONT_ASSIGN	8384	1	1	100.00
CONT_ASSIGN	8385	1	1	100.00
CONT_ASSIGN	8387	1	1	100.00
CONT_ASSIGN	8389	1	1	100.00
CONT_ASSIGN	8391	1	1	100.00
CONT_ASSIGN	8393	1	1	100.00
CONT_ASSIGN	8394	1	1	100.00
CONT_ASSIGN	8396	1	1	100.00
CONT_ASSIGN	8398	1	1	100.00
CONT_ASSIGN	8400	1	1	100.00
CONT_ASSIGN	8402	1	1	100.00
CONT_ASSIGN	8403	1	1	100.00
CONT_ASSIGN	8405	1	1	100.00
CONT_ASSIGN	8407	1	1	100.00
CONT_ASSIGN	8409	1	1	100.00
CONT_ASSIGN	8411	1	1	100.00
CONT_ASSIGN	8412	1	1	100.00
CONT_ASSIGN	8414	1	1	100.00
CONT_ASSIGN	8416	1	1	100.00
CONT_ASSIGN	8418	1	1	100.00
CONT_ASSIGN	8420	1	1	100.00
CONT_ASSIGN	8421	1	1	100.00
CONT_ASSIGN	8423	1	1	100.00
CONT_ASSIGN	8425	1	1	100.00
CONT_ASSIGN	8427	1	1	100.00
CONT_ASSIGN	8429	1	1	100.00
CONT_ASSIGN	8430	1	1	100.00
CONT_ASSIGN	8432	1	1	100.00
CONT_ASSIGN	8434	1	1	100.00
CONT_ASSIGN	8436	1	1	100.00
CONT_ASSIGN	8438	1	1	100.00
CONT_ASSIGN	8439	1	1	100.00
CONT_ASSIGN	8441	1	1	100.00
CONT_ASSIGN	8443	1	1	100.00
CONT_ASSIGN	8445	1	1	100.00
CONT_ASSIGN	8447	1	1	100.00
CONT_ASSIGN	8448	1	1	100.00
CONT_ASSIGN	8450	1	1	100.00
CONT_ASSIGN	8452	1	1	100.00
CONT_ASSIGN	8454	1	1	100.00
CONT_ASSIGN	8456	1	1	100.00
CONT_ASSIGN	8457	1	1	100.00
CONT_ASSIGN	8459	1	1	100.00
CONT_ASSIGN	8461	1	1	100.00
CONT_ASSIGN	8463	1	1	100.00
CONT_ASSIGN	8465	1	1	100.00
CONT_ASSIGN	8466	1	1	100.00
CONT_ASSIGN	8468	1	1	100.00
CONT_ASSIGN	8470	1	1	100.00
CONT_ASSIGN	8472	1	1	100.00
CONT_ASSIGN	8474	1	1	100.00
CONT_ASSIGN	8476	1	1	100.00
CONT_ASSIGN	8478	1	1	100.00
CONT_ASSIGN	8480	1	1	100.00
CONT_ASSIGN	8482	1	1	100.00
CONT_ASSIGN	8484	1	1	100.00
CONT_ASSIGN	8486	1	1	100.00
CONT_ASSIGN	8488	1	1	100.00
CONT_ASSIGN	8490	1	1	100.00
CONT_ASSIGN	8491	1	1	100.00
CONT_ASSIGN	8493	1	1	100.00
CONT_ASSIGN	8495	1	1	100.00
CONT_ASSIGN	8497	1	1	100.00
CONT_ASSIGN	8499	1	1	100.00
CONT_ASSIGN	8501	1	1	100.00
CONT_ASSIGN	8503	1	1	100.00
CONT_ASSIGN	8505	1	1	100.00
CONT_ASSIGN	8507	1	1	100.00
CONT_ASSIGN	8509	1	1	100.00
CONT_ASSIGN	8511	1	1	100.00
CONT_ASSIGN	8513	1	1	100.00
CONT_ASSIGN	8515	1	1	100.00
CONT_ASSIGN	8516	1	1	100.00
CONT_ASSIGN	8518	1	1	100.00
CONT_ASSIGN	8520	1	1	100.00
CONT_ASSIGN	8522	1	1	100.00
CONT_ASSIGN	8524	1	1	100.00
CONT_ASSIGN	8526	1	1	100.00
CONT_ASSIGN	8528	1	1	100.00
CONT_ASSIGN	8530	1	1	100.00
CONT_ASSIGN	8532	1	1	100.00
CONT_ASSIGN	8534	1	1	100.00
CONT_ASSIGN	8536	1	1	100.00
CONT_ASSIGN	8538	1	1	100.00
CONT_ASSIGN	8540	1	1	100.00
CONT_ASSIGN	8541	1	1	100.00
CONT_ASSIGN	8542	1	1	100.00
CONT_ASSIGN	8544	1	1	100.00
CONT_ASSIGN	8546	1	1	100.00
CONT_ASSIGN	8548	1	1	100.00
CONT_ASSIGN	8550	1	1	100.00
CONT_ASSIGN	8552	1	1	100.00
CONT_ASSIGN	8554	1	1	100.00
CONT_ASSIGN	8556	1	1	100.00
CONT_ASSIGN	8558	1	1	100.00
CONT_ASSIGN	8560	1	1	100.00
CONT_ASSIGN	8561	1	1	100.00
CONT_ASSIGN	8563	1	1	100.00
CONT_ASSIGN	8565	1	1	100.00
CONT_ASSIGN	8567	1	1	100.00
CONT_ASSIGN	8569	1	1	100.00
CONT_ASSIGN	8571	1	1	100.00
CONT_ASSIGN	8573	1	1	100.00
CONT_ASSIGN	8574	1	1	100.00
ALWAYS	8580	37	37	100.00
ALWAYS	8621	276	276	100.00
CONT_ASSIGN	9015	1	1	100.00
ALWAYS	9017	4	4	100.00
CONT_ASSIGN	9038	1	1	100.00
CONT_ASSIGN	9039	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
78	1	1
79	1	1
80	1	1
81	1	1
			MISSING_ELSE
87	1	1
105	1	1
106	1	1
108	1	1
109	1	1
135	1	1
141	1	1
142	1	1
			MISSING_ELSE
172	1	1
173	1	1
717	0	1
744	1	1
758	1	1
759	1	1
760	1	1
761	1	1
762	1	1
763	1	1
764	1	1
765	1	1
1719	1	1
1734	1	1
1750	1	1
1766	1	1
1782	1	1
1798	1	1
1814	1	1
1830	1	1
1846	1	1
1862	1	1
1878	1	1
1894	1	1
1910	1	1
1926	1	1
1942	1	1
1958	1	1
1974	1	1
1990	1	1
1996	1	1
2010	1	1
2078	1	1
2921	1	1
6973	1	1
7001	1	1
7029	1	1
7057	1	1
7085	1	1
7113	1	1
7141	1	1
7169	1	1
7197	1	1
7225	1	1
7253	1	1
7281	1	1
7833	1	1
7848	1	1
7864	1	1
7869	0	1
7955	1	1
7956	1	1
7957	1	1
7958	1	1
7959	1	1
7960	1	1
7961	1	1
7962	1	1
7963	1	1
7964	1	1
7965	1	1
7966	1	1
7967	1	1
7968	1	1
7969	1	1
7970	1	1
7971	1	1
7972	1	1
7973	1	1
7974	1	1
7975	1	1
7976	1	1
7977	1	1
7978	1	1
7979	1	1
7980	1	1
7981	1	1
7982	1	1
7983	1	1
7984	1	1
7985	1	1
7986	1	1
7987	1	1
7988	1	1
7989	1	1
7990	1	1
7991	1	1
7994	1	1
7998	1	1
8038	1	1
8040	1	1
8042	1	1
8044	1	1
8046	1	1
8048	1	1
8050	1	1
8052	1	1
8054	1	1
8056	1	1
8058	1	1
8060	1	1
8062	1	1
8064	1	1
8066	1	1
8068	1	1
8070	1	1
8072	1	1
8073	1	1
8075	1	1
8077	1	1
8079	1	1
8081	1	1
8083	1	1
8085	1	1
8087	1	1
8089	1	1
8091	1	1
8093	1	1
8095	1	1
8097	1	1
8099	1	1
8101	1	1
8103	1	1
8105	1	1
8107	1	1
8108	1	1
8110	1	1
8112	1	1
8114	1	1
8116	1	1
8118	1	1
8120	1	1
8122	1	1
8124	1	1
8126	1	1
8128	1	1
8130	1	1
8132	1	1
8134	1	1
8136	1	1
8138	1	1
8140	1	1
8142	1	1
8143	1	1
8145	1	1
8146	1	1
8148	1	1
8150	1	1
8152	1	1
8153	1	1
8155	1	1
8157	1	1
8159	1	1
8161	1	1
8163	1	1
8165	1	1
8167	1	1
8169	1	1
8171	1	1
8173	1	1
8175	1	1
8177	1	1
8178	1	1
8180	1	1
8182	1	1
8184	1	1
8186	1	1
8188	1	1
8190	1	1
8192	1	1
8194	1	1
8196	1	1
8198	1	1
8200	1	1
8202	1	1
8203	1	1
8204	1	1
8206	1	1
8207	1	1
8208	1	1
8210	1	1
8212	1	1
8214	1	1
8216	1	1
8218	1	1
8220	1	1
8222	1	1
8224	1	1
8226	1	1
8228	1	1
8230	1	1
8232	1	1
8233	1	1
8235	1	1
8237	1	1
8239	1	1
8241	1	1
8243	1	1
8245	1	1
8247	1	1
8249	1	1
8251	1	1
8253	1	1
8255	1	1
8257	1	1
8258	1	1
8260	1	1
8262	1	1
8264	1	1
8266	1	1
8268	1	1
8270	1	1
8272	1	1
8274	1	1
8276	1	1
8278	1	1
8280	1	1
8282	1	1
8283	1	1
8285	1	1
8287	1	1
8289	1	1
8291	1	1
8293	1	1
8295	1	1
8297	1	1
8299	1	1
8301	1	1
8303	1	1
8305	1	1
8307	1	1
8308	1	1
8310	1	1
8312	1	1
8314	1	1
8316	1	1
8318	1	1
8320	1	1
8322	1	1
8324	1	1
8326	1	1
8328	1	1
8330	1	1
8332	1	1
8333	1	1
8335	1	1
8337	1	1
8339	1	1
8341	1	1
8343	1	1
8345	1	1
8347	1	1
8349	1	1
8351	1	1
8353	1	1
8355	1	1
8357	1	1
8358	1	1
8360	1	1
8362	1	1
8364	1	1
8366	1	1
8367	1	1
8369	1	1
8371	1	1
8373	1	1
8375	1	1
8376	1	1
8378	1	1
8380	1	1
8382	1	1
8384	1	1
8385	1	1
8387	1	1
8389	1	1
8391	1	1
8393	1	1
8394	1	1
8396	1	1
8398	1	1
8400	1	1
8402	1	1
8403	1	1
8405	1	1
8407	1	1
8409	1	1
8411	1	1
8412	1	1
8414	1	1
8416	1	1
8418	1	1
8420	1	1
8421	1	1
8423	1	1
8425	1	1
8427	1	1
8429	1	1
8430	1	1
8432	1	1
8434	1	1
8436	1	1
8438	1	1
8439	1	1
8441	1	1
8443	1	1
8445	1	1
8447	1	1
8448	1	1
8450	1	1
8452	1	1
8454	1	1
8456	1	1
8457	1	1
8459	1	1
8461	1	1
8463	1	1
8465	1	1
8466	1	1
8468	1	1
8470	1	1
8472	1	1
8474	1	1
8476	1	1
8478	1	1
8480	1	1
8482	1	1
8484	1	1
8486	1	1
8488	1	1
8490	1	1
8491	1	1
8493	1	1
8495	1	1
8497	1	1
8499	1	1
8501	1	1
8503	1	1
8505	1	1
8507	1	1
8509	1	1
8511	1	1
8513	1	1
8515	1	1
8516	1	1
8518	1	1
8520	1	1
8522	1	1
8524	1	1
8526	1	1
8528	1	1
8530	1	1
8532	1	1
8534	1	1
8536	1	1
8538	1	1
8540	1	1
8541	1	1
8542	1	1
8544	1	1
8546	1	1
8548	1	1
8550	1	1
8552	1	1
8554	1	1
8556	1	1
8558	1	1
8560	1	1
8561	1	1
8563	1	1
8565	1	1
8567	1	1
8569	1	1
8571	1	1
8573	1	1
8574	1	1
8580	1	1
8581	1	1
8582	1	1
8583	1	1
8584	1	1
8585	1	1
8586	1	1
8587	1	1
8588	1	1
8589	1	1
8590	1	1
8591	1	1
8592	1	1
8593	1	1
8594	1	1
8595	1	1
8596	1	1
8597	1	1
8598	1	1
8599	1	1
8600	1	1
8601	1	1
8602	1	1
8603	1	1
8604	1	1
8605	1	1
8606	1	1
8607	1	1
8608	1	1
8609	1	1
8610	1	1
8611	1	1
8612	1	1
8613	1	1
8614	1	1
8615	1	1
8616	1	1
8621	1	1
8622	1	1
8624	1	1
8625	1	1
8626	1	1
8627	1	1
8628	1	1
8629	1	1
8630	1	1
8631	1	1
8632	1	1
8633	1	1
8634	1	1
8635	1	1
8636	1	1
8637	1	1
8638	1	1
8639	1	1
8640	1	1
8644	1	1
8645	1	1
8646	1	1
8647	1	1
8648	1	1
8649	1	1
8650	1	1
8651	1	1
8652	1	1
8653	1	1
8654	1	1
8655	1	1
8656	1	1
8657	1	1
8658	1	1
8659	1	1
8660	1	1
8664	1	1
8665	1	1
8666	1	1
8667	1	1
8668	1	1
8669	1	1
8670	1	1
8671	1	1
8672	1	1
8673	1	1
8674	1	1
8675	1	1
8676	1	1
8677	1	1
8678	1	1
8679	1	1
8680	1	1
8684	1	1
8688	1	1
8689	1	1
8690	1	1
8694	1	1
8695	1	1
8696	1	1
8697	1	1
8698	1	1
8699	1	1
8700	1	1
8701	1	1
8702	1	1
8703	1	1
8704	1	1
8705	1	1
8709	1	1
8710	1	1
8711	1	1
8712	1	1
8713	1	1
8714	1	1
8715	1	1
8716	1	1
8717	1	1
8718	1	1
8719	1	1
8720	1	1
8724	1	1
8725	1	1
8726	1	1
8727	1	1
8728	1	1
8729	1	1
8730	1	1
8731	1	1
8735	1	1
8739	1	1
8740	1	1
8741	1	1
8742	1	1
8746	1	1
8747	1	1
8748	1	1
8749	1	1
8750	1	1
8751	1	1
8752	1	1
8753	1	1
8754	1	1
8755	1	1
8756	1	1
8757	1	1
8761	1	1
8762	1	1
8763	1	1
8764	1	1
8765	1	1
8766	1	1
8767	1	1
8768	1	1
8769	1	1
8770	1	1
8771	1	1
8772	1	1
8776	1	1
8777	1	1
8778	1	1
8779	1	1
8780	1	1
8781	1	1
8782	1	1
8783	1	1
8784	1	1
8785	1	1
8786	1	1
8787	1	1
8791	1	1
8792	1	1
8793	1	1
8794	1	1
8795	1	1
8796	1	1
8797	1	1
8798	1	1
8799	1	1
8800	1	1
8801	1	1
8802	1	1
8806	1	1
8807	1	1
8808	1	1
8809	1	1
8810	1	1
8811	1	1
8812	1	1
8813	1	1
8814	1	1
8815	1	1
8816	1	1
8817	1	1
8821	1	1
8822	1	1
8823	1	1
8824	1	1
8825	1	1
8826	1	1
8827	1	1
8828	1	1
8829	1	1
8830	1	1
8831	1	1
8832	1	1
8836	1	1
8837	1	1
8838	1	1
8839	1	1
8843	1	1
8844	1	1
8845	1	1
8846	1	1
8850	1	1
8851	1	1
8852	1	1
8853	1	1
8857	1	1
8858	1	1
8859	1	1
8860	1	1
8864	1	1
8865	1	1
8866	1	1
8867	1	1
8871	1	1
8872	1	1
8873	1	1
8874	1	1
8878	1	1
8879	1	1
8880	1	1
8881	1	1
8885	1	1
8886	1	1
8887	1	1
8888	1	1
8892	1	1
8893	1	1
8894	1	1
8895	1	1
8899	1	1
8900	1	1
8901	1	1
8902	1	1
8906	1	1
8907	1	1
8908	1	1
8909	1	1
8913	1	1
8914	1	1
8915	1	1
8916	1	1
8920	1	1
8921	1	1
8922	1	1
8923	1	1
8924	1	1
8925	1	1
8926	1	1
8927	1	1
8928	1	1
8929	1	1
8930	1	1
8931	1	1
8935	1	1
8936	1	1
8937	1	1
8938	1	1
8939	1	1
8940	1	1
8941	1	1
8942	1	1
8943	1	1
8944	1	1
8945	1	1
8946	1	1
8950	1	1
8951	1	1
8952	1	1
8953	1	1
8954	1	1
8955	1	1
8956	1	1
8957	1	1
8958	1	1
8959	1	1
8960	1	1
8961	1	1
8965	1	1
8966	1	1
8967	1	1
8968	1	1
8969	1	1
8970	1	1
8971	1	1
8972	1	1
8973	1	1
8977	1	1
8978	1	1
8979	1	1
8980	1	1
8981	1	1
8982	1	1
8983	1	1
8984	1	1
8985	1	1
8989	1	1
8990	1	1
8991	1	1
8992	1	1
8993	1	1
8994	1	1
8998	1	1
9001	1	1
9015	1	1
9017	1	1
9018	1	1
9020	1	1
9023	1	1
9038	1	1
9039	1	1

---

Cond Coverage for Module : usbdev_reg_top

	Total	Covered	Percent
Conditions	385	380	98.70
Logical	385	380	98.70
Non-Logical	0	0
Event	0	0

 LINE       68
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2
1	0	Covered	T6,T32,T33

 LINE       87
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2
0	1	0	Covered	T6,T32,T33
1	0	0	Covered	T1,T2,T6

 LINE       135
 EXPRESSION ((tl_i.a_address[(AW - 1):0] inside {[2048:4095]}) ? 1'b0 : 1'b1)
             ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       173
 EXPRESSION ((devmode_i & addrmiss) | wr_err | intg_err)
             -----------1----------   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T6,T32,T33
0	1	0	Covered	T5,T7,T10
1	0	0	Covered	T5,T7,T10

 LINE       173
 SUB-EXPRESSION (devmode_i & addrmiss)
                 ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T6,T7

 LINE       7956
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_INTR_STATE_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       7957
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_INTR_ENABLE_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       7958
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_INTR_TEST_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       7959
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_ALERT_TEST_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       7960
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_USBCTRL_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       7961
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_EP_OUT_ENABLE_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       7962
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_EP_IN_ENABLE_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       7963
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_USBSTAT_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       7964
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_AVBUFFER_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       7965
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_RXFIFO_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       7966
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_RXENABLE_SETUP_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       7967
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_RXENABLE_OUT_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       7968
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_SET_NAK_OUT_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       7969
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_IN_SENT_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       7970
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_OUT_STALL_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       7971
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_IN_STALL_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       7972
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_0_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       7973
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_1_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       7974
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_2_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       7975
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_3_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       7976
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_4_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       7977
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_5_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       7978
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_6_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       7979
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_7_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       7980
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_8_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       7981
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_9_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       7982
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_10_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       7983
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_11_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       7984
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_OUT_ISO_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       7985
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_IN_ISO_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       7986
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_DATA_TOGGLE_CLEAR_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       7987
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_PHY_PINS_SENSE_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       7988
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_PHY_PINS_DRIVE_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       7989
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_PHY_CONFIG_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       7990
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_WAKE_CONTROL_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       7991
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_WAKE_EVENTS_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       7994
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       7994
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       7998
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[1] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[2] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[11] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[12] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[13] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[14] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[28] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[29] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[30] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[31] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[32] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[33] & ((|(4'b1 & (~reg_be))))) | (addr_hit[34] & ((|(4'b1 & (~reg_be))))) | (addr_hit[35] & ((|(4'b0011 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T7,T10

 LINE       7998
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b0111 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b0111 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b0111 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b0111 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b0111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b0011 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b0011 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b0011 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b0011 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b0011 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b0011 & (~reg_be))))) | 
     30  (addr_hit[29] & ((|(4'b0011 & (~reg_be))))) | 
     31  (addr_hit[30] & ((|(4'b0011 & (~reg_be))))) | 
     32  (addr_hit[31] & ((|(4'b0111 & (~reg_be))))) | 
     33  (addr_hit[32] & ((|(4'b0111 & (~reg_be))))) | 
     34  (addr_hit[33] & ((|(4'b1 & (~reg_be))))) | 
     35  (addr_hit[34] & ((|(4'b1 & (~reg_be))))) | 
     36  (addr_hit[35] & ((|(4'b0011 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T1,T2,T3
36 (addr_hit[35] & ((|(4'...	Covered	T5,T6,T7
35 (addr_hit[34] & ((|(4'...	Covered	T5,T6,T7
34 (addr_hit[33] & ((|(4'...	Covered	T5,T6,T7
33 (addr_hit[32] & ((|(4'...	Covered	T5,T6,T7
32 (addr_hit[31] & ((|(4'...	Covered	T5,T7,T10
31 (addr_hit[30] & ((|(4'...	Covered	T5,T6,T7
30 (addr_hit[29] & ((|(4'...	Covered	T5,T6,T7
29 (addr_hit[28] & ((|(4'...	Covered	T5,T6,T7
28 (addr_hit[27] & ((|(4'...	Covered	T5,T6,T7
27 (addr_hit[26] & ((|(4'...	Covered	T5,T6,T7
26 (addr_hit[25] & ((|(4'...	Covered	T5,T6,T7
25 (addr_hit[24] & ((|(4'...	Covered	T5,T6,T7
24 (addr_hit[23] & ((|(4'...	Covered	T5,T6,T7
23 (addr_hit[22] & ((|(4'...	Covered	T5,T6,T7
22 (addr_hit[21] & ((|(4'...	Covered	T5,T6,T7
21 (addr_hit[20] & ((|(4'...	Covered	T5,T6,T7
20 (addr_hit[19] & ((|(4'...	Covered	T5,T6,T7
19 (addr_hit[18] & ((|(4'...	Covered	T5,T6,T7
18 (addr_hit[17] & ((|(4'...	Covered	T5,T6,T7
17 (addr_hit[16] & ((|(4'...	Covered	T5,T6,T7
16 (addr_hit[15] & ((|(4'...	Covered	T5,T6,T7
15 (addr_hit[14] & ((|(4'...	Covered	T5,T6,T7
14 (addr_hit[13] & ((|(4'...	Covered	T5,T6,T7
13 (addr_hit[12] & ((|(4'...	Covered	T5,T6,T7
12 (addr_hit[11] & ((|(4'...	Covered	T5,T6,T7
11 (addr_hit[10] & ((|(4'...	Covered	T5,T6,T7
10 (addr_hit[9] & ((|(4'b...	Covered	T5,T6,T7
9 (addr_hit[8] & ((|(4'b...	Covered	T5,T7,T10
8 (addr_hit[7] & ((|(4'b...	Covered	T5,T7,T10
7 (addr_hit[6] & ((|(4'b...	Covered	T5,T6,T7
6 (addr_hit[5] & ((|(4'b...	Covered	T5,T6,T7
5 (addr_hit[4] & ((|(4'b...	Covered	T5,T6,T7
4 (addr_hit[3] & ((|(4'b...	Covered	T5,T6,T7
3 (addr_hit[2] & ((|(4'b...	Covered	T3,T5,T7
2 (addr_hit[1] & ((|(4'b...	Covered	T3,T5,T6
1 (addr_hit[0] & ((|(4'b...	Covered	T1,T2,T3

 LINE       7998
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       7998
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T5,T6

 LINE       7998
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T5,T7

 LINE       7998
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T6,T7

 LINE       7998
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T6,T7

 LINE       7998
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T6,T7

 LINE       7998
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T6,T7

 LINE       7998
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T8
1	1	Covered	T5,T7,T10

 LINE       7998
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T7
1	1	Covered	T5,T7,T10

 LINE       7998
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T6,T7

 LINE       7998
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T6,T7

 LINE       7998
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7
1	1	Covered	T5,T6,T7

 LINE       7998
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T6,T7

 LINE       7998
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T6,T7

 LINE       7998
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T6,T7

 LINE       7998
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T6,T7

 LINE       7998
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T6,T7

 LINE       7998
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7
1	1	Covered	T5,T6,T7

 LINE       7998
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7
1	1	Covered	T5,T6,T7

 LINE       7998
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T6,T7

 LINE       7998
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T6,T7

 LINE       7998
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T6,T7

 LINE       7998
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7
1	1	Covered	T5,T6,T7

 LINE       7998
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T6,T7

 LINE       7998
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7
1	1	Covered	T5,T6,T7

 LINE       7998
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T8
1	1	Covered	T5,T6,T7

 LINE       7998
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T6,T7

 LINE       7998
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T8
1	1	Covered	T5,T6,T7

 LINE       7998
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T6,T7

 LINE       7998
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T6,T7

 LINE       7998
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T8
1	1	Covered	T5,T6,T7

 LINE       7998
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7
1	1	Covered	T5,T7,T10

 LINE       7998
 SUB-EXPRESSION (addr_hit[32] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T6,T7

 LINE       7998
 SUB-EXPRESSION (addr_hit[33] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T6,T7

 LINE       7998
 SUB-EXPRESSION (addr_hit[34] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T6,T7

 LINE       7998
 SUB-EXPRESSION (addr_hit[35] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T6,T7

 LINE       8038
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T7,T10,T15
1	1	1	Covered	T1,T2,T3

 LINE       8073
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T5,T7,T10
1	1	1	Covered	T3,T4,T6

 LINE       8108
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T5,T7,T15
1	1	1	Covered	T3,T9,T27

 LINE       8143
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T5,T14,T36
1	1	1	Covered	T4,T6,T8

 LINE       8146
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T5,T7,T14
1	1	1	Covered	T4,T6,T8

 LINE       8153
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T5,T7,T14
1	1	1	Covered	T4,T6,T8

 LINE       8178
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T5,T7,T10
1	1	1	Covered	T4,T6,T8

 LINE       8203
 EXPRESSION (addr_hit[7] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       8204
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T7
1	1	0	Covered	T5,T7,T10
1	1	1	Covered	T9,T23,T26

 LINE       8207
 EXPRESSION (addr_hit[9] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T4,T6,T8

 LINE       8208
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T5,T7,T10
1	1	1	Covered	T4,T6,T8

 LINE       8233
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T7,T10,T15
1	1	1	Covered	T4,T6,T8

 LINE       8258
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T7,T10,T14
1	1	1	Covered	T4,T6,T8

 LINE       8283
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T5,T7,T10
1	1	1	Covered	T4,T6,T8

 LINE       8308
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T7,T35,T57
1	1	1	Covered	T4,T6,T8

 LINE       8333
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T5,T7,T14
1	1	1	Covered	T4,T6,T8

 LINE       8358
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T7,T34,T35
1	1	1	Covered	T4,T6,T8

 LINE       8367
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T7,T10,T15
1	1	1	Covered	T4,T6,T8

 LINE       8376
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T5,T7,T10
1	1	1	Covered	T4,T6,T8

 LINE       8385
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T5,T7,T14
1	1	1	Covered	T4,T6,T8

 LINE       8394
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T5,T7,T15
1	1	1	Covered	T4,T6,T8

 LINE       8403
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T5,T15,T57
1	1	1	Covered	T4,T6,T8

 LINE       8412
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T5,T7,T10
1	1	1	Covered	T4,T6,T8

 LINE       8421
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T5,T10,T14
1	1	1	Covered	T4,T6,T8

 LINE       8430
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T5,T7,T14
1	1	1	Covered	T4,T6,T8

 LINE       8439
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T5,T7,T10
1	1	1	Covered	T4,T6,T8

 LINE       8448
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T7,T15,T35
1	1	1	Covered	T4,T6,T8

 LINE       8457
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T5,T7,T14
1	1	1	Covered	T4,T6,T8

 LINE       8466
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T5,T7,T14
1	1	1	Covered	T4,T6,T8

 LINE       8491
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T5,T7,T14
1	1	1	Covered	T4,T6,T8

 LINE       8516
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T7,T14,T15
1	1	1	Covered	T4,T6,T8

 LINE       8541
 EXPRESSION (addr_hit[31] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       8542
 EXPRESSION (addr_hit[32] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T5,T15,T34
1	1	1	Covered	T4,T6,T8

 LINE       8561
 EXPRESSION (addr_hit[33] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T5,T7,T10
1	1	1	Covered	T4,T6,T8

 LINE       8574
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T7,T10,T14
1	1	1	Covered	T4,T6,T8

 LINE       9015
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T4,T6,T8

---

Branch Coverage for Module : usbdev_reg_top

	Line No.	Total	Covered	Percent
Branches		49	49	100.00
TERNARY	7994	2	2	100.00
IF	78	3	3	100.00
TERNARY	135	2	2	100.00
IF	141	2	2	100.00
CASE	8622	37	37	100.00
CASE	9018	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	7994	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	78	if ((!rst_ni))
-2-:	80	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	135	((tl_i.a_address[(AW - 1):0] inside {[2048:4095]})) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	141	if (intg_err)

Branches:

-1-	Status	Tests
1	Covered	T6,T32,T33
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	8622	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T3
addr_hit[29]	Covered	T1,T2,T3
addr_hit[30]	Covered	T1,T2,T3
addr_hit[31]	Covered	T1,T2,T3
addr_hit[32]	Covered	T1,T2,T3
addr_hit[33]	Covered	T1,T2,T3
addr_hit[34]	Covered	T1,T2,T3
addr_hit[35]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	9018	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[34]	Covered	T1,T2,T3
addr_hit[35]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : usbdev_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	593410	46060	0	0
reAfterRv	593410	46059	0	0
rePulse	593410	32087	0	0
wePulse	593410	13972	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	593410	46060	0	0
T1	7240	3	0	0
T2	5079	3	0	0
T3	1405	22	0	0
T4	2786	661	0	0
T5	15912	54	0	0
T6	23737	1519	0	0
T7	11123	77	0	0
T8	1304	151	0	0
T9	1848	68	0	0
T10	4367	39	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	593410	46059	0	0
T1	7240	3	0	0
T2	5079	3	0	0
T3	1405	22	0	0
T4	2786	661	0	0
T5	15912	54	0	0
T6	23737	1519	0	0
T7	11123	77	0	0
T8	1304	151	0	0
T9	1848	68	0	0
T10	4367	39	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	593410	32087	0	0
T1	7240	2	0	0
T2	5079	2	0	0
T3	1405	11	0	0
T4	2786	344	0	0
T5	15912	8	0	0
T6	23737	1200	0	0
T7	11123	7	0	0
T8	1304	119	0	0
T9	1848	33	0	0
T10	4367	11	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	593410	13972	0	0
T1	7240	1	0	0
T2	5079	1	0	0
T3	1405	11	0	0
T4	2786	317	0	0
T5	15912	46	0	0
T6	23737	319	0	0
T7	11123	70	0	0
T8	1304	32	0	0
T9	1848	35	0	0
T10	4367	28	0	0