Line Coverage for Module :
tlul_socket_1n
| Line No. | Total | Covered | Percent |
TOTAL | | 56 | 55 | 98.21 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
ALWAYS | 116 | 9 | 9 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 143 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
CONT_ASSIGN | 165 | 1 | 1 | 100.00 |
CONT_ASSIGN | 165 | 1 | 1 | 100.00 |
CONT_ASSIGN | 169 | 1 | 1 | 100.00 |
CONT_ASSIGN | 169 | 1 | 1 | 100.00 |
ALWAYS | 178 | 6 | 6 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
ALWAYS | 190 | 4 | 4 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
CONT_ASSIGN | 196 | 1 | 1 | 100.00 |
CONT_ASSIGN | 197 | 1 | 1 | 100.00 |
CONT_ASSIGN | 198 | 1 | 1 | 100.00 |
CONT_ASSIGN | 199 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
CONT_ASSIGN | 201 | 1 | 1 | 100.00 |
CONT_ASSIGN | 202 | 1 | 1 | 100.00 |
CONT_ASSIGN | 203 | 1 | 1 | 100.00 |
CONT_ASSIGN | 250 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
112 |
1 |
1 |
113 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
119 |
1 |
1 |
120 |
1 |
1 |
122 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
124 |
1 |
1 |
125 |
1 |
1 |
126 |
1 |
1 |
|
|
|
MISSING_ELSE |
130 |
1 |
1 |
143 |
1 |
1 |
153 |
2 |
2 |
155 |
2 |
2 |
156 |
2 |
2 |
157 |
2 |
2 |
158 |
2 |
2 |
159 |
2 |
2 |
160 |
2 |
2 |
161 |
2 |
2 |
162 |
2 |
2 |
165 |
2 |
2 |
169 |
2 |
2 |
178 |
1 |
1 |
179 |
1 |
1 |
181 |
2 |
2 |
|
|
|
MISSING_ELSE |
183 |
2 |
2 |
|
|
|
MISSING_ELSE |
187 |
1 |
1 |
190 |
1 |
1 |
191 |
1 |
1 |
192 |
2 |
2 |
|
|
|
MISSING_ELSE |
195 |
1 |
1 |
196 |
1 |
1 |
197 |
1 |
1 |
198 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
201 |
1 |
1 |
202 |
1 |
1 |
203 |
1 |
1 |
250 |
0 |
1 |
Cond Coverage for Module :
tlul_socket_1n
| Total | Covered | Percent |
Conditions | 44 | 43 | 97.73 |
Logical | 44 | 43 | 97.73 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 112
EXPRESSION (tl_t_o.a_valid & tl_t_i.a_ready)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 113
EXPRESSION (tl_t_i.d_valid & tl_t_o.d_ready)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T5,T6 |
1 | 1 | Covered | T1,T2,T3 |
LINE 130
EXPRESSION ((num_req_outstanding != '0) & (dev_select_t != dev_select_outstanding))
-------------1------------- --------------------2-------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T5,T7,T8 |
LINE 130
SUB-EXPRESSION (num_req_outstanding != '0)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 130
SUB-EXPRESSION (dev_select_t != dev_select_outstanding)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 153
EXPRESSION ((dev_select_t == 1'(0)) & ((~hold_all_requests)))
-----------1----------- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T5,T7,T8 |
1 | 1 | Covered | T5,T7,T8 |
LINE 153
SUB-EXPRESSION (dev_select_t == 1'(0))
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T7,T8 |
LINE 153
EXPRESSION ((dev_select_t == 1'(1)) & ((~hold_all_requests)))
-----------1----------- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T5,T7,T10 |
1 | 1 | Covered | T1,T2,T3 |
LINE 153
SUB-EXPRESSION (dev_select_t == 1'(1))
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION (tl_t_o.a_valid & gen_u_o[0].dev_select)
-------1------ ----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T5,T7,T10 |
LINE 155
EXPRESSION (tl_t_o.a_valid & gen_u_o[1].dev_select)
-------1------ ----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T5,T7,T10 |
1 | 1 | Covered | T1,T2,T3 |
LINE 162
EXPRESSION (gen_u_o[0].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T7,T8 |
LINE 162
EXPRESSION (gen_u_o[1].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
----------1----------
-1- | Status | Tests |
0 | Covered | T5,T7,T8 |
1 | Covered | T1,T2,T3 |
LINE 165
EXPRESSION (gen_u_o[0].dev_select ? tl_t_o.a_user : blanked_auser)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T7,T8 |
LINE 165
EXPRESSION (gen_u_o[1].dev_select ? tl_t_o.a_user : blanked_auser)
----------1----------
-1- | Status | Tests |
0 | Covered | T5,T7,T8 |
1 | Covered | T1,T2,T3 |
LINE 181
EXPRESSION (dev_select_t == 1'(idx))
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 187
EXPRESSION (tl_t_o.a_valid & hfifo_reqready)
-------1------ -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 192
EXPRESSION (dev_select_outstanding == 1'(idx))
-----------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
tlul_socket_1n
| Line No. | Total | Covered | Percent |
Branches |
|
19 |
18 |
94.74 |
TERNARY |
162 |
2 |
2 |
100.00 |
TERNARY |
165 |
2 |
2 |
100.00 |
TERNARY |
162 |
2 |
2 |
100.00 |
TERNARY |
165 |
2 |
2 |
100.00 |
IF |
116 |
5 |
4 |
80.00 |
IF |
181 |
2 |
2 |
100.00 |
IF |
183 |
2 |
2 |
100.00 |
IF |
192 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 162 (gen_u_o[0].dev_select) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T8 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 165 (gen_u_o[0].dev_select) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T8 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 162 (gen_u_o[1].dev_select) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T5,T7,T8 |
LineNo. Expression
-1-: 165 (gen_u_o[1].dev_select) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T5,T7,T8 |
LineNo. Expression
-1-: 116 if ((!rst_ni))
-2-: 119 if (accept_t_req)
-3-: 120 if ((!accept_t_rsp))
-4-: 125 if (accept_t_rsp)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
0 |
- |
Not Covered |
|
0 |
0 |
- |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 181 if ((dev_select_t == 1'(idx)))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 183 if (hold_all_requests)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 192 if ((dev_select_outstanding == 1'(idx)))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
tlul_socket_1n
Assertion Details
NotOverflowed_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
76995 |
76995 |
0 |
0 |
T1 |
3 |
3 |
0 |
0 |
T2 |
3 |
3 |
0 |
0 |
T3 |
22 |
22 |
0 |
0 |
T4 |
661 |
661 |
0 |
0 |
T5 |
2062 |
2062 |
0 |
0 |
T6 |
1522 |
1522 |
0 |
0 |
T7 |
1346 |
1346 |
0 |
0 |
T8 |
151 |
151 |
0 |
0 |
T9 |
68 |
68 |
0 |
0 |
T10 |
1675 |
1675 |
0 |
0 |
maxN
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
125 |
125 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |