Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46283	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	51750	1		T1	1		T2	2		T3	2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	58838	1		T1	2		T2	2		T3	2
values[0x0]	19087	1		T3	1		T4	1		T5	101
values[0x1]	20108	1		T1	1		T2	1		T5	73

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32124	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	65909	1		T1	2		T2	2		T3	2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	420	1		T5	3		T8	1		T9	7
valid_sources[0x01]	591	1		T7	7		T8	2		T9	7
valid_sources[0x02]	460	1		T6	1		T7	1		T9	6
valid_sources[0x03]	320	1		T7	1		T8	1		T9	3
valid_sources[0x04]	287	1		T5	4		T9	1		T10	6
valid_sources[0x05]	397	1		T5	7		T7	1		T9	1
valid_sources[0x06]	683	1		T5	6		T8	3		T10	9
valid_sources[0x07]	335	1		T5	3		T8	1		T9	1
valid_sources[0x08]	305	1		T5	12		T8	5		T10	1
valid_sources[0x09]	407	1		T5	1		T8	1		T11	5
valid_sources[0x0a]	249	1		T5	1		T8	2		T9	4
valid_sources[0x0b]	211	1		T5	1		T7	1		T24	1
valid_sources[0x0c]	316	1		T5	3		T7	2		T8	1
valid_sources[0x0d]	320	1		T5	2		T7	1		T8	3
valid_sources[0x0e]	461	1		T5	4		T7	1		T8	2
valid_sources[0x0f]	276	1		T10	1		T24	6		T11	1
valid_sources[0x10]	481	1		T5	1		T7	2		T8	1
valid_sources[0x11]	436	1		T5	2		T7	4		T11	2
valid_sources[0x12]	606	1		T5	2		T9	1		T10	14
valid_sources[0x13]	267	1		T10	2		T11	3		T12	2
valid_sources[0x14]	434	1		T5	4		T7	3		T8	1
valid_sources[0x15]	317	1		T7	2		T8	2		T10	7
valid_sources[0x16]	273	1		T5	2		T8	2		T9	1
valid_sources[0x17]	307	1		T5	1		T8	1		T9	1
valid_sources[0x18]	314	1		T5	1		T10	11		T11	2
valid_sources[0x19]	264	1		T8	1		T9	1		T24	7
valid_sources[0x1a]	316	1		T7	1		T9	1		T11	4
valid_sources[0x1b]	302	1		T5	1		T8	4		T9	1
valid_sources[0x1c]	337	1		T5	6		T7	4		T8	3
valid_sources[0x1d]	270	1		T9	4		T23	14		T36	3
valid_sources[0x1e]	298	1		T9	3		T11	2		T34	2
valid_sources[0x1f]	364	1		T8	5		T9	5		T10	4
valid_sources[0x20]	479	1		T5	1		T8	1		T11	1
valid_sources[0x21]	272	1		T8	3		T9	14		T10	12
valid_sources[0x22]	618	1		T7	3		T8	1		T9	2
valid_sources[0x23]	378	1		T5	2		T7	7		T8	1
valid_sources[0x24]	309	1		T7	2		T8	2		T9	9
valid_sources[0x25]	269	1		T7	2		T8	4		T10	8
valid_sources[0x26]	284	1		T2	3		T8	1		T9	5
valid_sources[0x27]	242	1		T5	1		T8	1		T9	5
valid_sources[0x28]	464	1		T5	4		T8	2		T9	1
valid_sources[0x29]	315	1		T7	1		T8	1		T9	1
valid_sources[0x2a]	540	1		T8	1		T9	1		T10	2
valid_sources[0x2b]	412	1		T8	1		T9	4		T11	3
valid_sources[0x2c]	404	1		T5	2		T7	1		T9	1
valid_sources[0x2d]	324	1		T5	2		T7	3		T8	1
valid_sources[0x2e]	256	1		T5	1		T11	3		T23	13
valid_sources[0x2f]	249	1		T7	2		T8	2		T9	2
valid_sources[0x30]	399	1		T8	2		T9	1		T11	3
valid_sources[0x31]	368	1		T5	2		T7	1		T9	6
valid_sources[0x32]	307	1		T8	8		T9	1		T10	2
valid_sources[0x33]	458	1		T5	3		T8	3		T9	9
valid_sources[0x34]	257	1		T5	3		T7	4		T8	4
valid_sources[0x35]	359	1		T10	7		T11	4		T23	84
valid_sources[0x36]	403	1		T5	1		T8	2		T9	1
valid_sources[0x37]	314	1		T5	1		T8	2		T11	2
valid_sources[0x38]	299	1		T7	7		T8	1		T9	4
valid_sources[0x39]	280	1		T5	3		T9	1		T10	4
valid_sources[0x3a]	419	1		T8	2		T9	1		T24	1
valid_sources[0x3b]	370	1		T5	7		T10	9		T24	3
valid_sources[0x3c]	417	1		T5	3		T7	1		T8	3
valid_sources[0x3d]	291	1		T5	1		T7	1		T8	1
valid_sources[0x3e]	495	1		T11	2		T23	67		T35	1
valid_sources[0x3f]	262	1		T7	2		T8	1		T9	4
valid_sources[0x40]	291	1		T5	1		T8	4		T9	3
valid_sources[0x41]	354	1		T7	2		T9	2		T12	1
valid_sources[0x42]	444	1		T8	6		T24	2		T11	1
valid_sources[0x43]	501	1		T5	4		T7	2		T24	5
valid_sources[0x44]	329	1		T5	3		T8	1		T9	7
valid_sources[0x45]	243	1		T5	2		T9	1		T24	3
valid_sources[0x46]	330	1		T10	3		T11	1		T32	1
valid_sources[0x47]	262	1		T5	1		T7	1		T8	1
valid_sources[0x48]	303	1		T5	7		T8	2		T9	2
valid_sources[0x49]	277	1		T7	5		T9	4		T10	7
valid_sources[0x4a]	252	1		T5	4		T8	7		T9	2
valid_sources[0x4b]	379	1		T7	3		T8	2		T9	1
valid_sources[0x4c]	242	1		T6	22		T8	1		T9	3
valid_sources[0x4d]	466	1		T5	2		T7	1		T9	4
valid_sources[0x4e]	332	1		T7	1		T8	2		T9	1
valid_sources[0x4f]	343	1		T5	3		T7	2		T9	3
valid_sources[0x50]	291	1		T5	7		T7	3		T8	2
valid_sources[0x51]	465	1		T8	8		T9	1		T24	2
valid_sources[0x52]	566	1		T7	1		T9	3		T10	19
valid_sources[0x53]	297	1		T5	3		T8	1		T9	1
valid_sources[0x54]	310	1		T7	1		T8	1		T9	2
valid_sources[0x55]	501	1		T7	1		T8	2		T9	1
valid_sources[0x56]	470	1		T8	4		T9	4		T10	2
valid_sources[0x57]	374	1		T9	1		T11	1		T23	24
valid_sources[0x58]	312	1		T9	4		T10	4		T11	3
valid_sources[0x59]	482	1		T5	1		T8	2		T11	1
valid_sources[0x5a]	292	1		T8	2		T11	1		T23	31
valid_sources[0x5b]	330	1		T5	4		T7	3		T8	1
valid_sources[0x5c]	336	1		T5	2		T8	1		T10	1
valid_sources[0x5d]	296	1		T7	3		T8	7		T10	4
valid_sources[0x5e]	318	1		T7	7		T8	2		T9	8
valid_sources[0x5f]	570	1		T8	1		T9	2		T10	6
valid_sources[0x60]	435	1		T6	5		T8	4		T10	4
valid_sources[0x61]	376	1		T5	2		T8	1		T9	2
valid_sources[0x62]	320	1		T5	3		T7	3		T8	1
valid_sources[0x63]	510	1		T10	2		T24	3		T11	3
valid_sources[0x64]	345	1		T8	3		T9	5		T10	3
valid_sources[0x65]	500	1		T8	1		T9	4		T10	3
valid_sources[0x66]	550	1		T5	2		T7	1		T10	5
valid_sources[0x67]	275	1		T5	2		T8	2		T9	5
valid_sources[0x68]	219	1		T5	2		T7	3		T9	2
valid_sources[0x69]	284	1		T8	1		T9	3		T10	19
valid_sources[0x6a]	358	1		T5	2		T9	5		T10	4
valid_sources[0x6b]	253	1		T5	3		T8	1		T9	3
valid_sources[0x6c]	296	1		T10	15		T11	1		T23	13
valid_sources[0x6d]	674	1		T5	2		T9	1		T10	1
valid_sources[0x6e]	420	1		T8	1		T9	1		T10	15
valid_sources[0x6f]	264	1		T5	4		T8	4		T9	5
valid_sources[0x70]	488	1		T8	1		T9	2		T10	5
valid_sources[0x71]	1801	1		T5	9		T7	4		T8	1
valid_sources[0x72]	557	1		T5	1		T7	2		T8	4
valid_sources[0x73]	461	1		T5	6		T8	3		T10	5
valid_sources[0x74]	395	1		T5	2		T8	1		T10	8
valid_sources[0x75]	407	1		T7	3		T8	3		T9	3
valid_sources[0x76]	467	1		T8	2		T9	1		T11	6
valid_sources[0x77]	429	1		T5	2		T8	1		T9	2
valid_sources[0x78]	258	1		T7	2		T9	1		T11	7
valid_sources[0x79]	311	1		T8	3		T9	1		T11	1
valid_sources[0x7a]	647	1		T5	6		T7	2		T8	1
valid_sources[0x7b]	291	1		T5	4		T7	1		T9	2
valid_sources[0x7c]	302	1		T5	4		T7	4		T9	6
valid_sources[0x7d]	223	1		T9	1		T10	4		T24	2
valid_sources[0x7e]	573	1		T8	3		T9	3		T10	6
valid_sources[0x7f]	377	1		T5	2		T8	5		T10	9
valid_sources[0x80]	324	1		T5	1		T7	1		T9	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

19686

1

T2

1

T3

1

T4

1

values[0x0]

all_enables

biggest_size

16706

1

T3

1

T4

1

T5

101

values[0x1]

all_enables

biggest_size

15358

1

T1

1

T2

1

T5

73