Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.67	91.67	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	91.67	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.67	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	2	14	87.50

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	2	14	87.50	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	58837	1		T1	2		T2	1		T3	1
full_word	52628	1		T1	1		T2	2		T3	2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	111255	1		T1	3		T2	3		T3	3
auto[TlIntgErrCmd]	79	1		T23	8		T20	3		T21	8
auto[TlIntgErrData]	68	1		T23	8		T20	4		T21	7
auto[TlIntgErrBoth]	63	1		T23	4		T20	3		T21	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	60477	1		T1	2		T2	2		T3	2
auto[1]	50988	1		T1	1		T2	1		T3	1

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	2	14	87.50	2

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	40511	1		T1	2		T2	1		T3	1
auto[TlIntgErrNone]	partial	auto[1]	18132	1		T6	4		T7	410		T9	673
auto[TlIntgErrNone]	full_word	auto[0]	19869	1		T2	1		T3	1		T4	1
auto[TlIntgErrNone]	full_word	auto[1]	32743	1		T1	1		T2	1		T3	1
auto[TlIntgErrCmd]	partial	auto[0]	32	1		T23	5		T21	6		T64	2
auto[TlIntgErrCmd]	partial	auto[1]	42	1		T23	3		T20	3		T21	2
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T64	1		T65	1		T66	1
auto[TlIntgErrData]	partial	auto[0]	31	1		T23	4		T20	2		T21	3
auto[TlIntgErrData]	partial	auto[1]	29	1		T23	3		T21	3		T40	1
auto[TlIntgErrData]	full_word	auto[0]	3	1		T20	1		T67	1		T68	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T23	1		T20	1		T21	1
auto[TlIntgErrBoth]	partial	auto[0]	31	1		T23	3		T20	2		T21	2
auto[TlIntgErrBoth]	partial	auto[1]	29	1		T23	1		T20	1		T21	3
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T64	1		T69	1		T68	1