Module Definition
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Module : prim_reg_cdc
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.86 100.00 71.43 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_wake_events_cdc 57.45 82.35 30.77 66.67 50.00
tb.dut.u_reg.u_wake_control_cdc 97.73 100.00 90.91 100.00 100.00



Module Instance : tb.dut.u_reg.u_wake_events_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
57.45 82.35 30.77 66.67 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
45.74 76.56 25.00 61.40 20.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.60 99.72 98.70 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 37.10 72.45 22.45 53.49 0.00
u_src_to_dst_req 58.33 100.00 33.33 100.00 0.00



Module Instance : tb.dut.u_reg.u_wake_control_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.13 96.08 96.43 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.60 99.72 98.70 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 96.88 87.50 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Module : prim_reg_cdc
TotalCoveredPercent
Conditions141071.43
Logical141071.43
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT5,T8,T10

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T8,T10
11CoveredT5,T8,T10

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT5,T8,T10

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT5,T8,T10
11CoveredT5,T8,T10

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

Branch Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T5,T8,T10
0 0 1 Covered T5,T8,T10
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T5,T8,T10
0 0 1 Covered T5,T8,T10
0 0 0 Covered T1,T2,T3


Assert Coverage for Module : prim_reg_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1497878 9856 0 0
DstReqKnown_A 429886 366876 0 0
SrcAckBusyChk_A 1497878 714 0 0
SrcBusyKnown_A 1497878 1433514 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1497878 9856 0 0
T5 3463 57 0 0
T8 3511 158 0 0
T10 3708 14 0 0
T14 3068 0 0 0
T19 7133 183 0 0
T20 0 134 0 0
T23 12609 162 0 0
T24 3151 34 0 0
T34 1718 7 0 0
T35 3284 32 0 0
T36 4923 48 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 429886 366876 0 0
T1 4024 2298 0 0
T2 5960 2884 0 0
T3 4580 2772 0 0
T4 2872 1170 0 0
T5 2304 2194 0 0
T6 776 662 0 0
T7 4292 4180 0 0
T8 1608 1508 0 0
T9 484 318 0 0
T10 1698 1500 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1497878 714 0 0
T5 3463 6 0 0
T8 3511 13 0 0
T10 3708 1 0 0
T14 3068 0 0 0
T19 7133 22 0 0
T20 0 10 0 0
T23 12609 18 0 0
T24 3151 2 0 0
T34 1718 1 0 0
T35 3284 4 0 0
T36 4923 3 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1497878 1433514 0 0
T1 8050 6452 0 0
T2 14308 11178 0 0
T3 9560 7954 0 0
T4 27596 25946 0 0
T5 6926 6820 0 0
T6 2338 2220 0 0
T7 11454 11260 0 0
T8 7022 6888 0 0
T9 11662 11492 0 0
T10 7416 7228 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
Line No.TotalCoveredPercent
TOTAL171482.35
CONT_ASSIGN5400
ALWAYS605480.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS1047571.43
CONT_ASSIGN13900
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 unreachable
60 1 1
61 1 1
62 1 1
63 unreachable
64 1 1
65 0 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 unreachable
113 unreachable
114 1 1
123 0 1
124 0 1
MISSING_ELSE
139 unreachable
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
TotalCoveredPercent
Conditions13430.77
Logical13430.77
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

Branch Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
Line No.TotalCoveredPercent
Branches 6 4 66.67
IF 60 3 2 66.67
IF 104 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Unreachable
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Unreachable
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 2 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 2 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 748939 0 0 0
DstReqKnown_A 214943 183438 0 0
SrcAckBusyChk_A 748939 0 0 0
SrcBusyKnown_A 748939 716757 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 748939 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 214943 183438 0 0
T1 2012 1149 0 0
T2 2980 1442 0 0
T3 2290 1386 0 0
T4 1436 585 0 0
T5 1152 1097 0 0
T6 388 331 0 0
T7 2146 2090 0 0
T8 804 754 0 0
T9 242 159 0 0
T10 849 750 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 748939 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 748939 716757 0 0
T1 4025 3226 0 0
T2 7154 5589 0 0
T3 4780 3977 0 0
T4 13798 12973 0 0
T5 3463 3410 0 0
T6 1169 1110 0 0
T7 5727 5630 0 0
T8 3511 3444 0 0
T9 5831 5746 0 0
T10 3708 3614 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT5,T8,T10

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T8,T10
11CoveredT5,T8,T10

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT5,T8,T10

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT5,T8,T10
11CoveredT5,T8,T10

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T5,T8,T10
0 0 1 Covered T5,T8,T10
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T5,T8,T10
0 0 1 Covered T5,T8,T10
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 748939 9856 0 0
DstReqKnown_A 214943 183438 0 0
SrcAckBusyChk_A 748939 714 0 0
SrcBusyKnown_A 748939 716757 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 748939 9856 0 0
T5 3463 57 0 0
T8 3511 158 0 0
T10 3708 14 0 0
T14 3068 0 0 0
T19 7133 183 0 0
T20 0 134 0 0
T23 12609 162 0 0
T24 3151 34 0 0
T34 1718 7 0 0
T35 3284 32 0 0
T36 4923 48 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 214943 183438 0 0
T1 2012 1149 0 0
T2 2980 1442 0 0
T3 2290 1386 0 0
T4 1436 585 0 0
T5 1152 1097 0 0
T6 388 331 0 0
T7 2146 2090 0 0
T8 804 754 0 0
T9 242 159 0 0
T10 849 750 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 748939 714 0 0
T5 3463 6 0 0
T8 3511 13 0 0
T10 3708 1 0 0
T14 3068 0 0 0
T19 7133 22 0 0
T20 0 10 0 0
T23 12609 18 0 0
T24 3151 2 0 0
T34 1718 1 0 0
T35 3284 4 0 0
T36 4923 3 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 748939 716757 0 0
T1 4025 3226 0 0
T2 7154 5589 0 0
T3 4780 3977 0 0
T4 13798 12973 0 0
T5 3463 3410 0 0
T6 1169 1110 0 0
T7 5727 5630 0 0
T8 3511 3444 0 0
T9 5831 5746 0 0
T10 3708 3614 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%