Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	37108	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	55003	1		T1	2		T2	1		T3	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	54350	1		T1	2		T2	2		T3	2
values[0x0]	18645	1		T1	1		T2	1		T4	7
values[0x1]	19116	1		T3	1		T4	4		T5	28

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25947	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	66164	1		T1	3		T2	2		T3	1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	259	1		T6	1		T22	5		T56	3
valid_sources[0x01]	318	1		T6	2		T23	16		T22	11
valid_sources[0x02]	444	1		T5	12		T6	2		T23	4
valid_sources[0x03]	382	1		T6	3		T23	2		T22	8
valid_sources[0x04]	261	1		T5	7		T23	3		T22	11
valid_sources[0x05]	363	1		T6	9		T23	1		T22	3
valid_sources[0x06]	362	1		T6	3		T23	6		T22	8
valid_sources[0x07]	324	1		T6	3		T23	2		T22	7
valid_sources[0x08]	273	1		T3	1		T6	2		T23	5
valid_sources[0x09]	281	1		T23	9		T22	4		T24	1
valid_sources[0x0a]	326	1		T6	1		T23	1		T22	6
valid_sources[0x0b]	295	1		T6	1		T22	1		T56	3
valid_sources[0x0c]	272	1		T6	2		T23	1		T22	3
valid_sources[0x0d]	287	1		T6	1		T23	3		T22	3
valid_sources[0x0e]	279	1		T6	3		T23	4		T22	6
valid_sources[0x0f]	350	1		T6	1		T23	2		T22	2
valid_sources[0x10]	411	1		T6	2		T23	1		T22	5
valid_sources[0x11]	322	1		T5	14		T23	1		T22	1
valid_sources[0x12]	389	1		T6	3		T23	5		T22	3
valid_sources[0x13]	283	1		T6	3		T23	6		T22	3
valid_sources[0x14]	345	1		T6	3		T23	1		T22	16
valid_sources[0x15]	329	1		T6	5		T22	5		T56	2
valid_sources[0x16]	3423	1		T6	3		T11	3073		T23	8
valid_sources[0x17]	431	1		T6	1		T22	5		T56	1
valid_sources[0x18]	433	1		T23	2		T22	5		T56	1
valid_sources[0x19]	272	1		T6	4		T23	4		T22	4
valid_sources[0x1a]	440	1		T6	4		T23	4		T28	1
valid_sources[0x1b]	341	1		T6	2		T8	1		T23	2
valid_sources[0x1c]	387	1		T6	2		T22	9		T56	2
valid_sources[0x1d]	260	1		T5	10		T6	3		T23	6
valid_sources[0x1e]	376	1		T6	2		T23	1		T22	2
valid_sources[0x1f]	344	1		T23	3		T22	2		T56	3
valid_sources[0x20]	431	1		T6	5		T23	5		T56	4
valid_sources[0x21]	266	1		T6	1		T23	2		T22	6
valid_sources[0x22]	362	1		T6	6		T23	5		T22	8
valid_sources[0x23]	312	1		T6	4		T22	3		T24	2
valid_sources[0x24]	360	1		T6	1		T23	7		T22	9
valid_sources[0x25]	286	1		T6	5		T23	6		T22	10
valid_sources[0x26]	357	1		T6	3		T7	82		T23	7
valid_sources[0x27]	382	1		T6	3		T23	1		T22	12
valid_sources[0x28]	315	1		T6	2		T23	4		T22	11
valid_sources[0x29]	304	1		T6	1		T23	4		T22	5
valid_sources[0x2a]	329	1		T23	3		T22	9		T56	4
valid_sources[0x2b]	273	1		T6	2		T23	1		T22	4
valid_sources[0x2c]	375	1		T6	5		T23	1		T22	2
valid_sources[0x2d]	305	1		T6	3		T28	1		T22	5
valid_sources[0x2e]	281	1		T6	1		T23	1		T22	3
valid_sources[0x2f]	334	1		T6	6		T23	3		T28	3
valid_sources[0x30]	270	1		T23	1		T22	2		T56	2
valid_sources[0x31]	548	1		T6	2		T23	1		T22	7
valid_sources[0x32]	315	1		T6	1		T23	7		T22	5
valid_sources[0x33]	254	1		T6	1		T23	3		T22	12
valid_sources[0x34]	460	1		T6	4		T23	3		T22	11
valid_sources[0x35]	304	1		T6	2		T23	4		T22	11
valid_sources[0x36]	206	1		T5	1		T6	1		T23	3
valid_sources[0x37]	370	1		T6	5		T23	8		T22	9
valid_sources[0x38]	309	1		T5	1		T6	1		T22	4
valid_sources[0x39]	297	1		T22	5		T56	3		T12	11
valid_sources[0x3a]	287	1		T6	3		T23	3		T22	6
valid_sources[0x3b]	255	1		T6	6		T23	8		T22	5
valid_sources[0x3c]	396	1		T6	2		T22	6		T56	4
valid_sources[0x3d]	368	1		T6	2		T23	9		T22	7
valid_sources[0x3e]	408	1		T23	8		T22	2		T24	1
valid_sources[0x3f]	533	1		T6	3		T7	83		T23	1
valid_sources[0x40]	328	1		T6	1		T22	10		T56	1
valid_sources[0x41]	345	1		T6	4		T23	8		T22	1
valid_sources[0x42]	305	1		T23	3		T22	6		T56	2
valid_sources[0x43]	288	1		T6	2		T23	6		T22	5
valid_sources[0x44]	1053	1		T6	1		T23	3		T22	3
valid_sources[0x45]	310	1		T6	5		T22	12		T56	2
valid_sources[0x46]	310	1		T6	5		T23	8		T22	4
valid_sources[0x47]	266	1		T5	8		T6	2		T23	3
valid_sources[0x48]	282	1		T6	4		T23	3		T22	6
valid_sources[0x49]	302	1		T6	1		T10	8		T22	8
valid_sources[0x4a]	408	1		T6	3		T23	7		T22	9
valid_sources[0x4b]	286	1		T5	12		T22	4		T24	1
valid_sources[0x4c]	368	1		T6	5		T23	2		T22	11
valid_sources[0x4d]	339	1		T5	6		T6	2		T23	2
valid_sources[0x4e]	342	1		T6	3		T23	4		T22	11
valid_sources[0x4f]	313	1		T6	8		T8	2		T23	2
valid_sources[0x50]	264	1		T6	2		T23	7		T28	1
valid_sources[0x51]	373	1		T5	3		T6	4		T23	3
valid_sources[0x52]	288	1		T6	3		T23	1		T22	5
valid_sources[0x53]	360	1		T6	5		T8	2		T23	6
valid_sources[0x54]	361	1		T6	5		T23	4		T22	6
valid_sources[0x55]	304	1		T5	6		T6	3		T23	1
valid_sources[0x56]	301	1		T6	6		T23	3		T22	8
valid_sources[0x57]	311	1		T6	1		T22	5		T24	1
valid_sources[0x58]	387	1		T6	1		T9	1		T22	1
valid_sources[0x59]	269	1		T23	5		T22	1		T12	7
valid_sources[0x5a]	349	1		T9	3		T22	5		T24	1
valid_sources[0x5b]	303	1		T3	1		T6	3		T23	1
valid_sources[0x5c]	310	1		T6	4		T23	2		T22	2
valid_sources[0x5d]	394	1		T5	16		T6	2		T9	3
valid_sources[0x5e]	253	1		T6	1		T23	2		T22	4
valid_sources[0x5f]	348	1		T5	36		T6	3		T23	4
valid_sources[0x60]	328	1		T6	2		T23	1		T22	9
valid_sources[0x61]	342	1		T6	1		T23	2		T22	7
valid_sources[0x62]	372	1		T6	1		T23	2		T22	10
valid_sources[0x63]	347	1		T6	1		T23	1		T22	4
valid_sources[0x64]	245	1		T23	4		T22	6		T56	2
valid_sources[0x65]	278	1		T3	1		T6	4		T22	5
valid_sources[0x66]	278	1		T6	1		T23	3		T22	10
valid_sources[0x67]	305	1		T5	17		T6	2		T23	2
valid_sources[0x68]	339	1		T5	10		T6	5		T8	4
valid_sources[0x69]	331	1		T6	1		T9	1		T22	1
valid_sources[0x6a]	288	1		T6	3		T23	11		T22	8
valid_sources[0x6b]	266	1		T6	1		T10	4		T23	1
valid_sources[0x6c]	366	1		T5	4		T6	1		T23	4
valid_sources[0x6d]	387	1		T6	1		T8	1		T22	5
valid_sources[0x6e]	358	1		T6	4		T23	4		T22	5
valid_sources[0x6f]	357	1		T6	1		T23	7		T22	5
valid_sources[0x70]	299	1		T2	2		T6	1		T23	4
valid_sources[0x71]	279	1		T6	2		T23	1		T22	6
valid_sources[0x72]	282	1		T6	5		T23	2		T22	5
valid_sources[0x73]	322	1		T6	1		T23	5		T22	4
valid_sources[0x74]	464	1		T6	2		T23	1		T22	8
valid_sources[0x75]	278	1		T6	5		T23	2		T28	1
valid_sources[0x76]	291	1		T6	2		T23	3		T22	13
valid_sources[0x77]	357	1		T5	13		T6	1		T10	19
valid_sources[0x78]	260	1		T6	1		T23	1		T22	5
valid_sources[0x79]	373	1		T6	4		T23	2		T22	2
valid_sources[0x7a]	370	1		T6	1		T22	2		T24	1
valid_sources[0x7b]	459	1		T6	5		T23	2		T22	14
valid_sources[0x7c]	305	1		T6	3		T23	7		T22	7
valid_sources[0x7d]	316	1		T5	4		T6	2		T23	1
valid_sources[0x7e]	350	1		T6	2		T23	1		T22	14
valid_sources[0x7f]	438	1		T6	5		T22	5		T24	1
valid_sources[0x80]	354	1		T6	2		T23	3		T22	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

22111

1

T1

1

T4

8

T5

15

values[0x0]

all_enables

biggest_size

17060

1

T1

1

T2

1

T4

7

values[0x1]

all_enables

biggest_size

15832

1

T3

1

T4

3

T5

21