Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
95.83 95.83 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block] 95.83 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
95.83 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 1 15 93.75


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 1 15 93.75 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 50720 1 T1 1 T2 2 T3 2
full_word 56005 1 T1 2 T2 1 T3 1



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 106565 1 T1 3 T2 3 T3 3
auto[TlIntgErrCmd] 58 1 T22 2 T30 4 T43 3
auto[TlIntgErrData] 46 1 T22 6 T30 3 T43 4
auto[TlIntgErrBoth] 56 1 T22 2 T30 3 T43 3



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 56356 1 T1 2 T2 2 T3 2
auto[1] 50369 1 T1 1 T2 1 T3 1



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 1 15 93.75 1


Automatically Generated Cross Bins for cr_all

Uncovered bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTNUMBER
[auto[TlIntgErrBoth]] [full_word] [auto[0]] 0 1 1


Covered bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 34011 1 T1 1 T2 2 T3 2
auto[TlIntgErrNone] partial auto[1] 16560 1 T4 1 T5 17 T6 902
auto[TlIntgErrNone] full_word auto[0] 22271 1 T1 1 T4 8 T5 15
auto[TlIntgErrNone] full_word auto[1] 33723 1 T1 1 T2 1 T3 1
auto[TlIntgErrCmd] partial auto[0] 24 1 T22 2 T32 4 T58 2
auto[TlIntgErrCmd] partial auto[1] 29 1 T30 4 T43 3 T32 3
auto[TlIntgErrCmd] full_word auto[0] 2 1 T59 2 - - - -
auto[TlIntgErrCmd] full_word auto[1] 3 1 T60 1 T61 1 T62 1
auto[TlIntgErrData] partial auto[0] 22 1 T22 3 T30 2 T43 1
auto[TlIntgErrData] partial auto[1] 19 1 T22 3 T30 1 T43 2
auto[TlIntgErrData] full_word auto[0] 1 1 T43 1 - - - -
auto[TlIntgErrData] full_word auto[1] 4 1 T58 1 T63 1 T61 1
auto[TlIntgErrBoth] partial auto[0] 25 1 T30 1 T43 1 T32 3
auto[TlIntgErrBoth] partial auto[1] 30 1 T22 2 T30 2 T43 2
auto[TlIntgErrBoth] full_word auto[1] 1 1 T63 1 - - - -

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