Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
72.68	83.19	35.82	89.24		55.17	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	759040	11664	0	0
ep_in_enable_rd_A	759040	798	0	0
ep_out_enable_rd_A	759040	848	0	0
in_iso_rd_A	759040	991	0	0
intr_enable_rd_A	759040	1345	0	0
out_iso_rd_A	759040	931	0	0
phy_config_rd_A	759040	745	0	0
phy_pins_drive_rd_A	759040	741	0	0
rxenable_setup_rd_A	759040	992	0	0
set_nak_out_rd_A	759040	889	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	759040	11664	0	0
T6	4495	819	0	0
T10	1436	2	0	0
T13	3199	11	0	0
T16	8006	443	0	0
T17	0	881	0	0
T18	0	2	0	0
T22	19611	2	0	0
T30	0	4	0	0
T31	0	700	0	0
T36	2946	0	0	0
T37	1646	0	0	0
T38	2416	0	0	0
T39	3319	0	0	0
T40	2424	0	0	0
T43	0	2	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	759040	798	0	0
T7	2420	5	0	0
T10	1436	4	0	0
T16	8006	0	0	0
T20	3839	16	0	0
T21	7551	62	0	0
T23	7501	15	0	0
T30	0	126	0	0
T36	2946	0	0	0
T37	1646	0	0	0
T38	0	42	0	0
T39	0	120	0	0
T47	1091	0	0	0
T48	1309	0	0	0
T50	0	38	0	0
T57	0	7	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	759040	848	0	0
T7	2420	2	0	0
T10	1436	7	0	0
T16	8006	0	0	0
T18	0	2	0	0
T20	3839	17	0	0
T21	7551	19	0	0
T23	7501	69	0	0
T30	0	171	0	0
T36	2946	0	0	0
T37	1646	0	0	0
T38	0	4	0	0
T39	0	84	0	0
T47	1091	0	0	0
T48	1309	0	0	0
T50	0	7	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	759040	991	0	0
T7	2420	50	0	0
T10	1436	7	0	0
T16	8006	0	0	0
T18	0	3	0	0
T20	3839	20	0	0
T21	7551	73	0	0
T23	7501	34	0	0
T30	0	216	0	0
T36	2946	0	0	0
T37	1646	0	0	0
T38	0	45	0	0
T39	0	9	0	0
T47	1091	0	0	0
T48	1309	0	0	0
T50	0	32	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	759040	1345	0	0
T4	1241	16	0	0
T7	2420	1	0	0
T8	1472	11	0	0
T10	1436	2	0	0
T16	8006	0	0	0
T20	3839	6	0	0
T21	7551	46	0	0
T23	7501	23	0	0
T38	0	63	0	0
T39	0	128	0	0
T42	0	9	0	0
T47	1091	0	0	0
T48	1309	0	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	759040	931	0	0
T7	2420	1	0	0
T10	1436	4	0	0
T16	8006	0	0	0
T18	0	8	0	0
T20	3839	36	0	0
T21	7551	45	0	0
T23	7501	72	0	0
T30	0	200	0	0
T36	2946	0	0	0
T37	1646	0	0	0
T38	0	46	0	0
T39	0	10	0	0
T47	1091	0	0	0
T48	1309	0	0	0
T50	0	2	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	759040	745	0	0
T7	2420	32	0	0
T16	8006	0	0	0
T18	0	3	0	0
T21	7551	34	0	0
T23	7501	102	0	0
T30	0	162	0	0
T36	2946	0	0	0
T37	1646	0	0	0
T38	2416	4	0	0
T39	3319	10	0	0
T47	1091	0	0	0
T48	1309	0	0	0
T50	0	6	0	0
T52	0	4	0	0
T57	0	30	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	759040	741	0	0
T7	2420	26	0	0
T10	1436	1	0	0
T16	8006	0	0	0
T18	0	5	0	0
T20	3839	26	0	0
T21	7551	18	0	0
T23	7501	20	0	0
T30	0	226	0	0
T36	2946	0	0	0
T37	1646	0	0	0
T38	0	40	0	0
T39	0	32	0	0
T47	1091	0	0	0
T48	1309	0	0	0
T50	0	15	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	759040	992	0	0
T7	2420	26	0	0
T10	1436	4	0	0
T16	8006	0	0	0
T18	0	7	0	0
T20	3839	17	0	0
T21	7551	24	0	0
T23	7501	30	0	0
T30	0	280	0	0
T36	2946	0	0	0
T37	1646	0	0	0
T38	0	46	0	0
T39	0	32	0	0
T47	1091	0	0	0
T48	1309	0	0	0
T50	0	43	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	759040	889	0	0
T7	2420	44	0	0
T10	1436	5	0	0
T16	8006	0	0	0
T18	0	3	0	0
T20	3839	2	0	0
T21	7551	5	0	0
T23	7501	88	0	0
T30	0	276	0	0
T36	2946	0	0	0
T37	1646	0	0	0
T38	0	4	0	0
T39	0	47	0	0
T47	1091	0	0	0
T48	1309	0	0	0
T50	0	39	0	0