Line Coverage for Instance : tb.dut.usbdev_avfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 19 | 86.36 |
ALWAYS | 70 | 4 | 4 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 165 | 2 | 1 | 50.00 |
CONT_ASSIGN | 175 | 1 | 0 | 0.00 |
CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
CONT_ASSIGN | 182 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
84 |
1 |
1 |
85 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
98 |
1 |
1 |
99 |
1 |
1 |
100 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
162 |
1 |
1 |
165 |
1 |
1 |
166 |
0 |
1 |
|
|
|
MISSING_ELSE |
175 |
0 |
1 |
176 |
1 |
1 |
182 |
0 |
1 |
Cond Coverage for Instance : tb.dut.usbdev_avfifo
| Total | Covered | Percent |
Conditions | 24 | 10 | 41.67 |
Logical | 24 | 10 | 41.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.usbdev_avfifo
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
5 |
62.50 |
TERNARY |
88 |
3 |
1 |
33.33 |
IF |
70 |
3 |
3 |
100.00 |
IF |
165 |
2 |
1 |
50.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 88 (gen_normal_fifo.full) ?
-2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Not Covered |
|
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 70 if ((!rst_ni))
-2-: 72 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 165 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.usbdev_avfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17813 |
0 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17813 |
15288 |
0 |
0 |
T1 |
4138 |
3275 |
0 |
0 |
T2 |
5273 |
4438 |
0 |
0 |
T3 |
8402 |
7575 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17813 |
15288 |
0 |
0 |
T1 |
4138 |
3275 |
0 |
0 |
T2 |
5273 |
4438 |
0 |
0 |
T3 |
8402 |
7575 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17813 |
15288 |
0 |
0 |
T1 |
4138 |
3275 |
0 |
0 |
T2 |
5273 |
4438 |
0 |
0 |
T3 |
8402 |
7575 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17813 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.usbdev_rxfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 20 | 90.91 |
ALWAYS | 70 | 4 | 4 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 165 | 2 | 1 | 50.00 |
CONT_ASSIGN | 175 | 1 | 0 | 0.00 |
CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
84 |
1 |
1 |
85 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
98 |
1 |
1 |
99 |
1 |
1 |
100 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
162 |
1 |
1 |
165 |
1 |
1 |
166 |
0 |
1 |
|
|
|
MISSING_ELSE |
175 |
0 |
1 |
176 |
1 |
1 |
180 |
1 |
1 |
Cond Coverage for Instance : tb.dut.usbdev_rxfifo
| Total | Covered | Percent |
Conditions | 26 | 11 | 42.31 |
Logical | 26 | 11 | 42.31 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.usbdev_rxfifo
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
6 |
60.00 |
TERNARY |
88 |
3 |
1 |
33.33 |
TERNARY |
180 |
2 |
1 |
50.00 |
IF |
70 |
3 |
3 |
100.00 |
IF |
165 |
2 |
1 |
50.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 88 (gen_normal_fifo.full) ?
-2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Not Covered |
|
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 180 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 70 if ((!rst_ni))
-2-: 72 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 165 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.usbdev_rxfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17813 |
0 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17813 |
15288 |
0 |
0 |
T1 |
4138 |
3275 |
0 |
0 |
T2 |
5273 |
4438 |
0 |
0 |
T3 |
8402 |
7575 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17813 |
15288 |
0 |
0 |
T1 |
4138 |
3275 |
0 |
0 |
T2 |
5273 |
4438 |
0 |
0 |
T3 |
8402 |
7575 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17813 |
15288 |
0 |
0 |
T1 |
4138 |
3275 |
0 |
0 |
T2 |
5273 |
4438 |
0 |
0 |
T3 |
8402 |
7575 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17813 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
759040 |
175896 |
0 |
0 |
T1 |
4138 |
3 |
0 |
0 |
T2 |
5273 |
3 |
0 |
0 |
T3 |
8402 |
3 |
0 |
0 |
T4 |
1241 |
22 |
0 |
0 |
T5 |
1855 |
691 |
0 |
0 |
T6 |
4495 |
3175 |
0 |
0 |
T7 |
2420 |
402 |
0 |
0 |
T8 |
1472 |
22 |
0 |
0 |
T9 |
1338 |
22 |
0 |
0 |
T10 |
1436 |
168 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
759040 |
731465 |
0 |
0 |
T1 |
4138 |
3275 |
0 |
0 |
T2 |
5273 |
4438 |
0 |
0 |
T3 |
8402 |
7575 |
0 |
0 |
T4 |
1241 |
1185 |
0 |
0 |
T5 |
1855 |
1755 |
0 |
0 |
T6 |
4495 |
4436 |
0 |
0 |
T7 |
2420 |
2357 |
0 |
0 |
T8 |
1472 |
1422 |
0 |
0 |
T9 |
1338 |
1284 |
0 |
0 |
T10 |
1436 |
1333 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
759040 |
731465 |
0 |
0 |
T1 |
4138 |
3275 |
0 |
0 |
T2 |
5273 |
4438 |
0 |
0 |
T3 |
8402 |
7575 |
0 |
0 |
T4 |
1241 |
1185 |
0 |
0 |
T5 |
1855 |
1755 |
0 |
0 |
T6 |
4495 |
4436 |
0 |
0 |
T7 |
2420 |
2357 |
0 |
0 |
T8 |
1472 |
1422 |
0 |
0 |
T9 |
1338 |
1284 |
0 |
0 |
T10 |
1436 |
1333 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
759040 |
731465 |
0 |
0 |
T1 |
4138 |
3275 |
0 |
0 |
T2 |
5273 |
4438 |
0 |
0 |
T3 |
8402 |
7575 |
0 |
0 |
T4 |
1241 |
1185 |
0 |
0 |
T5 |
1855 |
1755 |
0 |
0 |
T6 |
4495 |
4436 |
0 |
0 |
T7 |
2420 |
2357 |
0 |
0 |
T8 |
1472 |
1422 |
0 |
0 |
T9 |
1338 |
1284 |
0 |
0 |
T10 |
1436 |
1333 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
152 |
152 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
759040 |
163326 |
0 |
0 |
T1 |
4138 |
3 |
0 |
0 |
T2 |
5273 |
3 |
0 |
0 |
T3 |
8402 |
3 |
0 |
0 |
T4 |
1241 |
94 |
0 |
0 |
T5 |
1855 |
346 |
0 |
0 |
T6 |
4495 |
1592 |
0 |
0 |
T7 |
2420 |
775 |
0 |
0 |
T8 |
1472 |
105 |
0 |
0 |
T9 |
1338 |
22 |
0 |
0 |
T10 |
1436 |
326 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
759040 |
731465 |
0 |
0 |
T1 |
4138 |
3275 |
0 |
0 |
T2 |
5273 |
4438 |
0 |
0 |
T3 |
8402 |
7575 |
0 |
0 |
T4 |
1241 |
1185 |
0 |
0 |
T5 |
1855 |
1755 |
0 |
0 |
T6 |
4495 |
4436 |
0 |
0 |
T7 |
2420 |
2357 |
0 |
0 |
T8 |
1472 |
1422 |
0 |
0 |
T9 |
1338 |
1284 |
0 |
0 |
T10 |
1436 |
1333 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
759040 |
731465 |
0 |
0 |
T1 |
4138 |
3275 |
0 |
0 |
T2 |
5273 |
4438 |
0 |
0 |
T3 |
8402 |
7575 |
0 |
0 |
T4 |
1241 |
1185 |
0 |
0 |
T5 |
1855 |
1755 |
0 |
0 |
T6 |
4495 |
4436 |
0 |
0 |
T7 |
2420 |
2357 |
0 |
0 |
T8 |
1472 |
1422 |
0 |
0 |
T9 |
1338 |
1284 |
0 |
0 |
T10 |
1436 |
1333 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
759040 |
731465 |
0 |
0 |
T1 |
4138 |
3275 |
0 |
0 |
T2 |
5273 |
4438 |
0 |
0 |
T3 |
8402 |
7575 |
0 |
0 |
T4 |
1241 |
1185 |
0 |
0 |
T5 |
1855 |
1755 |
0 |
0 |
T6 |
4495 |
4436 |
0 |
0 |
T7 |
2420 |
2357 |
0 |
0 |
T8 |
1472 |
1422 |
0 |
0 |
T9 |
1338 |
1284 |
0 |
0 |
T10 |
1436 |
1333 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
152 |
152 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
759040 |
30901 |
0 |
0 |
T6 |
4495 |
388 |
0 |
0 |
T10 |
1436 |
65 |
0 |
0 |
T11 |
7167 |
3070 |
0 |
0 |
T12 |
11788 |
1535 |
0 |
0 |
T13 |
3199 |
1016 |
0 |
0 |
T14 |
2217 |
1001 |
0 |
0 |
T15 |
4756 |
849 |
0 |
0 |
T16 |
0 |
513 |
0 |
0 |
T17 |
0 |
450 |
0 |
0 |
T18 |
0 |
21 |
0 |
0 |
T19 |
1022 |
0 |
0 |
0 |
T20 |
3839 |
0 |
0 |
0 |
T21 |
7551 |
0 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
759040 |
731465 |
0 |
0 |
T1 |
4138 |
3275 |
0 |
0 |
T2 |
5273 |
4438 |
0 |
0 |
T3 |
8402 |
7575 |
0 |
0 |
T4 |
1241 |
1185 |
0 |
0 |
T5 |
1855 |
1755 |
0 |
0 |
T6 |
4495 |
4436 |
0 |
0 |
T7 |
2420 |
2357 |
0 |
0 |
T8 |
1472 |
1422 |
0 |
0 |
T9 |
1338 |
1284 |
0 |
0 |
T10 |
1436 |
1333 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
759040 |
731465 |
0 |
0 |
T1 |
4138 |
3275 |
0 |
0 |
T2 |
5273 |
4438 |
0 |
0 |
T3 |
8402 |
7575 |
0 |
0 |
T4 |
1241 |
1185 |
0 |
0 |
T5 |
1855 |
1755 |
0 |
0 |
T6 |
4495 |
4436 |
0 |
0 |
T7 |
2420 |
2357 |
0 |
0 |
T8 |
1472 |
1422 |
0 |
0 |
T9 |
1338 |
1284 |
0 |
0 |
T10 |
1436 |
1333 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
759040 |
731465 |
0 |
0 |
T1 |
4138 |
3275 |
0 |
0 |
T2 |
5273 |
4438 |
0 |
0 |
T3 |
8402 |
7575 |
0 |
0 |
T4 |
1241 |
1185 |
0 |
0 |
T5 |
1855 |
1755 |
0 |
0 |
T6 |
4495 |
4436 |
0 |
0 |
T7 |
2420 |
2357 |
0 |
0 |
T8 |
1472 |
1422 |
0 |
0 |
T9 |
1338 |
1284 |
0 |
0 |
T10 |
1436 |
1333 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
152 |
152 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
759040 |
36774 |
0 |
0 |
T6 |
4495 |
334 |
0 |
0 |
T10 |
1436 |
117 |
0 |
0 |
T11 |
7167 |
3070 |
0 |
0 |
T12 |
11788 |
1535 |
0 |
0 |
T13 |
3199 |
565 |
0 |
0 |
T14 |
2217 |
501 |
0 |
0 |
T15 |
4756 |
1522 |
0 |
0 |
T16 |
0 |
1646 |
0 |
0 |
T17 |
0 |
437 |
0 |
0 |
T18 |
0 |
66 |
0 |
0 |
T19 |
1022 |
0 |
0 |
0 |
T20 |
3839 |
0 |
0 |
0 |
T21 |
7551 |
0 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
759040 |
731465 |
0 |
0 |
T1 |
4138 |
3275 |
0 |
0 |
T2 |
5273 |
4438 |
0 |
0 |
T3 |
8402 |
7575 |
0 |
0 |
T4 |
1241 |
1185 |
0 |
0 |
T5 |
1855 |
1755 |
0 |
0 |
T6 |
4495 |
4436 |
0 |
0 |
T7 |
2420 |
2357 |
0 |
0 |
T8 |
1472 |
1422 |
0 |
0 |
T9 |
1338 |
1284 |
0 |
0 |
T10 |
1436 |
1333 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
759040 |
731465 |
0 |
0 |
T1 |
4138 |
3275 |
0 |
0 |
T2 |
5273 |
4438 |
0 |
0 |
T3 |
8402 |
7575 |
0 |
0 |
T4 |
1241 |
1185 |
0 |
0 |
T5 |
1855 |
1755 |
0 |
0 |
T6 |
4495 |
4436 |
0 |
0 |
T7 |
2420 |
2357 |
0 |
0 |
T8 |
1472 |
1422 |
0 |
0 |
T9 |
1338 |
1284 |
0 |
0 |
T10 |
1436 |
1333 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
759040 |
731465 |
0 |
0 |
T1 |
4138 |
3275 |
0 |
0 |
T2 |
5273 |
4438 |
0 |
0 |
T3 |
8402 |
7575 |
0 |
0 |
T4 |
1241 |
1185 |
0 |
0 |
T5 |
1855 |
1755 |
0 |
0 |
T6 |
4495 |
4436 |
0 |
0 |
T7 |
2420 |
2357 |
0 |
0 |
T8 |
1472 |
1422 |
0 |
0 |
T9 |
1338 |
1284 |
0 |
0 |
T10 |
1436 |
1333 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
152 |
152 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
759040 |
139202 |
0 |
0 |
T1 |
4138 |
3 |
0 |
0 |
T2 |
5273 |
3 |
0 |
0 |
T3 |
8402 |
3 |
0 |
0 |
T4 |
1241 |
22 |
0 |
0 |
T5 |
1855 |
691 |
0 |
0 |
T6 |
4495 |
2233 |
0 |
0 |
T7 |
2420 |
402 |
0 |
0 |
T8 |
1472 |
22 |
0 |
0 |
T9 |
1338 |
22 |
0 |
0 |
T10 |
1436 |
82 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
759040 |
731465 |
0 |
0 |
T1 |
4138 |
3275 |
0 |
0 |
T2 |
5273 |
4438 |
0 |
0 |
T3 |
8402 |
7575 |
0 |
0 |
T4 |
1241 |
1185 |
0 |
0 |
T5 |
1855 |
1755 |
0 |
0 |
T6 |
4495 |
4436 |
0 |
0 |
T7 |
2420 |
2357 |
0 |
0 |
T8 |
1472 |
1422 |
0 |
0 |
T9 |
1338 |
1284 |
0 |
0 |
T10 |
1436 |
1333 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
759040 |
731465 |
0 |
0 |
T1 |
4138 |
3275 |
0 |
0 |
T2 |
5273 |
4438 |
0 |
0 |
T3 |
8402 |
7575 |
0 |
0 |
T4 |
1241 |
1185 |
0 |
0 |
T5 |
1855 |
1755 |
0 |
0 |
T6 |
4495 |
4436 |
0 |
0 |
T7 |
2420 |
2357 |
0 |
0 |
T8 |
1472 |
1422 |
0 |
0 |
T9 |
1338 |
1284 |
0 |
0 |
T10 |
1436 |
1333 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
759040 |
731465 |
0 |
0 |
T1 |
4138 |
3275 |
0 |
0 |
T2 |
5273 |
4438 |
0 |
0 |
T3 |
8402 |
7575 |
0 |
0 |
T4 |
1241 |
1185 |
0 |
0 |
T5 |
1855 |
1755 |
0 |
0 |
T6 |
4495 |
4436 |
0 |
0 |
T7 |
2420 |
2357 |
0 |
0 |
T8 |
1472 |
1422 |
0 |
0 |
T9 |
1338 |
1284 |
0 |
0 |
T10 |
1436 |
1333 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
152 |
152 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
759040 |
126552 |
0 |
0 |
T1 |
4138 |
3 |
0 |
0 |
T2 |
5273 |
3 |
0 |
0 |
T3 |
8402 |
3 |
0 |
0 |
T4 |
1241 |
94 |
0 |
0 |
T5 |
1855 |
346 |
0 |
0 |
T6 |
4495 |
1258 |
0 |
0 |
T7 |
2420 |
775 |
0 |
0 |
T8 |
1472 |
105 |
0 |
0 |
T9 |
1338 |
22 |
0 |
0 |
T10 |
1436 |
209 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
759040 |
731465 |
0 |
0 |
T1 |
4138 |
3275 |
0 |
0 |
T2 |
5273 |
4438 |
0 |
0 |
T3 |
8402 |
7575 |
0 |
0 |
T4 |
1241 |
1185 |
0 |
0 |
T5 |
1855 |
1755 |
0 |
0 |
T6 |
4495 |
4436 |
0 |
0 |
T7 |
2420 |
2357 |
0 |
0 |
T8 |
1472 |
1422 |
0 |
0 |
T9 |
1338 |
1284 |
0 |
0 |
T10 |
1436 |
1333 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
759040 |
731465 |
0 |
0 |
T1 |
4138 |
3275 |
0 |
0 |
T2 |
5273 |
4438 |
0 |
0 |
T3 |
8402 |
7575 |
0 |
0 |
T4 |
1241 |
1185 |
0 |
0 |
T5 |
1855 |
1755 |
0 |
0 |
T6 |
4495 |
4436 |
0 |
0 |
T7 |
2420 |
2357 |
0 |
0 |
T8 |
1472 |
1422 |
0 |
0 |
T9 |
1338 |
1284 |
0 |
0 |
T10 |
1436 |
1333 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
759040 |
731465 |
0 |
0 |
T1 |
4138 |
3275 |
0 |
0 |
T2 |
5273 |
4438 |
0 |
0 |
T3 |
8402 |
7575 |
0 |
0 |
T4 |
1241 |
1185 |
0 |
0 |
T5 |
1855 |
1755 |
0 |
0 |
T6 |
4495 |
4436 |
0 |
0 |
T7 |
2420 |
2357 |
0 |
0 |
T8 |
1472 |
1422 |
0 |
0 |
T9 |
1338 |
1284 |
0 |
0 |
T10 |
1436 |
1333 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
152 |
152 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 19 | 86.36 |
ALWAYS | 70 | 4 | 4 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 0 | 0.00 |
ALWAYS | 157 | 2 | 1 | 50.00 |
CONT_ASSIGN | 175 | 1 | 0 | 0.00 |
CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
84 |
1 |
1 |
85 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
98 |
1 |
1 |
99 |
1 |
1 |
100 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
154 |
0 |
1 |
157 |
1 |
1 |
158 |
0 |
1 |
|
|
|
MISSING_ELSE |
175 |
0 |
1 |
176 |
1 |
1 |
180 |
1 |
1 |
Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
| Total | Covered | Percent |
Conditions | 26 | 11 | 42.31 |
Logical | 26 | 11 | 42.31 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
6 |
60.00 |
TERNARY |
88 |
3 |
1 |
33.33 |
TERNARY |
180 |
2 |
1 |
50.00 |
IF |
70 |
3 |
3 |
100.00 |
IF |
165 |
2 |
1 |
50.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 88 (gen_normal_fifo.full) ?
-2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Not Covered |
|
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 180 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 70 if ((!rst_ni))
-2-: 72 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 165 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17813 |
0 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17813 |
15288 |
0 |
0 |
T1 |
4138 |
3275 |
0 |
0 |
T2 |
5273 |
4438 |
0 |
0 |
T3 |
8402 |
7575 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17813 |
15288 |
0 |
0 |
T1 |
4138 |
3275 |
0 |
0 |
T2 |
5273 |
4438 |
0 |
0 |
T3 |
8402 |
7575 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17813 |
15288 |
0 |
0 |
T1 |
4138 |
3275 |
0 |
0 |
T2 |
5273 |
4438 |
0 |
0 |
T3 |
8402 |
7575 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17813 |
0 |
0 |
0 |