Unified Coverage Report :: Module :: usbdev_reg_top

Module : usbdev_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.60	99.72	98.69			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	99.60	99.72	98.69			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.60	99.72	98.69			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.48	98.36	93.60	100.00		98.34	87.10

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
72.68	83.19	35.82	89.24		55.17	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_avbuffer	100.00	100.00	100.00			100.00
u_avbuffer0_qe	100.00	100.00				100.00
u_chk	100.00	100.00		100.00			100.00
u_configin_0_buffer_0	100.00	100.00	100.00			100.00
u_configin_0_pend_0	94.44	100.00	83.33			100.00
u_configin_0_rdy_0	100.00	100.00	100.00			100.00
u_configin_0_size_0	100.00	100.00	100.00			100.00
u_configin_10_buffer_10	100.00	100.00	100.00			100.00
u_configin_10_pend_10	94.44	100.00	83.33			100.00
u_configin_10_rdy_10	100.00	100.00	100.00			100.00
u_configin_10_size_10	100.00	100.00	100.00			100.00
u_configin_11_buffer_11	100.00	100.00	100.00			100.00
u_configin_11_pend_11	94.44	100.00	83.33			100.00
u_configin_11_rdy_11	100.00	100.00	100.00			100.00
u_configin_11_size_11	100.00	100.00	100.00			100.00
u_configin_1_buffer_1	100.00	100.00	100.00			100.00
u_configin_1_pend_1	94.44	100.00	83.33			100.00
u_configin_1_rdy_1	100.00	100.00	100.00			100.00
u_configin_1_size_1	100.00	100.00	100.00			100.00
u_configin_2_buffer_2	100.00	100.00	100.00			100.00
u_configin_2_pend_2	94.44	100.00	83.33			100.00
u_configin_2_rdy_2	100.00	100.00	100.00			100.00
u_configin_2_size_2	100.00	100.00	100.00			100.00
u_configin_3_buffer_3	100.00	100.00	100.00			100.00
u_configin_3_pend_3	94.44	100.00	83.33			100.00
u_configin_3_rdy_3	100.00	100.00	100.00			100.00
u_configin_3_size_3	100.00	100.00	100.00			100.00
u_configin_4_buffer_4	100.00	100.00	100.00			100.00
u_configin_4_pend_4	94.44	100.00	83.33			100.00
u_configin_4_rdy_4	100.00	100.00	100.00			100.00
u_configin_4_size_4	100.00	100.00	100.00			100.00
u_configin_5_buffer_5	100.00	100.00	100.00			100.00
u_configin_5_pend_5	94.44	100.00	83.33			100.00
u_configin_5_rdy_5	100.00	100.00	100.00			100.00
u_configin_5_size_5	100.00	100.00	100.00			100.00
u_configin_6_buffer_6	100.00	100.00	100.00			100.00
u_configin_6_pend_6	94.44	100.00	83.33			100.00
u_configin_6_rdy_6	100.00	100.00	100.00			100.00
u_configin_6_size_6	100.00	100.00	100.00			100.00
u_configin_7_buffer_7	100.00	100.00	100.00			100.00
u_configin_7_pend_7	94.44	100.00	83.33			100.00
u_configin_7_rdy_7	100.00	100.00	100.00			100.00
u_configin_7_size_7	100.00	100.00	100.00			100.00
u_configin_8_buffer_8	100.00	100.00	100.00			100.00
u_configin_8_pend_8	94.44	100.00	83.33			100.00
u_configin_8_rdy_8	100.00	100.00	100.00			100.00
u_configin_8_size_8	100.00	100.00	100.00			100.00
u_configin_9_buffer_9	100.00	100.00	100.00			100.00
u_configin_9_pend_9	94.44	100.00	83.33			100.00
u_configin_9_rdy_9	100.00	100.00	100.00			100.00
u_configin_9_size_9	100.00	100.00	100.00			100.00
u_data_toggle_clear0_qe	100.00	100.00				100.00
u_data_toggle_clear_clear_0	100.00	100.00	100.00			100.00
u_data_toggle_clear_clear_1	100.00	100.00	100.00			100.00
u_data_toggle_clear_clear_10	100.00	100.00	100.00			100.00
u_data_toggle_clear_clear_11	100.00	100.00	100.00			100.00
u_data_toggle_clear_clear_2	100.00	100.00	100.00			100.00
u_data_toggle_clear_clear_3	100.00	100.00	100.00			100.00
u_data_toggle_clear_clear_4	100.00	100.00	100.00			100.00
u_data_toggle_clear_clear_5	100.00	100.00	100.00			100.00
u_data_toggle_clear_clear_6	100.00	100.00	100.00			100.00
u_data_toggle_clear_clear_7	100.00	100.00	100.00			100.00
u_data_toggle_clear_clear_8	100.00	100.00	100.00			100.00
u_data_toggle_clear_clear_9	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_0	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_1	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_10	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_11	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_2	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_3	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_4	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_5	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_6	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_7	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_8	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_9	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_0	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_1	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_10	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_11	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_2	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_3	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_4	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_5	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_6	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_7	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_8	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_9	100.00	100.00	100.00			100.00
u_in_iso_iso_0	100.00	100.00	100.00			100.00
u_in_iso_iso_1	100.00	100.00	100.00			100.00
u_in_iso_iso_10	100.00	100.00	100.00			100.00
u_in_iso_iso_11	100.00	100.00	100.00			100.00
u_in_iso_iso_2	100.00	100.00	100.00			100.00
u_in_iso_iso_3	100.00	100.00	100.00			100.00
u_in_iso_iso_4	100.00	100.00	100.00			100.00
u_in_iso_iso_5	100.00	100.00	100.00			100.00
u_in_iso_iso_6	100.00	100.00	100.00			100.00
u_in_iso_iso_7	100.00	100.00	100.00			100.00
u_in_iso_iso_8	100.00	100.00	100.00			100.00
u_in_iso_iso_9	100.00	100.00	100.00			100.00
u_in_sent_sent_0	88.89	100.00	66.67			100.00
u_in_sent_sent_1	88.89	100.00	66.67			100.00
u_in_sent_sent_10	88.89	100.00	66.67			100.00
u_in_sent_sent_11	88.89	100.00	66.67			100.00
u_in_sent_sent_2	88.89	100.00	66.67			100.00
u_in_sent_sent_3	88.89	100.00	66.67			100.00
u_in_sent_sent_4	88.89	100.00	66.67			100.00
u_in_sent_sent_5	88.89	100.00	66.67			100.00
u_in_sent_sent_6	88.89	100.00	66.67			100.00
u_in_sent_sent_7	88.89	100.00	66.67			100.00
u_in_sent_sent_8	88.89	100.00	66.67			100.00
u_in_sent_sent_9	88.89	100.00	66.67			100.00
u_in_stall_endpoint_0	96.30	100.00	88.89			100.00
u_in_stall_endpoint_1	96.30	100.00	88.89			100.00
u_in_stall_endpoint_10	96.30	100.00	88.89			100.00
u_in_stall_endpoint_11	96.30	100.00	88.89			100.00
u_in_stall_endpoint_2	96.30	100.00	88.89			100.00
u_in_stall_endpoint_3	96.30	100.00	88.89			100.00
u_in_stall_endpoint_4	96.30	100.00	88.89			100.00
u_in_stall_endpoint_5	96.30	100.00	88.89			100.00
u_in_stall_endpoint_6	96.30	100.00	88.89			100.00
u_in_stall_endpoint_7	96.30	100.00	88.89			100.00
u_in_stall_endpoint_8	96.30	100.00	88.89			100.00
u_in_stall_endpoint_9	96.30	100.00	88.89			100.00
u_intr_enable_av_empty	100.00	100.00	100.00			100.00
u_intr_enable_av_overflow	100.00	100.00	100.00			100.00
u_intr_enable_disconnected	100.00	100.00	100.00			100.00
u_intr_enable_frame	100.00	100.00	100.00			100.00
u_intr_enable_host_lost	100.00	100.00	100.00			100.00
u_intr_enable_link_in_err	100.00	100.00	100.00			100.00
u_intr_enable_link_out_err	100.00	100.00	100.00			100.00
u_intr_enable_link_reset	100.00	100.00	100.00			100.00
u_intr_enable_link_resume	100.00	100.00	100.00			100.00
u_intr_enable_link_suspend	100.00	100.00	100.00			100.00
u_intr_enable_pkt_received	100.00	100.00	100.00			100.00
u_intr_enable_pkt_sent	100.00	100.00	100.00			100.00
u_intr_enable_powered	100.00	100.00	100.00			100.00
u_intr_enable_rx_bitstuff_err	100.00	100.00	100.00			100.00
u_intr_enable_rx_crc_err	100.00	100.00	100.00			100.00
u_intr_enable_rx_full	100.00	100.00	100.00			100.00
u_intr_enable_rx_pid_err	100.00	100.00	100.00			100.00
u_intr_state_av_empty	100.00	100.00	100.00			100.00
u_intr_state_av_overflow	100.00	100.00	100.00			100.00
u_intr_state_disconnected	100.00	100.00	100.00			100.00
u_intr_state_frame	100.00	100.00	100.00			100.00
u_intr_state_host_lost	100.00	100.00	100.00			100.00
u_intr_state_link_in_err	100.00	100.00	100.00			100.00
u_intr_state_link_out_err	100.00	100.00	100.00			100.00
u_intr_state_link_reset	100.00	100.00	100.00			100.00
u_intr_state_link_resume	100.00	100.00	100.00			100.00
u_intr_state_link_suspend	100.00	100.00	100.00			100.00
u_intr_state_pkt_received	100.00	100.00	100.00			100.00
u_intr_state_pkt_sent	100.00	100.00	100.00			100.00
u_intr_state_powered	100.00	100.00	100.00			100.00
u_intr_state_rx_bitstuff_err	100.00	100.00	100.00			100.00
u_intr_state_rx_crc_err	100.00	100.00	100.00			100.00
u_intr_state_rx_full	100.00	100.00	100.00			100.00
u_intr_state_rx_pid_err	100.00	100.00	100.00			100.00
u_intr_test_av_empty	100.00	100.00
u_intr_test_av_overflow	100.00	100.00
u_intr_test_disconnected	100.00	100.00
u_intr_test_frame	100.00	100.00
u_intr_test_host_lost	100.00	100.00
u_intr_test_link_in_err	100.00	100.00
u_intr_test_link_out_err	100.00	100.00
u_intr_test_link_reset	100.00	100.00
u_intr_test_link_resume	100.00	100.00
u_intr_test_link_suspend	100.00	100.00
u_intr_test_pkt_received	100.00	100.00
u_intr_test_pkt_sent	100.00	100.00
u_intr_test_powered	100.00	100.00
u_intr_test_rx_bitstuff_err	100.00	100.00
u_intr_test_rx_crc_err	100.00	100.00
u_intr_test_rx_full	100.00	100.00
u_intr_test_rx_pid_err	100.00	100.00
u_out_iso_iso_0	100.00	100.00	100.00			100.00
u_out_iso_iso_1	100.00	100.00	100.00			100.00
u_out_iso_iso_10	100.00	100.00	100.00			100.00
u_out_iso_iso_11	100.00	100.00	100.00			100.00
u_out_iso_iso_2	100.00	100.00	100.00			100.00
u_out_iso_iso_3	100.00	100.00	100.00			100.00
u_out_iso_iso_4	100.00	100.00	100.00			100.00
u_out_iso_iso_5	100.00	100.00	100.00			100.00
u_out_iso_iso_6	100.00	100.00	100.00			100.00
u_out_iso_iso_7	100.00	100.00	100.00			100.00
u_out_iso_iso_8	100.00	100.00	100.00			100.00
u_out_iso_iso_9	100.00	100.00	100.00			100.00
u_out_stall_endpoint_0	96.30	100.00	88.89			100.00
u_out_stall_endpoint_1	96.30	100.00	88.89			100.00
u_out_stall_endpoint_10	96.30	100.00	88.89			100.00
u_out_stall_endpoint_11	96.30	100.00	88.89			100.00
u_out_stall_endpoint_2	96.30	100.00	88.89			100.00
u_out_stall_endpoint_3	96.30	100.00	88.89			100.00
u_out_stall_endpoint_4	96.30	100.00	88.89			100.00
u_out_stall_endpoint_5	96.30	100.00	88.89			100.00
u_out_stall_endpoint_6	96.30	100.00	88.89			100.00
u_out_stall_endpoint_7	96.30	100.00	88.89			100.00
u_out_stall_endpoint_8	96.30	100.00	88.89			100.00
u_out_stall_endpoint_9	96.30	100.00	88.89			100.00
u_phy_config_eop_single_bit	100.00	100.00	100.00			100.00
u_phy_config_pinflip	100.00	100.00	100.00			100.00
u_phy_config_tx_osc_test_mode	100.00	100.00	100.00			100.00
u_phy_config_tx_use_d_se0	100.00	100.00	100.00			100.00
u_phy_config_usb_ref_disable	100.00	100.00	100.00			100.00
u_phy_config_use_diff_rcvr	100.00	100.00	100.00			100.00
u_phy_pins_drive_d_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_dn_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_dn_pullup_en_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_dp_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_dp_pullup_en_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_en	100.00	100.00	100.00			100.00
u_phy_pins_drive_oe_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_rx_enable_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_se0_o	100.00	100.00	100.00			100.00
u_phy_pins_sense_pwr_sense	100.00	100.00
u_phy_pins_sense_rx_d_i	100.00	100.00
u_phy_pins_sense_rx_dn_i	100.00	100.00
u_phy_pins_sense_rx_dp_i	100.00	100.00
u_phy_pins_sense_tx_d_o	100.00	100.00
u_phy_pins_sense_tx_dn_o	100.00	100.00
u_phy_pins_sense_tx_dp_o	100.00	100.00
u_phy_pins_sense_tx_oe_o	100.00	100.00
u_phy_pins_sense_tx_se0_o	100.00	100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.39	97.14	96.43			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_rxenable_out_out_0	96.30	100.00	88.89			100.00
u_rxenable_out_out_1	96.30	100.00	88.89			100.00
u_rxenable_out_out_10	96.30	100.00	88.89			100.00
u_rxenable_out_out_11	96.30	100.00	88.89			100.00
u_rxenable_out_out_2	96.30	100.00	88.89			100.00
u_rxenable_out_out_3	96.30	100.00	88.89			100.00
u_rxenable_out_out_4	96.30	100.00	88.89			100.00
u_rxenable_out_out_5	96.30	100.00	88.89			100.00
u_rxenable_out_out_6	96.30	100.00	88.89			100.00
u_rxenable_out_out_7	96.30	100.00	88.89			100.00
u_rxenable_out_out_8	96.30	100.00	88.89			100.00
u_rxenable_out_out_9	96.30	100.00	88.89			100.00
u_rxenable_setup_setup_0	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_1	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_10	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_11	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_2	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_3	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_4	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_5	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_6	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_7	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_8	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_9	100.00	100.00	100.00			100.00
u_rxfifo_buffer	100.00	100.00
u_rxfifo_ep	100.00	100.00
u_rxfifo_setup	100.00	100.00
u_rxfifo_size	100.00	100.00
u_set_nak_out_enable_0	100.00	100.00	100.00			100.00
u_set_nak_out_enable_1	100.00	100.00	100.00			100.00
u_set_nak_out_enable_10	100.00	100.00	100.00			100.00
u_set_nak_out_enable_11	100.00	100.00	100.00			100.00
u_set_nak_out_enable_2	100.00	100.00	100.00			100.00
u_set_nak_out_enable_3	100.00	100.00	100.00			100.00
u_set_nak_out_enable_4	100.00	100.00	100.00			100.00
u_set_nak_out_enable_5	100.00	100.00	100.00			100.00
u_set_nak_out_enable_6	100.00	100.00	100.00			100.00
u_set_nak_out_enable_7	100.00	100.00	100.00			100.00
u_set_nak_out_enable_8	100.00	100.00	100.00			100.00
u_set_nak_out_enable_9	100.00	100.00	100.00			100.00
u_socket	98.24	98.75	98.21			96.00	100.00
u_usbctrl0_qe	100.00	100.00				100.00
u_usbctrl_device_address	96.30	100.00	88.89			100.00
u_usbctrl_enable	100.00	100.00	100.00			100.00
u_usbctrl_resume_link_active	100.00	100.00	100.00			100.00
u_usbstat_av_depth	66.67	66.67
u_usbstat_av_full	66.67	66.67
u_usbstat_frame	66.67	66.67
u_usbstat_host_lost	66.67	66.67
u_usbstat_link_state	66.67	66.67
u_usbstat_rx_depth	66.67	66.67
u_usbstat_rx_empty	66.67	66.67
u_usbstat_sense	66.67	66.67
u_wake_control_cdc	98.13	96.08	96.43			100.00	100.00
u_wake_control_suspend_req	100.00	100.00
u_wake_control_wake_ack	100.00	100.00
u_wake_events_bus_reset	58.89	66.67	50.00			60.00
u_wake_events_cdc	45.74	76.56	25.00			61.40	20.00
u_wake_events_disconnected	58.89	66.67	50.00			60.00
u_wake_events_module_active	58.89	66.67	50.00			60.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : usbdev_reg_top

	Line No.	Total	Covered	Percent
TOTAL		707	705	99.72
ALWAYS	75	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	102	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
ALWAYS	132	3	3	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	170	1	1	100.00
ALWAYS	714	1	0	0.00
CONT_ASSIGN	741	1	1	100.00
ALWAYS	755	8	8	100.00
CONT_ASSIGN	1716	1	1	100.00
CONT_ASSIGN	1731	1	1	100.00
CONT_ASSIGN	1747	1	1	100.00
CONT_ASSIGN	1763	1	1	100.00
CONT_ASSIGN	1779	1	1	100.00
CONT_ASSIGN	1795	1	1	100.00
CONT_ASSIGN	1811	1	1	100.00
CONT_ASSIGN	1827	1	1	100.00
CONT_ASSIGN	1843	1	1	100.00
CONT_ASSIGN	1859	1	1	100.00
CONT_ASSIGN	1875	1	1	100.00
CONT_ASSIGN	1891	1	1	100.00
CONT_ASSIGN	1907	1	1	100.00
CONT_ASSIGN	1923	1	1	100.00
CONT_ASSIGN	1939	1	1	100.00
CONT_ASSIGN	1955	1	1	100.00
CONT_ASSIGN	1971	1	1	100.00
CONT_ASSIGN	1987	1	1	100.00
CONT_ASSIGN	1993	1	1	100.00
CONT_ASSIGN	2007	1	1	100.00
CONT_ASSIGN	2075	1	1	100.00
CONT_ASSIGN	2918	1	1	100.00
CONT_ASSIGN	6970	1	1	100.00
CONT_ASSIGN	6998	1	1	100.00
CONT_ASSIGN	7026	1	1	100.00
CONT_ASSIGN	7054	1	1	100.00
CONT_ASSIGN	7082	1	1	100.00
CONT_ASSIGN	7110	1	1	100.00
CONT_ASSIGN	7138	1	1	100.00
CONT_ASSIGN	7166	1	1	100.00
CONT_ASSIGN	7194	1	1	100.00
CONT_ASSIGN	7222	1	1	100.00
CONT_ASSIGN	7250	1	1	100.00
CONT_ASSIGN	7278	1	1	100.00
CONT_ASSIGN	7830	1	1	100.00
CONT_ASSIGN	7845	1	1	100.00
CONT_ASSIGN	7861	1	1	100.00
CONT_ASSIGN	7866	1	0	0.00
ALWAYS	7952	37	37	100.00
CONT_ASSIGN	7991	1	1	100.00
ALWAYS	7995	1	1	100.00
CONT_ASSIGN	8035	1	1	100.00
CONT_ASSIGN	8037	1	1	100.00
CONT_ASSIGN	8039	1	1	100.00
CONT_ASSIGN	8041	1	1	100.00
CONT_ASSIGN	8043	1	1	100.00
CONT_ASSIGN	8045	1	1	100.00
CONT_ASSIGN	8047	1	1	100.00
CONT_ASSIGN	8049	1	1	100.00
CONT_ASSIGN	8051	1	1	100.00
CONT_ASSIGN	8053	1	1	100.00
CONT_ASSIGN	8055	1	1	100.00
CONT_ASSIGN	8057	1	1	100.00
CONT_ASSIGN	8059	1	1	100.00
CONT_ASSIGN	8061	1	1	100.00
CONT_ASSIGN	8063	1	1	100.00
CONT_ASSIGN	8065	1	1	100.00
CONT_ASSIGN	8067	1	1	100.00
CONT_ASSIGN	8069	1	1	100.00
CONT_ASSIGN	8070	1	1	100.00
CONT_ASSIGN	8072	1	1	100.00
CONT_ASSIGN	8074	1	1	100.00
CONT_ASSIGN	8076	1	1	100.00
CONT_ASSIGN	8078	1	1	100.00
CONT_ASSIGN	8080	1	1	100.00
CONT_ASSIGN	8082	1	1	100.00
CONT_ASSIGN	8084	1	1	100.00
CONT_ASSIGN	8086	1	1	100.00
CONT_ASSIGN	8088	1	1	100.00
CONT_ASSIGN	8090	1	1	100.00
CONT_ASSIGN	8092	1	1	100.00
CONT_ASSIGN	8094	1	1	100.00
CONT_ASSIGN	8096	1	1	100.00
CONT_ASSIGN	8098	1	1	100.00
CONT_ASSIGN	8100	1	1	100.00
CONT_ASSIGN	8102	1	1	100.00
CONT_ASSIGN	8104	1	1	100.00
CONT_ASSIGN	8105	1	1	100.00
CONT_ASSIGN	8107	1	1	100.00
CONT_ASSIGN	8109	1	1	100.00
CONT_ASSIGN	8111	1	1	100.00
CONT_ASSIGN	8113	1	1	100.00
CONT_ASSIGN	8115	1	1	100.00
CONT_ASSIGN	8117	1	1	100.00
CONT_ASSIGN	8119	1	1	100.00
CONT_ASSIGN	8121	1	1	100.00
CONT_ASSIGN	8123	1	1	100.00
CONT_ASSIGN	8125	1	1	100.00
CONT_ASSIGN	8127	1	1	100.00
CONT_ASSIGN	8129	1	1	100.00
CONT_ASSIGN	8131	1	1	100.00
CONT_ASSIGN	8133	1	1	100.00
CONT_ASSIGN	8135	1	1	100.00
CONT_ASSIGN	8137	1	1	100.00
CONT_ASSIGN	8139	1	1	100.00
CONT_ASSIGN	8140	1	1	100.00
CONT_ASSIGN	8142	1	1	100.00
CONT_ASSIGN	8143	1	1	100.00
CONT_ASSIGN	8145	1	1	100.00
CONT_ASSIGN	8147	1	1	100.00
CONT_ASSIGN	8149	1	1	100.00
CONT_ASSIGN	8150	1	1	100.00
CONT_ASSIGN	8152	1	1	100.00
CONT_ASSIGN	8154	1	1	100.00
CONT_ASSIGN	8156	1	1	100.00
CONT_ASSIGN	8158	1	1	100.00
CONT_ASSIGN	8160	1	1	100.00
CONT_ASSIGN	8162	1	1	100.00
CONT_ASSIGN	8164	1	1	100.00
CONT_ASSIGN	8166	1	1	100.00
CONT_ASSIGN	8168	1	1	100.00
CONT_ASSIGN	8170	1	1	100.00
CONT_ASSIGN	8172	1	1	100.00
CONT_ASSIGN	8174	1	1	100.00
CONT_ASSIGN	8175	1	1	100.00
CONT_ASSIGN	8177	1	1	100.00
CONT_ASSIGN	8179	1	1	100.00
CONT_ASSIGN	8181	1	1	100.00
CONT_ASSIGN	8183	1	1	100.00
CONT_ASSIGN	8185	1	1	100.00
CONT_ASSIGN	8187	1	1	100.00
CONT_ASSIGN	8189	1	1	100.00
CONT_ASSIGN	8191	1	1	100.00
CONT_ASSIGN	8193	1	1	100.00
CONT_ASSIGN	8195	1	1	100.00
CONT_ASSIGN	8197	1	1	100.00
CONT_ASSIGN	8199	1	1	100.00
CONT_ASSIGN	8200	1	1	100.00
CONT_ASSIGN	8201	1	1	100.00
CONT_ASSIGN	8203	1	1	100.00
CONT_ASSIGN	8204	1	1	100.00
CONT_ASSIGN	8205	1	1	100.00
CONT_ASSIGN	8207	1	1	100.00
CONT_ASSIGN	8209	1	1	100.00
CONT_ASSIGN	8211	1	1	100.00
CONT_ASSIGN	8213	1	1	100.00
CONT_ASSIGN	8215	1	1	100.00
CONT_ASSIGN	8217	1	1	100.00
CONT_ASSIGN	8219	1	1	100.00
CONT_ASSIGN	8221	1	1	100.00
CONT_ASSIGN	8223	1	1	100.00
CONT_ASSIGN	8225	1	1	100.00
CONT_ASSIGN	8227	1	1	100.00
CONT_ASSIGN	8229	1	1	100.00
CONT_ASSIGN	8230	1	1	100.00
CONT_ASSIGN	8232	1	1	100.00
CONT_ASSIGN	8234	1	1	100.00
CONT_ASSIGN	8236	1	1	100.00
CONT_ASSIGN	8238	1	1	100.00
CONT_ASSIGN	8240	1	1	100.00
CONT_ASSIGN	8242	1	1	100.00
CONT_ASSIGN	8244	1	1	100.00
CONT_ASSIGN	8246	1	1	100.00
CONT_ASSIGN	8248	1	1	100.00
CONT_ASSIGN	8250	1	1	100.00
CONT_ASSIGN	8252	1	1	100.00
CONT_ASSIGN	8254	1	1	100.00
CONT_ASSIGN	8255	1	1	100.00
CONT_ASSIGN	8257	1	1	100.00
CONT_ASSIGN	8259	1	1	100.00
CONT_ASSIGN	8261	1	1	100.00
CONT_ASSIGN	8263	1	1	100.00
CONT_ASSIGN	8265	1	1	100.00
CONT_ASSIGN	8267	1	1	100.00
CONT_ASSIGN	8269	1	1	100.00
CONT_ASSIGN	8271	1	1	100.00
CONT_ASSIGN	8273	1	1	100.00
CONT_ASSIGN	8275	1	1	100.00
CONT_ASSIGN	8277	1	1	100.00
CONT_ASSIGN	8279	1	1	100.00
CONT_ASSIGN	8280	1	1	100.00
CONT_ASSIGN	8282	1	1	100.00
CONT_ASSIGN	8284	1	1	100.00
CONT_ASSIGN	8286	1	1	100.00
CONT_ASSIGN	8288	1	1	100.00
CONT_ASSIGN	8290	1	1	100.00
CONT_ASSIGN	8292	1	1	100.00
CONT_ASSIGN	8294	1	1	100.00
CONT_ASSIGN	8296	1	1	100.00
CONT_ASSIGN	8298	1	1	100.00
CONT_ASSIGN	8300	1	1	100.00
CONT_ASSIGN	8302	1	1	100.00
CONT_ASSIGN	8304	1	1	100.00
CONT_ASSIGN	8305	1	1	100.00
CONT_ASSIGN	8307	1	1	100.00
CONT_ASSIGN	8309	1	1	100.00
CONT_ASSIGN	8311	1	1	100.00
CONT_ASSIGN	8313	1	1	100.00
CONT_ASSIGN	8315	1	1	100.00
CONT_ASSIGN	8317	1	1	100.00
CONT_ASSIGN	8319	1	1	100.00
CONT_ASSIGN	8321	1	1	100.00
CONT_ASSIGN	8323	1	1	100.00
CONT_ASSIGN	8325	1	1	100.00
CONT_ASSIGN	8327	1	1	100.00
CONT_ASSIGN	8329	1	1	100.00
CONT_ASSIGN	8330	1	1	100.00
CONT_ASSIGN	8332	1	1	100.00
CONT_ASSIGN	8334	1	1	100.00
CONT_ASSIGN	8336	1	1	100.00
CONT_ASSIGN	8338	1	1	100.00
CONT_ASSIGN	8340	1	1	100.00
CONT_ASSIGN	8342	1	1	100.00
CONT_ASSIGN	8344	1	1	100.00
CONT_ASSIGN	8346	1	1	100.00
CONT_ASSIGN	8348	1	1	100.00
CONT_ASSIGN	8350	1	1	100.00
CONT_ASSIGN	8352	1	1	100.00
CONT_ASSIGN	8354	1	1	100.00
CONT_ASSIGN	8355	1	1	100.00
CONT_ASSIGN	8357	1	1	100.00
CONT_ASSIGN	8359	1	1	100.00
CONT_ASSIGN	8361	1	1	100.00
CONT_ASSIGN	8363	1	1	100.00
CONT_ASSIGN	8364	1	1	100.00
CONT_ASSIGN	8366	1	1	100.00
CONT_ASSIGN	8368	1	1	100.00
CONT_ASSIGN	8370	1	1	100.00
CONT_ASSIGN	8372	1	1	100.00
CONT_ASSIGN	8373	1	1	100.00
CONT_ASSIGN	8375	1	1	100.00
CONT_ASSIGN	8377	1	1	100.00
CONT_ASSIGN	8379	1	1	100.00
CONT_ASSIGN	8381	1	1	100.00
CONT_ASSIGN	8382	1	1	100.00
CONT_ASSIGN	8384	1	1	100.00
CONT_ASSIGN	8386	1	1	100.00
CONT_ASSIGN	8388	1	1	100.00
CONT_ASSIGN	8390	1	1	100.00
CONT_ASSIGN	8391	1	1	100.00
CONT_ASSIGN	8393	1	1	100.00
CONT_ASSIGN	8395	1	1	100.00
CONT_ASSIGN	8397	1	1	100.00
CONT_ASSIGN	8399	1	1	100.00
CONT_ASSIGN	8400	1	1	100.00
CONT_ASSIGN	8402	1	1	100.00
CONT_ASSIGN	8404	1	1	100.00
CONT_ASSIGN	8406	1	1	100.00
CONT_ASSIGN	8408	1	1	100.00
CONT_ASSIGN	8409	1	1	100.00
CONT_ASSIGN	8411	1	1	100.00
CONT_ASSIGN	8413	1	1	100.00
CONT_ASSIGN	8415	1	1	100.00
CONT_ASSIGN	8417	1	1	100.00
CONT_ASSIGN	8418	1	1	100.00
CONT_ASSIGN	8420	1	1	100.00
CONT_ASSIGN	8422	1	1	100.00
CONT_ASSIGN	8424	1	1	100.00
CONT_ASSIGN	8426	1	1	100.00
CONT_ASSIGN	8427	1	1	100.00
CONT_ASSIGN	8429	1	1	100.00
CONT_ASSIGN	8431	1	1	100.00
CONT_ASSIGN	8433	1	1	100.00
CONT_ASSIGN	8435	1	1	100.00
CONT_ASSIGN	8436	1	1	100.00
CONT_ASSIGN	8438	1	1	100.00
CONT_ASSIGN	8440	1	1	100.00
CONT_ASSIGN	8442	1	1	100.00
CONT_ASSIGN	8444	1	1	100.00
CONT_ASSIGN	8445	1	1	100.00
CONT_ASSIGN	8447	1	1	100.00
CONT_ASSIGN	8449	1	1	100.00
CONT_ASSIGN	8451	1	1	100.00
CONT_ASSIGN	8453	1	1	100.00
CONT_ASSIGN	8454	1	1	100.00
CONT_ASSIGN	8456	1	1	100.00
CONT_ASSIGN	8458	1	1	100.00
CONT_ASSIGN	8460	1	1	100.00
CONT_ASSIGN	8462	1	1	100.00
CONT_ASSIGN	8463	1	1	100.00
CONT_ASSIGN	8465	1	1	100.00
CONT_ASSIGN	8467	1	1	100.00
CONT_ASSIGN	8469	1	1	100.00
CONT_ASSIGN	8471	1	1	100.00
CONT_ASSIGN	8473	1	1	100.00
CONT_ASSIGN	8475	1	1	100.00
CONT_ASSIGN	8477	1	1	100.00
CONT_ASSIGN	8479	1	1	100.00
CONT_ASSIGN	8481	1	1	100.00
CONT_ASSIGN	8483	1	1	100.00
CONT_ASSIGN	8485	1	1	100.00
CONT_ASSIGN	8487	1	1	100.00
CONT_ASSIGN	8488	1	1	100.00
CONT_ASSIGN	8490	1	1	100.00
CONT_ASSIGN	8492	1	1	100.00
CONT_ASSIGN	8494	1	1	100.00
CONT_ASSIGN	8496	1	1	100.00
CONT_ASSIGN	8498	1	1	100.00
CONT_ASSIGN	8500	1	1	100.00
CONT_ASSIGN	8502	1	1	100.00
CONT_ASSIGN	8504	1	1	100.00
CONT_ASSIGN	8506	1	1	100.00
CONT_ASSIGN	8508	1	1	100.00
CONT_ASSIGN	8510	1	1	100.00
CONT_ASSIGN	8512	1	1	100.00
CONT_ASSIGN	8513	1	1	100.00
CONT_ASSIGN	8515	1	1	100.00
CONT_ASSIGN	8517	1	1	100.00
CONT_ASSIGN	8519	1	1	100.00
CONT_ASSIGN	8521	1	1	100.00
CONT_ASSIGN	8523	1	1	100.00
CONT_ASSIGN	8525	1	1	100.00
CONT_ASSIGN	8527	1	1	100.00
CONT_ASSIGN	8529	1	1	100.00
CONT_ASSIGN	8531	1	1	100.00
CONT_ASSIGN	8533	1	1	100.00
CONT_ASSIGN	8535	1	1	100.00
CONT_ASSIGN	8537	1	1	100.00
CONT_ASSIGN	8538	1	1	100.00
CONT_ASSIGN	8539	1	1	100.00
CONT_ASSIGN	8541	1	1	100.00
CONT_ASSIGN	8543	1	1	100.00
CONT_ASSIGN	8545	1	1	100.00
CONT_ASSIGN	8547	1	1	100.00
CONT_ASSIGN	8549	1	1	100.00
CONT_ASSIGN	8551	1	1	100.00
CONT_ASSIGN	8553	1	1	100.00
CONT_ASSIGN	8555	1	1	100.00
CONT_ASSIGN	8557	1	1	100.00
CONT_ASSIGN	8558	1	1	100.00
CONT_ASSIGN	8560	1	1	100.00
CONT_ASSIGN	8562	1	1	100.00
CONT_ASSIGN	8564	1	1	100.00
CONT_ASSIGN	8566	1	1	100.00
CONT_ASSIGN	8568	1	1	100.00
CONT_ASSIGN	8570	1	1	100.00
CONT_ASSIGN	8571	1	1	100.00
ALWAYS	8577	37	37	100.00
ALWAYS	8618	276	276	100.00
CONT_ASSIGN	9012	1	1	100.00
ALWAYS	9014	4	4	100.00
CONT_ASSIGN	9035	1	1	100.00
CONT_ASSIGN	9036	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
75	1	1
76	1	1
77	1	1
78	1	1
			MISSING_ELSE
84	1	1
102	1	1
103	1	1
105	1	1
106	1	1
132	1	1
138	1	1
139	1	1
			MISSING_ELSE
169	1	1
170	1	1
714	0	1
741	1	1
755	1	1
756	1	1
757	1	1
758	1	1
759	1	1
760	1	1
761	1	1
762	1	1
1716	1	1
1731	1	1
1747	1	1
1763	1	1
1779	1	1
1795	1	1
1811	1	1
1827	1	1
1843	1	1
1859	1	1
1875	1	1
1891	1	1
1907	1	1
1923	1	1
1939	1	1
1955	1	1
1971	1	1
1987	1	1
1993	1	1
2007	1	1
2075	1	1
2918	1	1
6970	1	1
6998	1	1
7026	1	1
7054	1	1
7082	1	1
7110	1	1
7138	1	1
7166	1	1
7194	1	1
7222	1	1
7250	1	1
7278	1	1
7830	1	1
7845	1	1
7861	1	1
7866	0	1
7952	1	1
7953	1	1
7954	1	1
7955	1	1
7956	1	1
7957	1	1
7958	1	1
7959	1	1
7960	1	1
7961	1	1
7962	1	1
7963	1	1
7964	1	1
7965	1	1
7966	1	1
7967	1	1
7968	1	1
7969	1	1
7970	1	1
7971	1	1
7972	1	1
7973	1	1
7974	1	1
7975	1	1
7976	1	1
7977	1	1
7978	1	1
7979	1	1
7980	1	1
7981	1	1
7982	1	1
7983	1	1
7984	1	1
7985	1	1
7986	1	1
7987	1	1
7988	1	1
7991	1	1
7995	1	1
8035	1	1
8037	1	1
8039	1	1
8041	1	1
8043	1	1
8045	1	1
8047	1	1
8049	1	1
8051	1	1
8053	1	1
8055	1	1
8057	1	1
8059	1	1
8061	1	1
8063	1	1
8065	1	1
8067	1	1
8069	1	1
8070	1	1
8072	1	1
8074	1	1
8076	1	1
8078	1	1
8080	1	1
8082	1	1
8084	1	1
8086	1	1
8088	1	1
8090	1	1
8092	1	1
8094	1	1
8096	1	1
8098	1	1
8100	1	1
8102	1	1
8104	1	1
8105	1	1
8107	1	1
8109	1	1
8111	1	1
8113	1	1
8115	1	1
8117	1	1
8119	1	1
8121	1	1
8123	1	1
8125	1	1
8127	1	1
8129	1	1
8131	1	1
8133	1	1
8135	1	1
8137	1	1
8139	1	1
8140	1	1
8142	1	1
8143	1	1
8145	1	1
8147	1	1
8149	1	1
8150	1	1
8152	1	1
8154	1	1
8156	1	1
8158	1	1
8160	1	1
8162	1	1
8164	1	1
8166	1	1
8168	1	1
8170	1	1
8172	1	1
8174	1	1
8175	1	1
8177	1	1
8179	1	1
8181	1	1
8183	1	1
8185	1	1
8187	1	1
8189	1	1
8191	1	1
8193	1	1
8195	1	1
8197	1	1
8199	1	1
8200	1	1
8201	1	1
8203	1	1
8204	1	1
8205	1	1
8207	1	1
8209	1	1
8211	1	1
8213	1	1
8215	1	1
8217	1	1
8219	1	1
8221	1	1
8223	1	1
8225	1	1
8227	1	1
8229	1	1
8230	1	1
8232	1	1
8234	1	1
8236	1	1
8238	1	1
8240	1	1
8242	1	1
8244	1	1
8246	1	1
8248	1	1
8250	1	1
8252	1	1
8254	1	1
8255	1	1
8257	1	1
8259	1	1
8261	1	1
8263	1	1
8265	1	1
8267	1	1
8269	1	1
8271	1	1
8273	1	1
8275	1	1
8277	1	1
8279	1	1
8280	1	1
8282	1	1
8284	1	1
8286	1	1
8288	1	1
8290	1	1
8292	1	1
8294	1	1
8296	1	1
8298	1	1
8300	1	1
8302	1	1
8304	1	1
8305	1	1
8307	1	1
8309	1	1
8311	1	1
8313	1	1
8315	1	1
8317	1	1
8319	1	1
8321	1	1
8323	1	1
8325	1	1
8327	1	1
8329	1	1
8330	1	1
8332	1	1
8334	1	1
8336	1	1
8338	1	1
8340	1	1
8342	1	1
8344	1	1
8346	1	1
8348	1	1
8350	1	1
8352	1	1
8354	1	1
8355	1	1
8357	1	1
8359	1	1
8361	1	1
8363	1	1
8364	1	1
8366	1	1
8368	1	1
8370	1	1
8372	1	1
8373	1	1
8375	1	1
8377	1	1
8379	1	1
8381	1	1
8382	1	1
8384	1	1
8386	1	1
8388	1	1
8390	1	1
8391	1	1
8393	1	1
8395	1	1
8397	1	1
8399	1	1
8400	1	1
8402	1	1
8404	1	1
8406	1	1
8408	1	1
8409	1	1
8411	1	1
8413	1	1
8415	1	1
8417	1	1
8418	1	1
8420	1	1
8422	1	1
8424	1	1
8426	1	1
8427	1	1
8429	1	1
8431	1	1
8433	1	1
8435	1	1
8436	1	1
8438	1	1
8440	1	1
8442	1	1
8444	1	1
8445	1	1
8447	1	1
8449	1	1
8451	1	1
8453	1	1
8454	1	1
8456	1	1
8458	1	1
8460	1	1
8462	1	1
8463	1	1
8465	1	1
8467	1	1
8469	1	1
8471	1	1
8473	1	1
8475	1	1
8477	1	1
8479	1	1
8481	1	1
8483	1	1
8485	1	1
8487	1	1
8488	1	1
8490	1	1
8492	1	1
8494	1	1
8496	1	1
8498	1	1
8500	1	1
8502	1	1
8504	1	1
8506	1	1
8508	1	1
8510	1	1
8512	1	1
8513	1	1
8515	1	1
8517	1	1
8519	1	1
8521	1	1
8523	1	1
8525	1	1
8527	1	1
8529	1	1
8531	1	1
8533	1	1
8535	1	1
8537	1	1
8538	1	1
8539	1	1
8541	1	1
8543	1	1
8545	1	1
8547	1	1
8549	1	1
8551	1	1
8553	1	1
8555	1	1
8557	1	1
8558	1	1
8560	1	1
8562	1	1
8564	1	1
8566	1	1
8568	1	1
8570	1	1
8571	1	1
8577	1	1
8578	1	1
8579	1	1
8580	1	1
8581	1	1
8582	1	1
8583	1	1
8584	1	1
8585	1	1
8586	1	1
8587	1	1
8588	1	1
8589	1	1
8590	1	1
8591	1	1
8592	1	1
8593	1	1
8594	1	1
8595	1	1
8596	1	1
8597	1	1
8598	1	1
8599	1	1
8600	1	1
8601	1	1
8602	1	1
8603	1	1
8604	1	1
8605	1	1
8606	1	1
8607	1	1
8608	1	1
8609	1	1
8610	1	1
8611	1	1
8612	1	1
8613	1	1
8618	1	1
8619	1	1
8621	1	1
8622	1	1
8623	1	1
8624	1	1
8625	1	1
8626	1	1
8627	1	1
8628	1	1
8629	1	1
8630	1	1
8631	1	1
8632	1	1
8633	1	1
8634	1	1
8635	1	1
8636	1	1
8637	1	1
8641	1	1
8642	1	1
8643	1	1
8644	1	1
8645	1	1
8646	1	1
8647	1	1
8648	1	1
8649	1	1
8650	1	1
8651	1	1
8652	1	1
8653	1	1
8654	1	1
8655	1	1
8656	1	1
8657	1	1
8661	1	1
8662	1	1
8663	1	1
8664	1	1
8665	1	1
8666	1	1
8667	1	1
8668	1	1
8669	1	1
8670	1	1
8671	1	1
8672	1	1
8673	1	1
8674	1	1
8675	1	1
8676	1	1
8677	1	1
8681	1	1
8685	1	1
8686	1	1
8687	1	1
8691	1	1
8692	1	1
8693	1	1
8694	1	1
8695	1	1
8696	1	1
8697	1	1
8698	1	1
8699	1	1
8700	1	1
8701	1	1
8702	1	1
8706	1	1
8707	1	1
8708	1	1
8709	1	1
8710	1	1
8711	1	1
8712	1	1
8713	1	1
8714	1	1
8715	1	1
8716	1	1
8717	1	1
8721	1	1
8722	1	1
8723	1	1
8724	1	1
8725	1	1
8726	1	1
8727	1	1
8728	1	1
8732	1	1
8736	1	1
8737	1	1
8738	1	1
8739	1	1
8743	1	1
8744	1	1
8745	1	1
8746	1	1
8747	1	1
8748	1	1
8749	1	1
8750	1	1
8751	1	1
8752	1	1
8753	1	1
8754	1	1
8758	1	1
8759	1	1
8760	1	1
8761	1	1
8762	1	1
8763	1	1
8764	1	1
8765	1	1
8766	1	1
8767	1	1
8768	1	1
8769	1	1
8773	1	1
8774	1	1
8775	1	1
8776	1	1
8777	1	1
8778	1	1
8779	1	1
8780	1	1
8781	1	1
8782	1	1
8783	1	1
8784	1	1
8788	1	1
8789	1	1
8790	1	1
8791	1	1
8792	1	1
8793	1	1
8794	1	1
8795	1	1
8796	1	1
8797	1	1
8798	1	1
8799	1	1
8803	1	1
8804	1	1
8805	1	1
8806	1	1
8807	1	1
8808	1	1
8809	1	1
8810	1	1
8811	1	1
8812	1	1
8813	1	1
8814	1	1
8818	1	1
8819	1	1
8820	1	1
8821	1	1
8822	1	1
8823	1	1
8824	1	1
8825	1	1
8826	1	1
8827	1	1
8828	1	1
8829	1	1
8833	1	1
8834	1	1
8835	1	1
8836	1	1
8840	1	1
8841	1	1
8842	1	1
8843	1	1
8847	1	1
8848	1	1
8849	1	1
8850	1	1
8854	1	1
8855	1	1
8856	1	1
8857	1	1
8861	1	1
8862	1	1
8863	1	1
8864	1	1
8868	1	1
8869	1	1
8870	1	1
8871	1	1
8875	1	1
8876	1	1
8877	1	1
8878	1	1
8882	1	1
8883	1	1
8884	1	1
8885	1	1
8889	1	1
8890	1	1
8891	1	1
8892	1	1
8896	1	1
8897	1	1
8898	1	1
8899	1	1
8903	1	1
8904	1	1
8905	1	1
8906	1	1
8910	1	1
8911	1	1
8912	1	1
8913	1	1
8917	1	1
8918	1	1
8919	1	1
8920	1	1
8921	1	1
8922	1	1
8923	1	1
8924	1	1
8925	1	1
8926	1	1
8927	1	1
8928	1	1
8932	1	1
8933	1	1
8934	1	1
8935	1	1
8936	1	1
8937	1	1
8938	1	1
8939	1	1
8940	1	1
8941	1	1
8942	1	1
8943	1	1
8947	1	1
8948	1	1
8949	1	1
8950	1	1
8951	1	1
8952	1	1
8953	1	1
8954	1	1
8955	1	1
8956	1	1
8957	1	1
8958	1	1
8962	1	1
8963	1	1
8964	1	1
8965	1	1
8966	1	1
8967	1	1
8968	1	1
8969	1	1
8970	1	1
8974	1	1
8975	1	1
8976	1	1
8977	1	1
8978	1	1
8979	1	1
8980	1	1
8981	1	1
8982	1	1
8986	1	1
8987	1	1
8988	1	1
8989	1	1
8990	1	1
8991	1	1
8995	1	1
8998	1	1
9012	1	1
9014	1	1
9015	1	1
9017	1	1
9020	1	1
9035	1	1
9036	1	1

---

Cond Coverage for Module : usbdev_reg_top

	Total	Covered	Percent
Conditions	383	378	98.69
Logical	383	378	98.69
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T22,T16
1	1	Covered	T1,T2,T3

 LINE       77
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T30,T43

 LINE       84
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T22,T30,T43
1	0	0	Covered	T1,T2,T3

 LINE       132
 EXPRESSION ((tl_i.a_address[(AW - 1):0] inside {[2048:4095]}) ? 1'b0 : 1'b1)
             ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       170
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T22,T30,T43
0	1	0	Covered	T6,T17,T31
1	0	0	Covered	T6,T16,T17

 LINE       7953
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_INTR_STATE_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       7954
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_INTR_ENABLE_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       7955
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_INTR_TEST_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T8

 LINE       7956
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_ALERT_TEST_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       7957
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_USBCTRL_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       7958
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_EP_OUT_ENABLE_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       7959
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_EP_IN_ENABLE_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       7960
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_USBSTAT_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       7961
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_AVBUFFER_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T10,T11

 LINE       7962
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_RXFIFO_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       7963
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_RXENABLE_SETUP_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       7964
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_RXENABLE_OUT_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       7965
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_SET_NAK_OUT_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T6

 LINE       7966
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_IN_SENT_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       7967
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_OUT_STALL_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       7968
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_IN_STALL_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       7969
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_0_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       7970
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_1_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       7971
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_2_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       7972
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_3_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       7973
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_4_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       7974
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_5_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       7975
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_6_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       7976
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_7_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       7977
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_8_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       7978
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_9_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       7979
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_10_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       7980
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_11_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       7981
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_OUT_ISO_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       7982
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_IN_ISO_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       7983
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_DATA_TOGGLE_CLEAR_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       7984
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_PHY_PINS_SENSE_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       7985
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_PHY_PINS_DRIVE_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       7986
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_PHY_CONFIG_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       7987
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_WAKE_CONTROL_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       7988
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_WAKE_EVENTS_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

 LINE       7991
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       7991
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       7995
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[1] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[2] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[11] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[12] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[13] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[14] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[28] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[29] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[30] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[31] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[32] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[33] & ((|(4'b1 & (~reg_be))))) | (addr_hit[34] & ((|(4'b1 & (~reg_be))))) | (addr_hit[35] & ((|(4'b0011 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T17,T31

 LINE       7995
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b0111 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b0111 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b0111 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b0111 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b0111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b0011 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b0011 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b0011 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b0011 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b0011 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b0011 & (~reg_be))))) | 
     30  (addr_hit[29] & ((|(4'b0011 & (~reg_be))))) | 
     31  (addr_hit[30] & ((|(4'b0011 & (~reg_be))))) | 
     32  (addr_hit[31] & ((|(4'b0111 & (~reg_be))))) | 
     33  (addr_hit[32] & ((|(4'b0111 & (~reg_be))))) | 
     34  (addr_hit[33] & ((|(4'b1 & (~reg_be))))) | 
     35  (addr_hit[34] & ((|(4'b1 & (~reg_be))))) | 
     36  (addr_hit[35] & ((|(4'b0011 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T1,T2,T3
36 (addr_hit[35] & ((|(4'...	Covered	T5,T6,T7
35 (addr_hit[34] & ((|(4'...	Covered	T5,T6,T11
34 (addr_hit[33] & ((|(4'...	Covered	T5,T6,T10
33 (addr_hit[32] & ((|(4'...	Covered	T5,T6,T7
32 (addr_hit[31] & ((|(4'...	Covered	T6,T11,T56
31 (addr_hit[30] & ((|(4'...	Covered	T5,T6,T7
30 (addr_hit[29] & ((|(4'...	Covered	T5,T6,T7
29 (addr_hit[28] & ((|(4'...	Covered	T5,T6,T7
28 (addr_hit[27] & ((|(4'...	Covered	T5,T6,T7
27 (addr_hit[26] & ((|(4'...	Covered	T5,T6,T7
26 (addr_hit[25] & ((|(4'...	Covered	T5,T6,T7
25 (addr_hit[24] & ((|(4'...	Covered	T5,T6,T7
24 (addr_hit[23] & ((|(4'...	Covered	T5,T6,T7
23 (addr_hit[22] & ((|(4'...	Covered	T5,T6,T7
22 (addr_hit[21] & ((|(4'...	Covered	T5,T6,T7
21 (addr_hit[20] & ((|(4'...	Covered	T5,T6,T7
20 (addr_hit[19] & ((|(4'...	Covered	T5,T6,T7
19 (addr_hit[18] & ((|(4'...	Covered	T5,T6,T7
18 (addr_hit[17] & ((|(4'...	Covered	T5,T6,T7
17 (addr_hit[16] & ((|(4'...	Covered	T6,T7,T10
16 (addr_hit[15] & ((|(4'...	Covered	T5,T6,T7
15 (addr_hit[14] & ((|(4'...	Covered	T5,T6,T10
14 (addr_hit[13] & ((|(4'...	Covered	T5,T6,T7
13 (addr_hit[12] & ((|(4'...	Covered	T5,T6,T7
12 (addr_hit[11] & ((|(4'...	Covered	T5,T6,T10
11 (addr_hit[10] & ((|(4'...	Covered	T5,T6,T7
10 (addr_hit[9] & ((|(4'b...	Covered	T6,T7,T11
9 (addr_hit[8] & ((|(4'b...	Covered	T6,T10,T11
8 (addr_hit[7] & ((|(4'b...	Covered	T5,T6,T11
7 (addr_hit[6] & ((|(4'b...	Covered	T5,T6,T10
6 (addr_hit[5] & ((|(4'b...	Covered	T5,T6,T7
5 (addr_hit[4] & ((|(4'b...	Covered	T5,T6,T7
4 (addr_hit[3] & ((|(4'b...	Covered	T6,T11,T22
3 (addr_hit[2] & ((|(4'b...	Covered	T4,T6,T8
2 (addr_hit[1] & ((|(4'b...	Covered	T4,T5,T6
1 (addr_hit[0] & ((|(4'b...	Covered	T1,T2,T3

 LINE       7995
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       7995
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       7995
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T8
1	1	Covered	T4,T6,T8

 LINE       7995
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T6,T11,T22

 LINE       7995
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       7995
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       7995
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T23
1	1	Covered	T5,T6,T10

 LINE       7995
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T23
1	1	Covered	T5,T6,T11

 LINE       7995
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T23,T22
1	1	Covered	T6,T10,T11

 LINE       7995
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T6,T7,T11

 LINE       7995
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T11
1	1	Covered	T5,T6,T7

 LINE       7995
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T10

 LINE       7995
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T7
1	1	Covered	T5,T6,T7

 LINE       7995
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T23
1	1	Covered	T5,T6,T7

 LINE       7995
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T10

 LINE       7995
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       7995
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T23
1	1	Covered	T6,T7,T10

 LINE       7995
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       7995
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       7995
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       7995
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T10
1	1	Covered	T5,T6,T7

 LINE       7995
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T10
1	1	Covered	T5,T6,T7

 LINE       7995
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T10
1	1	Covered	T5,T6,T7

 LINE       7995
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       7995
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T23
1	1	Covered	T5,T6,T7

 LINE       7995
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T10
1	1	Covered	T5,T6,T7

 LINE       7995
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T23
1	1	Covered	T5,T6,T7

 LINE       7995
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       7995
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       7995
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T10
1	1	Covered	T5,T6,T7

 LINE       7995
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       7995
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T10
1	1	Covered	T6,T11,T56

 LINE       7995
 SUB-EXPRESSION (addr_hit[32] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       7995
 SUB-EXPRESSION (addr_hit[33] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T10

 LINE       7995
 SUB-EXPRESSION (addr_hit[34] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T10
1	1	Covered	T5,T6,T11

 LINE       7995
 SUB-EXPRESSION (addr_hit[35] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       8035
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T6,T17,T31
1	1	1	Covered	T1,T2,T3

 LINE       8070
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T6,T17,T31
1	1	1	Covered	T4,T5,T7

 LINE       8105
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T6,T8
1	1	0	Covered	T6,T31,T33
1	1	1	Covered	T4,T8,T9

 LINE       8140
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T7
1	1	0	Covered	T6,T17,T31
1	1	1	Covered	T5,T7,T23

 LINE       8143
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T7
1	1	0	Covered	T6,T17,T31
1	1	1	Covered	T5,T7,T23

 LINE       8150
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T7
1	1	0	Covered	T33,T34,T46
1	1	1	Covered	T5,T7,T23

 LINE       8175
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T7
1	1	0	Covered	T6,T17,T33
1	1	1	Covered	T5,T7,T23

 LINE       8200
 EXPRESSION (addr_hit[7] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T7
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       8201
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T10,T11
1	1	0	Covered	T17,T31,T34
1	1	1	Covered	T24,T25,T26

 LINE       8204
 EXPRESSION (addr_hit[9] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T7
1	1	0	Not Covered
1	1	1	Covered	T5,T7,T23

 LINE       8205
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T7
1	1	0	Covered	T6,T31,T33
1	1	1	Covered	T5,T7,T23

 LINE       8230
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T7
1	1	0	Covered	T6,T33,T46
1	1	1	Covered	T5,T7,T23

 LINE       8255
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T5,T6
1	1	0	Covered	T6,T17,T31
1	1	1	Covered	T5,T7,T23

 LINE       8280
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T7
1	1	0	Covered	T17,T31,T46
1	1	1	Covered	T5,T7,T23

 LINE       8305
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T7
1	1	0	Covered	T6,T31,T33
1	1	1	Covered	T5,T7,T23

 LINE       8330
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T7
1	1	0	Covered	T6,T31,T33
1	1	1	Covered	T5,T7,T10

 LINE       8355
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T7
1	1	0	Covered	T17,T31,T33
1	1	1	Covered	T5,T7,T23

 LINE       8364
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T7
1	1	0	Covered	T6,T31,T33
1	1	1	Covered	T5,T7,T23

 LINE       8373
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T7
1	1	0	Covered	T6,T31,T33
1	1	1	Covered	T5,T7,T10

 LINE       8382
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T7
1	1	0	Covered	T6,T31,T33
1	1	1	Covered	T5,T7,T10

 LINE       8391
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T7
1	1	0	Covered	T6,T31,T33
1	1	1	Covered	T5,T7,T23

 LINE       8400
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T7
1	1	0	Covered	T6,T31,T35
1	1	1	Covered	T5,T7,T23

 LINE       8409
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T7
1	1	0	Covered	T6,T31,T34
1	1	1	Covered	T5,T7,T10

 LINE       8418
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T7
1	1	0	Covered	T6,T17,T31
1	1	1	Covered	T5,T7,T10

 LINE       8427
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T7
1	1	0	Covered	T6,T17,T31
1	1	1	Covered	T5,T7,T23

 LINE       8436
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T7
1	1	0	Covered	T6,T17,T31
1	1	1	Covered	T5,T7,T10

 LINE       8445
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T7
1	1	0	Covered	T6,T31,T34
1	1	1	Covered	T5,T7,T23

 LINE       8454
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T7
1	1	0	Covered	T6,T17,T31
1	1	1	Covered	T5,T7,T23

 LINE       8463
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T7
1	1	0	Covered	T6,T17,T43
1	1	1	Covered	T5,T7,T23

 LINE       8488
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T7
1	1	0	Covered	T6,T17,T31
1	1	1	Covered	T5,T7,T23

 LINE       8513
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T7
1	1	0	Covered	T6,T17,T31
1	1	1	Covered	T5,T7,T23

 LINE       8538
 EXPRESSION (addr_hit[31] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T7
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       8539
 EXPRESSION (addr_hit[32] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T7
1	1	0	Covered	T6,T17,T31
1	1	1	Covered	T5,T7,T23

 LINE       8558
 EXPRESSION (addr_hit[33] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T7
1	1	0	Covered	T6,T17,T31
1	1	1	Covered	T5,T7,T23

 LINE       8571
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T7
1	1	0	Covered	T6,T31,T34
1	1	1	Covered	T5,T7,T10

 LINE       9012
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T5,T7,T10

---

Branch Coverage for Module : usbdev_reg_top

	Line No.	Total	Covered	Percent
Branches		49	49	100.00
TERNARY	7991	2	2	100.00
IF	75	3	3	100.00
TERNARY	132	2	2	100.00
IF	138	2	2	100.00
CASE	8619	37	37	100.00
CASE	9015	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	7991	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	75	if ((!rst_ni))
-2-:	77	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	132	((tl_i.a_address[(AW - 1):0] inside {[2048:4095]})) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	if (intg_err)

Branches:

-1-	Status	Tests
1	Covered	T22,T30,T43
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	8619	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T2,T4,T5
addr_hit[2]	Covered	T2,T4,T6
addr_hit[3]	Covered	T2,T4,T5
addr_hit[4]	Covered	T2,T4,T5
addr_hit[5]	Covered	T2,T4,T5
addr_hit[6]	Covered	T2,T4,T5
addr_hit[7]	Covered	T2,T4,T5
addr_hit[8]	Covered	T2,T4,T6
addr_hit[9]	Covered	T2,T4,T5
addr_hit[10]	Covered	T2,T4,T5
addr_hit[11]	Covered	T2,T4,T5
addr_hit[12]	Covered	T1,T2,T4
addr_hit[13]	Covered	T2,T4,T5
addr_hit[14]	Covered	T2,T4,T5
addr_hit[15]	Covered	T2,T4,T5
addr_hit[16]	Covered	T2,T4,T5
addr_hit[17]	Covered	T2,T4,T5
addr_hit[18]	Covered	T2,T4,T5
addr_hit[19]	Covered	T2,T4,T5
addr_hit[20]	Covered	T2,T4,T5
addr_hit[21]	Covered	T2,T4,T5
addr_hit[22]	Covered	T2,T4,T5
addr_hit[23]	Covered	T2,T4,T5
addr_hit[24]	Covered	T2,T4,T5
addr_hit[25]	Covered	T2,T4,T5
addr_hit[26]	Covered	T2,T4,T5
addr_hit[27]	Covered	T2,T4,T5
addr_hit[28]	Covered	T2,T4,T5
addr_hit[29]	Covered	T2,T4,T5
addr_hit[30]	Covered	T2,T4,T5
addr_hit[31]	Covered	T2,T4,T5
addr_hit[32]	Covered	T2,T4,T5
addr_hit[33]	Covered	T2,T4,T5
addr_hit[34]	Covered	T2,T4,T5
addr_hit[35]	Covered	T2,T4,T5
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	9015	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[34]	Covered	T2,T4,T5
addr_hit[35]	Covered	T2,T4,T5
default	Covered	T1,T2,T3

---

Assert Coverage for Module : usbdev_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	759040	66840	0	0
reAfterRv	759040	66838	0	0
rePulse	759040	46999	0	0
wePulse	759040	19839	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	759040	66840	0	0
T1	4138	3	0	0
T2	5273	3	0	0
T3	8402	3	0	0
T4	1241	22	0	0
T5	1855	346	0	0
T6	4495	87	0	0
T7	2420	165	0	0
T8	1472	22	0	0
T9	1338	22	0	0
T10	1436	36	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	759040	66838	0	0
T1	4138	3	0	0
T2	5273	3	0	0
T3	8402	3	0	0
T4	1241	22	0	0
T5	1855	346	0	0
T6	4495	87	0	0
T7	2420	165	0	0
T8	1472	22	0	0
T9	1338	22	0	0
T10	1436	36	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	759040	46999	0	0
T1	4138	2	0	0
T2	5273	2	0	0
T3	8402	2	0	0
T4	1241	11	0	0
T5	1855	283	0	0
T6	4495	11	0	0
T7	2420	132	0	0
T8	1472	11	0	0
T9	1338	11	0	0
T10	1436	28	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	759040	19839	0	0
T1	4138	1	0	0
T2	5273	1	0	0
T3	8402	1	0	0
T4	1241	11	0	0
T5	1855	63	0	0
T6	4495	76	0	0
T7	2420	33	0	0
T8	1472	11	0	0
T9	1338	11	0	0
T10	1436	8	0	0