Module Definition
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Module Instance : tb.dut.u_reg.u_wake_events_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.68 66.00 25.58 39.13 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
37.10 72.45 22.45 53.49 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
57.45 82.35 30.77 66.67 50.00 u_wake_events_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_wr_req.u_dst_update_sync 37.29 79.17 0.00 70.00 0.00



Module Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 33.33 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.88 87.50 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_wake_control_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=2,ResetVal=0,DstWrReq=0 )
Line Coverage for Module self-instances :
SCORELINE
66.67 33.33
tb.dut.u_reg.u_wake_control_cdc.u_arb

Line No.TotalCoveredPercent
TOTAL3133.33
CONT_ASSIGN100100.00
CONT_ASSIGN284100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 0 1
284 0 1
285 1 1
300 unreachable


Line Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=10,ResetVal=0,DstWrReq=1 )
Line Coverage for Module self-instances :
SCORELINE
32.68 66.00
tb.dut.u_reg.u_wake_events_cdc.u_arb

Line No.TotalCoveredPercent
TOTAL503366.00
CONT_ASSIGN10011100.00
ALWAYS11233100.00
ALWAYS1226466.67
CONT_ASSIGN13611100.00
ALWAYS1406466.67
ALWAYS15610660.00
CONT_ASSIGN18411100.00
ALWAYS188191052.63
CONT_ASSIGN22911100.00
CONT_ASSIGN24411100.00
CONT_ASSIGN24511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 1 1
112 1 1
113 1 1
115 1 1
122 1 1
123 1 1
124 1 1
129 0 1
130 1 1
133 0 1
MISSING_ELSE
136 1 1
140 1 1
141 1 1
142 1 1
143 0 1
144 1 1
145 0 1
MISSING_ELSE
156 1 1
157 1 1
158 1 1
159 0 1
160 1 1
161 0 1
162 1 1
163 0 1
164 1 1
165 0 1
MISSING_ELSE
184 1 1
188 1 1
189 1 1
193 1 1
194 1 1
196 1 1
198 1 1
200 1 1
201 1 1
203 0 1
204 0 1
205 1 1
206 0 1
207 0 1
208 1 1
211 0 1
212 0 1
MISSING_ELSE
217 0 1
218 0 1
219 0 1
==> MISSING_ELSE
229 1 1
244 1 1
245 1 1


Cond Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=2,ResetVal=0,DstWrReq=0 )
Cond Coverage for Module self-instances :
SCORECOND
66.67 100.00
tb.dut.u_reg.u_wake_control_cdc.u_arb

TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01Unreachable
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1Unreachable

Cond Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=10,ResetVal=0,DstWrReq=1 )
Cond Coverage for Module self-instances :
SCORECOND
32.68 25.58
tb.dut.u_reg.u_wake_events_cdc.u_arb

TotalCoveredPercent
Conditions431125.58
Logical431125.58
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       124
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       130
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       136
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       158
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       160
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       162
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       184
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       208
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       229
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010Not Covered
100Not Covered

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       245
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       245
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Branch Coverage for Module : prim_reg_cdc_arb
Line No.TotalCoveredPercent
Branches 23 9 39.13
IF 112 2 2 100.00
IF 122 4 2 50.00
IF 140 4 2 50.00
IF 156 6 2 33.33
CASE 198 7 1 14.29

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 112 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 122 if ((!rst_dst_ni)) -2-: 124 if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)) -3-: 130 if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 140 if ((!rst_dst_ni)) -2-: 142 if (gen_wr_req.dst_lat_d) -3-: 144 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 156 if ((!rst_dst_ni)) -2-: 158 if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)) -3-: 160 if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d)) -4-: 162 if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d)) -5-: 164 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Not Covered
0 0 1 - - Not Covered
0 0 0 1 - Not Covered
0 0 0 0 1 Not Covered
0 0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 198 case (gen_wr_req.state_q) -2-: 201 if (gen_wr_req.dst_req) -3-: 205 if (dst_update) -4-: 208 if ((dst_qs_o != dst_qs_i)) -5-: 218 if (gen_wr_req.dst_update_ack)

Branches:
-1--2--3--4--5-StatusTests
StIdle 1 - - - Not Covered
StIdle 0 1 - - Not Covered
StIdle 0 0 1 - Not Covered
StIdle 0 0 0 - Covered T1,T2,T3
StWait - - - 1 Not Covered
StWait - - - 0 Not Covered
default - - - - Not Covered


Assert Coverage for Module : prim_reg_cdc_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 0 0.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 0 0.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_wr_req.DstUpdateReqCheck_A 199608 0 0 152
gen_wr_req.HwIdSelCheck_A 199608 0 0 0


gen_wr_req.DstUpdateReqCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 199608 0 0 152

gen_wr_req.HwIdSelCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 199608 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL503366.00
CONT_ASSIGN10011100.00
ALWAYS11233100.00
ALWAYS1226466.67
CONT_ASSIGN13611100.00
ALWAYS1406466.67
ALWAYS15610660.00
CONT_ASSIGN18411100.00
ALWAYS188191052.63
CONT_ASSIGN22911100.00
CONT_ASSIGN24411100.00
CONT_ASSIGN24511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 1 1
112 1 1
113 1 1
115 1 1
122 1 1
123 1 1
124 1 1
129 0 1
130 1 1
133 0 1
MISSING_ELSE
136 1 1
140 1 1
141 1 1
142 1 1
143 0 1
144 1 1
145 0 1
MISSING_ELSE
156 1 1
157 1 1
158 1 1
159 0 1
160 1 1
161 0 1
162 1 1
163 0 1
164 1 1
165 0 1
MISSING_ELSE
184 1 1
188 1 1
189 1 1
193 1 1
194 1 1
196 1 1
198 1 1
200 1 1
201 1 1
203 0 1
204 0 1
205 1 1
206 0 1
207 0 1
208 1 1
211 0 1
212 0 1
MISSING_ELSE
217 0 1
218 0 1
219 0 1
==> MISSING_ELSE
229 1 1
244 1 1
245 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc.u_arb
TotalCoveredPercent
Conditions431125.58
Logical431125.58
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       124
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       130
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       136
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       158
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       160
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       162
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       184
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       208
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       229
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010Not Covered
100Not Covered

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       245
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       245
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Branch Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc.u_arb
Line No.TotalCoveredPercent
Branches 23 9 39.13
IF 112 2 2 100.00
IF 122 4 2 50.00
IF 140 4 2 50.00
IF 156 6 2 33.33
CASE 198 7 1 14.29

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 112 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 122 if ((!rst_dst_ni)) -2-: 124 if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)) -3-: 130 if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 140 if ((!rst_dst_ni)) -2-: 142 if (gen_wr_req.dst_lat_d) -3-: 144 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 156 if ((!rst_dst_ni)) -2-: 158 if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)) -3-: 160 if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d)) -4-: 162 if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d)) -5-: 164 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Not Covered
0 0 1 - - Not Covered
0 0 0 1 - Not Covered
0 0 0 0 1 Not Covered
0 0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 198 case (gen_wr_req.state_q) -2-: 201 if (gen_wr_req.dst_req) -3-: 205 if (dst_update) -4-: 208 if ((dst_qs_o != dst_qs_i)) -5-: 218 if (gen_wr_req.dst_update_ack)

Branches:
-1--2--3--4--5-StatusTests
StIdle 1 - - - Not Covered
StIdle 0 1 - - Not Covered
StIdle 0 0 1 - Not Covered
StIdle 0 0 0 - Covered T1,T2,T3
StWait - - - 1 Not Covered
StWait - - - 0 Not Covered
default - - - - Not Covered


Assert Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 0 0.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 0 0.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_wr_req.DstUpdateReqCheck_A 199608 0 0 152
gen_wr_req.HwIdSelCheck_A 199608 0 0 0


gen_wr_req.DstUpdateReqCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 199608 0 0 152

gen_wr_req.HwIdSelCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 199608 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL3133.33
CONT_ASSIGN100100.00
CONT_ASSIGN284100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 0 1
284 0 1
285 1 1
300 unreachable


Cond Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb
TotalCoveredPercent
Conditions11100.00
Logical11100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01Unreachable
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1Unreachable
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%