Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34916	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	40824	1		T1	7		T2	9		T3	8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	45751	1		T1	3		T2	3		T3	4
values[0x0]	14645	1		T1	4		T2	6		T3	3
values[0x1]	15344	1		T1	5		T2	3		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	23941	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	51799	1		T1	10		T2	10		T3	9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	257	1		T106	4		T107	1		T32	18
valid_sources[0x01]	211	1		T9	1		T108	1		T32	13
valid_sources[0x02]	267	1		T1	3		T106	2		T109	13
valid_sources[0x03]	321	1		T110	1		T111	2		T32	23
valid_sources[0x04]	212	1		T3	1		T32	19		T27	3
valid_sources[0x05]	198	1		T76	1		T112	1		T32	16
valid_sources[0x06]	245	1		T75	2		T29	1		T32	15
valid_sources[0x07]	431	1		T113	1		T32	26		T27	8
valid_sources[0x08]	159	1		T3	1		T32	19		T27	5
valid_sources[0x09]	248	1		T5	1		T28	1		T32	15
valid_sources[0x0a]	248	1		T114	3		T115	3		T32	20
valid_sources[0x0b]	357	1		T116	2		T117	1		T72	4
valid_sources[0x0c]	296	1		T118	1		T119	1		T32	17
valid_sources[0x0d]	338	1		T116	2		T120	13		T32	13
valid_sources[0x0e]	243	1		T11	1		T108	2		T32	7
valid_sources[0x0f]	294	1		T3	1		T108	1		T32	15
valid_sources[0x10]	222	1		T32	15		T27	5		T37	2
valid_sources[0x11]	234	1		T11	2		T121	1		T32	11
valid_sources[0x12]	265	1		T75	1		T32	13		T27	7
valid_sources[0x13]	250	1		T122	3		T32	11		T37	3
valid_sources[0x14]	259	1		T73	1		T32	11		T27	3
valid_sources[0x15]	193	1		T32	15		T27	7		T37	3
valid_sources[0x16]	234	1		T43	1		T123	1		T124	2
valid_sources[0x17]	277	1		T32	12		T27	1		T37	1
valid_sources[0x18]	257	1		T43	1		T106	1		T32	12
valid_sources[0x19]	342	1		T32	9		T27	9		T37	5
valid_sources[0x1a]	517	1		T123	1		T32	14		T27	7
valid_sources[0x1b]	205	1		T114	2		T125	4		T126	2
valid_sources[0x1c]	236	1		T43	1		T127	12		T32	20
valid_sources[0x1d]	486	1		T7	1		T76	1		T32	14
valid_sources[0x1e]	280	1		T110	2		T128	1		T126	1
valid_sources[0x1f]	272	1		T32	12		T27	5		T14	12
valid_sources[0x20]	343	1		T32	16		T27	8		T14	5
valid_sources[0x21]	230	1		T43	1		T124	3		T32	14
valid_sources[0x22]	195	1		T5	3		T6	1		T116	1
valid_sources[0x23]	297	1		T123	1		T129	3		T130	1
valid_sources[0x24]	258	1		T121	6		T32	19		T27	10
valid_sources[0x25]	337	1		T112	1		T32	15		T27	13
valid_sources[0x26]	300	1		T13	8		T117	1		T71	1
valid_sources[0x27]	279	1		T8	12		T111	1		T126	1
valid_sources[0x28]	291	1		T114	6		T125	4		T32	15
valid_sources[0x29]	217	1		T116	1		T71	2		T32	14
valid_sources[0x2a]	324	1		T131	2		T46	8		T32	21
valid_sources[0x2b]	264	1		T32	10		T27	2		T14	2
valid_sources[0x2c]	305	1		T118	1		T129	4		T32	15
valid_sources[0x2d]	359	1		T6	1		T132	1		T133	12
valid_sources[0x2e]	288	1		T13	1		T131	1		T32	13
valid_sources[0x2f]	253	1		T6	1		T134	12		T135	1
valid_sources[0x30]	359	1		T122	1		T119	1		T73	1
valid_sources[0x31]	319	1		T136	12		T32	12		T27	7
valid_sources[0x32]	285	1		T32	17		T27	5		T14	6
valid_sources[0x33]	251	1		T32	15		T27	3		T37	3
valid_sources[0x34]	251	1		T137	1		T32	15		T27	8
valid_sources[0x35]	211	1		T9	2		T11	2		T107	1
valid_sources[0x36]	209	1		T125	3		T32	13		T27	7
valid_sources[0x37]	315	1		T13	1		T107	1		T138	1
valid_sources[0x38]	225	1		T11	1		T73	1		T32	21
valid_sources[0x39]	416	1		T123	1		T32	20		T27	12
valid_sources[0x3a]	457	1		T139	2		T138	3		T32	18
valid_sources[0x3b]	355	1		T3	1		T140	1		T32	15
valid_sources[0x3c]	229	1		T1	1		T75	1		T141	2
valid_sources[0x3d]	293	1		T112	1		T32	18		T27	2
valid_sources[0x3e]	256	1		T76	1		T130	1		T32	16
valid_sources[0x3f]	333	1		T128	1		T130	1		T73	1
valid_sources[0x40]	287	1		T119	1		T32	14		T27	11
valid_sources[0x41]	242	1		T108	1		T32	12		T27	6
valid_sources[0x42]	383	1		T32	13		T27	8		T14	5
valid_sources[0x43]	228	1		T76	1		T142	13		T32	13
valid_sources[0x44]	1785	1		T108	2		T132	1		T32	19
valid_sources[0x45]	457	1		T128	1		T32	18		T27	2
valid_sources[0x46]	269	1		T7	1		T29	1		T32	14
valid_sources[0x47]	315	1		T143	12		T32	17		T27	6
valid_sources[0x48]	293	1		T3	1		T32	16		T27	1
valid_sources[0x49]	206	1		T11	1		T129	1		T112	1
valid_sources[0x4a]	260	1		T73	1		T32	14		T27	2
valid_sources[0x4b]	268	1		T32	16		T27	4		T37	1
valid_sources[0x4c]	344	1		T122	5		T144	3		T145	13
valid_sources[0x4d]	227	1		T118	1		T130	1		T113	1
valid_sources[0x4e]	417	1		T118	1		T144	8		T132	1
valid_sources[0x4f]	282	1		T32	12		T27	5		T37	4
valid_sources[0x50]	270	1		T118	2		T75	1		T117	2
valid_sources[0x51]	281	1		T49	13		T146	12		T137	1
valid_sources[0x52]	315	1		T5	2		T131	2		T128	1
valid_sources[0x53]	332	1		T137	1		T32	22		T27	9
valid_sources[0x54]	227	1		T123	1		T119	1		T32	12
valid_sources[0x55]	375	1		T32	15		T27	6		T37	1
valid_sources[0x56]	416	1		T6	1		T138	2		T32	20
valid_sources[0x57]	229	1		T111	1		T32	13		T27	5
valid_sources[0x58]	217	1		T43	1		T75	1		T110	1
valid_sources[0x59]	291	1		T139	1		T147	12		T32	14
valid_sources[0x5a]	263	1		T44	1		T124	1		T32	28
valid_sources[0x5b]	353	1		T128	1		T32	18		T27	11
valid_sources[0x5c]	336	1		T118	1		T32	11		T27	18
valid_sources[0x5d]	238	1		T3	1		T113	1		T32	16
valid_sources[0x5e]	252	1		T1	3		T123	1		T128	1
valid_sources[0x5f]	245	1		T110	1		T108	1		T32	15
valid_sources[0x60]	295	1		T118	1		T32	14		T27	1
valid_sources[0x61]	220	1		T43	1		T32	9		T27	3
valid_sources[0x62]	256	1		T128	1		T138	1		T32	14
valid_sources[0x63]	278	1		T76	1		T32	15		T27	5
valid_sources[0x64]	362	1		T135	5		T138	1		T32	23
valid_sources[0x65]	291	1		T32	18		T27	4		T37	2
valid_sources[0x66]	258	1		T6	1		T111	3		T112	1
valid_sources[0x67]	243	1		T111	1		T32	11		T27	1
valid_sources[0x68]	348	1		T139	1		T71	1		T32	17
valid_sources[0x69]	234	1		T43	1		T76	1		T138	1
valid_sources[0x6a]	248	1		T124	1		T32	7		T27	3
valid_sources[0x6b]	170	1		T111	1		T32	14		T27	2
valid_sources[0x6c]	197	1		T42	12		T32	14		T27	11
valid_sources[0x6d]	552	1		T148	12		T130	1		T32	12
valid_sources[0x6e]	195	1		T6	1		T128	1		T137	2
valid_sources[0x6f]	198	1		T6	1		T32	15		T27	8
valid_sources[0x70]	242	1		T32	11		T27	2		T37	1
valid_sources[0x71]	267	1		T32	16		T27	15		T37	4
valid_sources[0x72]	254	1		T32	15		T27	4		T37	1
valid_sources[0x73]	329	1		T6	1		T32	16		T27	2
valid_sources[0x74]	338	1		T112	1		T138	1		T32	13
valid_sources[0x75]	564	1		T117	2		T32	11		T27	8
valid_sources[0x76]	271	1		T7	1		T10	2		T137	1
valid_sources[0x77]	272	1		T149	2		T73	1		T32	17
valid_sources[0x78]	229	1		T75	1		T106	3		T73	1
valid_sources[0x79]	210	1		T32	15		T37	3		T14	7
valid_sources[0x7a]	307	1		T128	2		T32	24		T27	4
valid_sources[0x7b]	297	1		T32	14		T27	11		T14	5
valid_sources[0x7c]	220	1		T116	1		T150	13		T32	7
valid_sources[0x7d]	220	1		T121	4		T123	1		T108	1
valid_sources[0x7e]	221	1		T73	1		T32	19		T27	13
valid_sources[0x7f]	305	1		T43	1		T130	1		T137	1
valid_sources[0x80]	242	1		T44	3		T32	18		T27	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

15041

1

T1

2

T2

3

T3

3

values[0x0]

all_enables

biggest_size

13364

1

T1

3

T2

4

T3

2

values[0x1]

all_enables

biggest_size

12419

1

T1

2

T2

2

T3

3