SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[usbdev_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 70694 | 1 | T1 | 12 | T2 | 12 | T3 | 13 | |||
auto[1] | 18375 | 1 | T27 | 7 | T14 | 1535 | T15 | 1535 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 88951 | 1 | T1 | 12 | T2 | 12 | T3 | 13 | |||
values[1] | 9 | 1 | T27 | 1 | T48 | 1 | T50 | 1 | |||
values[2] | 1 | 1 | T59 | 1 | - | - | - | - | |||
values[3] | 64 | 1 | T27 | 3 | T25 | 4 | T48 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 88957 | 1 | T1 | 12 | T2 | 12 | T3 | 13 | |||
values[1] | 6 | 1 | T57 | 1 | T59 | 1 | T105 | 1 | |||
values[2] | 5 | 1 | T27 | 1 | T48 | 1 | T57 | 1 | |||
values[3] | 54 | 1 | T27 | 7 | T25 | 4 | T48 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 88899 | 1 | T1 | 12 | T2 | 12 | T3 | 13 | |||
auto[TlIntgErrCmd] | 58 | 1 | T27 | 2 | T25 | 3 | T48 | 2 | |||
auto[TlIntgErrData] | 52 | 1 | T27 | 4 | T25 | 3 | T48 | 3 | |||
auto[TlIntgErrBoth] | 60 | 1 | T27 | 4 | T25 | 4 | T48 | 5 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |