Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	47379	1		T1	5		T2	3		T3	5
full_word	41690	1		T1	7		T2	9		T3	8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	88899	1		T1	12		T2	12		T3	13
auto[TlIntgErrCmd]	58	1		T27	2		T25	3		T48	2
auto[TlIntgErrData]	52	1		T27	4		T25	3		T48	3
auto[TlIntgErrBoth]	60	1		T27	4		T25	4		T48	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	47363	1		T1	3		T2	3		T3	4
auto[1]	41706	1		T1	9		T2	9		T3	9

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	32087	1		T1	1		T3	1		T4	2
auto[TlIntgErrNone]	partial	auto[1]	15142	1		T1	4		T2	3		T3	4
auto[TlIntgErrNone]	full_word	auto[0]	15197	1		T1	2		T2	3		T3	3
auto[TlIntgErrNone]	full_word	auto[1]	26473	1		T1	5		T2	6		T3	5
auto[TlIntgErrCmd]	partial	auto[0]	27	1		T27	1		T57	3		T50	3
auto[TlIntgErrCmd]	partial	auto[1]	24	1		T27	1		T25	3		T48	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T58	2		T87	1		T88	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T48	1		T89	1		-	-
auto[TlIntgErrData]	partial	auto[0]	22	1		T27	2		T25	1		T57	4
auto[TlIntgErrData]	partial	auto[1]	21	1		T27	1		T25	2		T48	1
auto[TlIntgErrData]	full_word	auto[0]	3	1		T90	2		T88	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	6	1		T27	1		T48	2		T57	1
auto[TlIntgErrBoth]	partial	auto[0]	22	1		T27	3		T25	1		T48	3
auto[TlIntgErrBoth]	partial	auto[1]	34	1		T27	1		T25	3		T48	2
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T57	1		T58	1		T91	1