Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.gen_no_stubbed_memory.u_memory_1p.u_mem.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.37 71.43 66.67 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.37 71.43 66.67 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_mem


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_generic_ram_1p
Line No.TotalCoveredPercent
TOTAL7571.43
CONT_ASSIGN42100.00
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
ALWAYS636583.33
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 0 1
52 unreachable
63 1 1
64 1 1
65 1 1
66 1 1
67 1 1
==> MISSING_ELSE
72 0 1
MISSING_ELSE


Branch Coverage for Module : prim_generic_ram_1p
Line No.TotalCoveredPercent
Branches 3 2 66.67
IF 63 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Not Covered
0 - Covered T1,T2,T3


Assert Coverage for Module : prim_generic_ram_1p
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataBitsPerMaskCheck_A 88 88 0 0
gen_wmask[0].MaskCheck_A 34228874 489 0 0
gen_wmask[1].MaskCheck_A 34228874 489 0 0
gen_wmask[2].MaskCheck_A 34228874 489 0 0
gen_wmask[3].MaskCheck_A 34228874 489 0 0


DataBitsPerMaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 88 88 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

gen_wmask[0].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 489 0 0
T1 402267 3 0 0
T2 401984 3 0 0
T3 403505 7 0 0
T4 401643 3 0 0
T5 403130 13 0 0
T6 401942 5 0 0
T7 4637 0 0 0
T8 401806 3 0 0
T9 401519 3 0 0
T10 401645 3 0 0
T13 0 3 0 0

gen_wmask[1].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 489 0 0
T1 402267 3 0 0
T2 401984 3 0 0
T3 403505 7 0 0
T4 401643 3 0 0
T5 403130 13 0 0
T6 401942 5 0 0
T7 4637 0 0 0
T8 401806 3 0 0
T9 401519 3 0 0
T10 401645 3 0 0
T13 0 3 0 0

gen_wmask[2].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 489 0 0
T1 402267 3 0 0
T2 401984 3 0 0
T3 403505 7 0 0
T4 401643 3 0 0
T5 403130 13 0 0
T6 401942 5 0 0
T7 4637 0 0 0
T8 401806 3 0 0
T9 401519 3 0 0
T10 401645 3 0 0
T13 0 3 0 0

gen_wmask[3].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 489 0 0
T1 402267 3 0 0
T2 401984 3 0 0
T3 403505 7 0 0
T4 401643 3 0 0
T5 403130 13 0 0
T6 401942 5 0 0
T7 4637 0 0 0
T8 401806 3 0 0
T9 401519 3 0 0
T10 401645 3 0 0
T13 0 3 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%