Line Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Module :
prim_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T32,T27,T37 |
1 | 0 | Covered | T32,T27,T37 |
1 | 1 | Covered | T32,T37,T33 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T32,T27,T37 |
1 | 0 | Covered | T32,T37,T33 |
1 | 1 | Covered | T32,T27,T37 |
Branch Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_pulse_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
54369568 |
894 |
0 |
0 |
T17 |
2776 |
4 |
0 |
0 |
T20 |
21425 |
0 |
0 |
0 |
T25 |
10276 |
20 |
0 |
0 |
T26 |
2384 |
2 |
0 |
0 |
T27 |
9241 |
20 |
0 |
0 |
T32 |
15112 |
124 |
0 |
0 |
T33 |
5962 |
4 |
0 |
0 |
T34 |
4186 |
4 |
0 |
0 |
T37 |
4888 |
4 |
0 |
0 |
T47 |
7041 |
2 |
0 |
0 |
T48 |
0 |
20 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
79472279 |
898 |
0 |
0 |
T17 |
2776 |
4 |
0 |
0 |
T19 |
5621 |
1 |
0 |
0 |
T20 |
6733 |
0 |
0 |
0 |
T25 |
10276 |
20 |
0 |
0 |
T26 |
2384 |
2 |
0 |
0 |
T27 |
9241 |
20 |
0 |
0 |
T32 |
15112 |
124 |
0 |
0 |
T33 |
5962 |
4 |
0 |
0 |
T34 |
4186 |
4 |
0 |
0 |
T37 |
4888 |
4 |
0 |
0 |
T47 |
7041 |
2 |
0 |
0 |
T48 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 6 | 2 | 33.33 |
Logical | 6 | 2 | 33.33 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Not Covered | |
1 | 1 | Unreachable | |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9755619 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34858330 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T32,T27,T37 |
1 | 0 | Covered | T32,T27,T37 |
1 | 1 | Covered | T32,T37,T33 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T32,T27,T37 |
1 | 0 | Covered | T32,T37,T33 |
1 | 1 | Covered | T32,T27,T37 |
Branch Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9755619 |
447 |
0 |
0 |
T17 |
554 |
2 |
0 |
0 |
T20 |
6733 |
0 |
0 |
0 |
T25 |
2055 |
10 |
0 |
0 |
T26 |
182 |
1 |
0 |
0 |
T27 |
2309 |
10 |
0 |
0 |
T32 |
603 |
62 |
0 |
0 |
T33 |
120 |
2 |
0 |
0 |
T34 |
1355 |
2 |
0 |
0 |
T37 |
1487 |
2 |
0 |
0 |
T47 |
143 |
1 |
0 |
0 |
T48 |
0 |
10 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34858330 |
450 |
0 |
0 |
T17 |
2222 |
2 |
0 |
0 |
T19 |
5621 |
1 |
0 |
0 |
T25 |
8221 |
10 |
0 |
0 |
T26 |
2202 |
1 |
0 |
0 |
T27 |
6932 |
10 |
0 |
0 |
T32 |
14509 |
62 |
0 |
0 |
T33 |
5842 |
2 |
0 |
0 |
T34 |
2831 |
2 |
0 |
0 |
T37 |
3401 |
2 |
0 |
0 |
T47 |
6898 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T32,T27,T37 |
1 | 0 | Covered | T32,T27,T37 |
1 | 1 | Covered | T32,T37,T33 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T32,T27,T37 |
1 | 0 | Covered | T32,T37,T33 |
1 | 1 | Covered | T32,T27,T37 |
Branch Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34858330 |
447 |
0 |
0 |
T17 |
2222 |
2 |
0 |
0 |
T20 |
14692 |
0 |
0 |
0 |
T25 |
8221 |
10 |
0 |
0 |
T26 |
2202 |
1 |
0 |
0 |
T27 |
6932 |
10 |
0 |
0 |
T32 |
14509 |
62 |
0 |
0 |
T33 |
5842 |
2 |
0 |
0 |
T34 |
2831 |
2 |
0 |
0 |
T37 |
3401 |
2 |
0 |
0 |
T47 |
6898 |
1 |
0 |
0 |
T48 |
0 |
10 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9755619 |
448 |
0 |
0 |
T17 |
554 |
2 |
0 |
0 |
T20 |
6733 |
0 |
0 |
0 |
T25 |
2055 |
10 |
0 |
0 |
T26 |
182 |
1 |
0 |
0 |
T27 |
2309 |
10 |
0 |
0 |
T32 |
603 |
62 |
0 |
0 |
T33 |
120 |
2 |
0 |
0 |
T34 |
1355 |
2 |
0 |
0 |
T37 |
1487 |
2 |
0 |
0 |
T47 |
143 |
1 |
0 |
0 |
T48 |
0 |
10 |
0 |
0 |