Unified Coverage Report :: Module Instance :: tb.dut.usbdev_avfifo

Module Instance : tb.dut.usbdev_avfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	100.00	58.33			75.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.08	95.00	58.33			75.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.35	90.70	57.14	93.90		75.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00

Module Instance : tb.dut.usbdev_rxfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.38	100.00	61.54			80.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.58	95.00	61.54			77.78	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.35	90.70	57.14	93.90		75.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.77	100.00	73.08			90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.85	95.00	73.08			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.38	95.38	70.80			83.33	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00

Line Coverage for Instance : tb.dut.usbdev_avfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	182	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
182	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avfifo

	Total	Covered	Percent
Conditions	24	14	58.33
Logical	24	14	58.33
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.usbdev_avfifo

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
TERNARY	88	3	1	33.33
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	50722704	50464338	0	0
DepthKnown_A	50722704	50687057	0	0
RvalidKnown_A	50722704	50687057	0	0
WreadyKnown_A	50722704	50687057	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	50722704	50464338	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50464338	0	0
T1	401813	400733	0	0
T2	401865	400692	0	0
T3	401831	400673	0	0
T4	401855	401002	0	0
T5	401821	401002	0	0
T6	401892	401061	0	0
T7	401795	400765	0	0
T8	401784	400680	0	0
T9	401890	400941	0	0
T10	401706	400888	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50464338	0	0
T1	401813	400733	0	0
T2	401865	400692	0	0
T3	401831	400673	0	0
T4	401855	401002	0	0
T5	401821	401002	0	0
T6	401892	401061	0	0
T7	401795	400765	0	0
T8	401784	400680	0	0
T9	401890	400941	0	0
T10	401706	400888	0	0

Line Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Covered	Percent
Conditions	26	16	61.54
Logical	26	16	61.54
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
Branches		10	8	80.00
TERNARY	88	3	1	33.33
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	50722704	14125	0	0
DepthKnown_A	50722704	50687057	0	0
RvalidKnown_A	50722704	50687057	0	0
WreadyKnown_A	50722704	50687057	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	50722704	14125	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	14125	0	0
T1	401813	116	0	0
T2	401865	116	0	0
T3	401831	115	0	0
T4	401855	109	0	0
T5	401821	109	0	0
T6	401892	109	0	0
T7	401795	109	0	0
T8	401784	119	0	0
T9	401890	119	0	0
T10	401706	109	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	14125	0	0
T1	401813	116	0	0
T2	401865	116	0	0
T3	401831	115	0	0
T4	401855	109	0	0
T5	401821	109	0	0
T6	401892	109	0	0
T7	401795	109	0	0
T8	401784	119	0	0
T9	401890	119	0	0
T10	401706	109	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	51341712	153603	0	0
DepthKnown_A	51341712	51281711	0	0
RvalidKnown_A	51341712	51281711	0	0
WreadyKnown_A	51341712	51281711	0	0
gen_passthru_fifo.paramCheckPass	269	269	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51341712	153603	0	0
T1	401813	12	0	0
T2	401865	12	0	0
T3	401831	12	0	0
T4	401855	12	0	0
T5	401821	12	0	0
T6	401892	12	0	0
T7	401795	12	0	0
T8	401784	12	0	0
T9	401890	12	0	0
T10	401706	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51341712	51281711	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51341712	51281711	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51341712	51281711	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	269	269	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	51341712	139567	0	0
DepthKnown_A	51341712	51281711	0	0
RvalidKnown_A	51341712	51281711	0	0
WreadyKnown_A	51341712	51281711	0	0
gen_passthru_fifo.paramCheckPass	269	269	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51341712	139567	0	0
T1	401813	44	0	0
T2	401865	12	0	0
T3	401831	29	0	0
T4	401855	12	0	0
T5	401821	12	0	0
T6	401892	12	0	0
T7	401795	12	0	0
T8	401784	50	0	0
T9	401890	41	0	0
T10	401706	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51341712	51281711	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51341712	51281711	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51341712	51281711	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	269	269	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	51341712	27933	0	0
DepthKnown_A	51341712	51281711	0	0
RvalidKnown_A	51341712	51281711	0	0
WreadyKnown_A	51341712	51281711	0	0
gen_passthru_fifo.paramCheckPass	269	269	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51341712	27933	0	0
T1	401813	2	0	0
T2	401865	2	0	0
T3	401831	2	0	0
T4	401855	0	0	0
T5	401821	0	0	0
T6	401892	0	0	0
T7	401795	2	0	0
T8	401784	2	0	0
T9	401890	2	0	0
T10	401706	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51341712	51281711	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51341712	51281711	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51341712	51281711	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	269	269	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	51341712	28548	0	0
DepthKnown_A	51341712	51281711	0	0
RvalidKnown_A	51341712	51281711	0	0
WreadyKnown_A	51341712	51281711	0	0
gen_passthru_fifo.paramCheckPass	269	269	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51341712	28548	0	0
T1	401813	6	0	0
T2	401865	2	0	0
T3	401831	3	0	0
T4	401855	0	0	0
T5	401821	0	0	0
T6	401892	0	0	0
T7	401795	2	0	0
T8	401784	5	0	0
T9	401890	8	0	0
T10	401706	2	0	0
T39	0	2	0	0
T40	0	7	0	0
T41	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51341712	51281711	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51341712	51281711	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51341712	51281711	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	269	269	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	51341712	119331	0	0
DepthKnown_A	51341712	51281711	0	0
RvalidKnown_A	51341712	51281711	0	0
WreadyKnown_A	51341712	51281711	0	0
gen_passthru_fifo.paramCheckPass	269	269	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51341712	119331	0	0
T1	401813	10	0	0
T2	401865	10	0	0
T3	401831	10	0	0
T4	401855	12	0	0
T5	401821	12	0	0
T6	401892	12	0	0
T7	401795	10	0	0
T8	401784	10	0	0
T9	401890	10	0	0
T10	401706	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51341712	51281711	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51341712	51281711	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51341712	51281711	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	269	269	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	51341712	111019	0	0
DepthKnown_A	51341712	51281711	0	0
RvalidKnown_A	51341712	51281711	0	0
WreadyKnown_A	51341712	51281711	0	0
gen_passthru_fifo.paramCheckPass	269	269	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51341712	111019	0	0
T1	401813	38	0	0
T2	401865	10	0	0
T3	401831	26	0	0
T4	401855	12	0	0
T5	401821	12	0	0
T6	401892	12	0	0
T7	401795	10	0	0
T8	401784	45	0	0
T9	401890	33	0	0
T10	401706	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51341712	51281711	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51341712	51281711	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51341712	51281711	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	269	269	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
ALWAYS	157	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
154	1	1
157	1	1
158	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	26	19	73.08
Logical	26	19	73.08
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	88	3	2	66.67
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	50722704	175	0	0
DepthKnown_A	50722704	50687057	0	0
RvalidKnown_A	50722704	50687057	0	0
WreadyKnown_A	50722704	50687057	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	50722704	175	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	175	0	0
T1	401813	6	0	0
T2	401865	2	0	0
T3	401831	3	0	0
T4	401855	0	0	0
T5	401821	0	0	0
T6	401892	0	0	0
T7	401795	2	0	0
T8	401784	5	0	0
T9	401890	8	0	0
T10	401706	2	0	0
T39	0	2	0	0
T40	0	7	0	0
T41	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	50687057	0	0
T1	401813	401545	0	0
T2	401865	401654	0	0
T3	401831	401612	0	0
T4	401855	401569	0	0
T5	401821	401570	0	0
T6	401892	401662	0	0
T7	401795	401563	0	0
T8	401784	401554	0	0
T9	401890	401646	0	0
T10	401706	401520	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	50722704	175	0	0
T1	401813	6	0	0
T2	401865	2	0	0
T3	401831	3	0	0
T4	401855	0	0	0
T5	401821	0	0	0
T6	401892	0	0	0
T7	401795	2	0	0
T8	401784	5	0	0
T9	401890	8	0	0
T10	401706	2	0	0
T39	0	2	0	0
T40	0	7	0	0
T41	0	7	0	0