Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : usbdev_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.60 99.72 98.69 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg 99.60 99.72 98.69 100.00 100.00



Module Instance : tb.dut.u_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.60 99.72 98.69 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.45 98.09 93.71 100.00 98.34 87.10


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.35 90.70 57.14 93.90 75.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_alert_test 100.00 100.00
u_avbuffer 100.00 100.00 100.00 100.00
u_avbuffer0_qe 100.00 100.00 100.00
u_chk 100.00 100.00 100.00 100.00
u_configin_0_buffer_0 100.00 100.00 100.00 100.00
u_configin_0_pend_0 94.44 100.00 83.33 100.00
u_configin_0_rdy_0 100.00 100.00 100.00 100.00
u_configin_0_size_0 100.00 100.00 100.00 100.00
u_configin_10_buffer_10 100.00 100.00 100.00 100.00
u_configin_10_pend_10 94.44 100.00 83.33 100.00
u_configin_10_rdy_10 100.00 100.00 100.00 100.00
u_configin_10_size_10 100.00 100.00 100.00 100.00
u_configin_11_buffer_11 100.00 100.00 100.00 100.00
u_configin_11_pend_11 94.44 100.00 83.33 100.00
u_configin_11_rdy_11 100.00 100.00 100.00 100.00
u_configin_11_size_11 100.00 100.00 100.00 100.00
u_configin_1_buffer_1 100.00 100.00 100.00 100.00
u_configin_1_pend_1 94.44 100.00 83.33 100.00
u_configin_1_rdy_1 100.00 100.00 100.00 100.00
u_configin_1_size_1 100.00 100.00 100.00 100.00
u_configin_2_buffer_2 100.00 100.00 100.00 100.00
u_configin_2_pend_2 94.44 100.00 83.33 100.00
u_configin_2_rdy_2 100.00 100.00 100.00 100.00
u_configin_2_size_2 100.00 100.00 100.00 100.00
u_configin_3_buffer_3 100.00 100.00 100.00 100.00
u_configin_3_pend_3 94.44 100.00 83.33 100.00
u_configin_3_rdy_3 100.00 100.00 100.00 100.00
u_configin_3_size_3 100.00 100.00 100.00 100.00
u_configin_4_buffer_4 100.00 100.00 100.00 100.00
u_configin_4_pend_4 94.44 100.00 83.33 100.00
u_configin_4_rdy_4 100.00 100.00 100.00 100.00
u_configin_4_size_4 100.00 100.00 100.00 100.00
u_configin_5_buffer_5 100.00 100.00 100.00 100.00
u_configin_5_pend_5 94.44 100.00 83.33 100.00
u_configin_5_rdy_5 100.00 100.00 100.00 100.00
u_configin_5_size_5 100.00 100.00 100.00 100.00
u_configin_6_buffer_6 100.00 100.00 100.00 100.00
u_configin_6_pend_6 94.44 100.00 83.33 100.00
u_configin_6_rdy_6 100.00 100.00 100.00 100.00
u_configin_6_size_6 100.00 100.00 100.00 100.00
u_configin_7_buffer_7 100.00 100.00 100.00 100.00
u_configin_7_pend_7 94.44 100.00 83.33 100.00
u_configin_7_rdy_7 100.00 100.00 100.00 100.00
u_configin_7_size_7 100.00 100.00 100.00 100.00
u_configin_8_buffer_8 100.00 100.00 100.00 100.00
u_configin_8_pend_8 94.44 100.00 83.33 100.00
u_configin_8_rdy_8 100.00 100.00 100.00 100.00
u_configin_8_size_8 100.00 100.00 100.00 100.00
u_configin_9_buffer_9 100.00 100.00 100.00 100.00
u_configin_9_pend_9 94.44 100.00 83.33 100.00
u_configin_9_rdy_9 100.00 100.00 100.00 100.00
u_configin_9_size_9 100.00 100.00 100.00 100.00
u_data_toggle_clear0_qe 100.00 100.00 100.00
u_data_toggle_clear_clear_0 100.00 100.00 100.00 100.00
u_data_toggle_clear_clear_1 100.00 100.00 100.00 100.00
u_data_toggle_clear_clear_10 100.00 100.00 100.00 100.00
u_data_toggle_clear_clear_11 100.00 100.00 100.00 100.00
u_data_toggle_clear_clear_2 100.00 100.00 100.00 100.00
u_data_toggle_clear_clear_3 100.00 100.00 100.00 100.00
u_data_toggle_clear_clear_4 100.00 100.00 100.00 100.00
u_data_toggle_clear_clear_5 100.00 100.00 100.00 100.00
u_data_toggle_clear_clear_6 100.00 100.00 100.00 100.00
u_data_toggle_clear_clear_7 100.00 100.00 100.00 100.00
u_data_toggle_clear_clear_8 100.00 100.00 100.00 100.00
u_data_toggle_clear_clear_9 100.00 100.00 100.00 100.00
u_ep_in_enable_enable_0 100.00 100.00 100.00 100.00
u_ep_in_enable_enable_1 100.00 100.00 100.00 100.00
u_ep_in_enable_enable_10 100.00 100.00 100.00 100.00
u_ep_in_enable_enable_11 100.00 100.00 100.00 100.00
u_ep_in_enable_enable_2 100.00 100.00 100.00 100.00
u_ep_in_enable_enable_3 100.00 100.00 100.00 100.00
u_ep_in_enable_enable_4 100.00 100.00 100.00 100.00
u_ep_in_enable_enable_5 100.00 100.00 100.00 100.00
u_ep_in_enable_enable_6 100.00 100.00 100.00 100.00
u_ep_in_enable_enable_7 100.00 100.00 100.00 100.00
u_ep_in_enable_enable_8 100.00 100.00 100.00 100.00
u_ep_in_enable_enable_9 100.00 100.00 100.00 100.00
u_ep_out_enable_enable_0 100.00 100.00 100.00 100.00
u_ep_out_enable_enable_1 100.00 100.00 100.00 100.00
u_ep_out_enable_enable_10 100.00 100.00 100.00 100.00
u_ep_out_enable_enable_11 100.00 100.00 100.00 100.00
u_ep_out_enable_enable_2 100.00 100.00 100.00 100.00
u_ep_out_enable_enable_3 100.00 100.00 100.00 100.00
u_ep_out_enable_enable_4 100.00 100.00 100.00 100.00
u_ep_out_enable_enable_5 100.00 100.00 100.00 100.00
u_ep_out_enable_enable_6 100.00 100.00 100.00 100.00
u_ep_out_enable_enable_7 100.00 100.00 100.00 100.00
u_ep_out_enable_enable_8 100.00 100.00 100.00 100.00
u_ep_out_enable_enable_9 100.00 100.00 100.00 100.00
u_in_iso_iso_0 100.00 100.00 100.00 100.00
u_in_iso_iso_1 100.00 100.00 100.00 100.00
u_in_iso_iso_10 100.00 100.00 100.00 100.00
u_in_iso_iso_11 100.00 100.00 100.00 100.00
u_in_iso_iso_2 100.00 100.00 100.00 100.00
u_in_iso_iso_3 100.00 100.00 100.00 100.00
u_in_iso_iso_4 100.00 100.00 100.00 100.00
u_in_iso_iso_5 100.00 100.00 100.00 100.00
u_in_iso_iso_6 100.00 100.00 100.00 100.00
u_in_iso_iso_7 100.00 100.00 100.00 100.00
u_in_iso_iso_8 100.00 100.00 100.00 100.00
u_in_iso_iso_9 100.00 100.00 100.00 100.00
u_in_sent_sent_0 88.89 100.00 66.67 100.00
u_in_sent_sent_1 88.89 100.00 66.67 100.00
u_in_sent_sent_10 88.89 100.00 66.67 100.00
u_in_sent_sent_11 88.89 100.00 66.67 100.00
u_in_sent_sent_2 88.89 100.00 66.67 100.00
u_in_sent_sent_3 88.89 100.00 66.67 100.00
u_in_sent_sent_4 88.89 100.00 66.67 100.00
u_in_sent_sent_5 88.89 100.00 66.67 100.00
u_in_sent_sent_6 88.89 100.00 66.67 100.00
u_in_sent_sent_7 88.89 100.00 66.67 100.00
u_in_sent_sent_8 88.89 100.00 66.67 100.00
u_in_sent_sent_9 88.89 100.00 66.67 100.00
u_in_stall_endpoint_0 100.00 100.00 100.00 100.00
u_in_stall_endpoint_1 96.30 100.00 88.89 100.00
u_in_stall_endpoint_10 96.30 100.00 88.89 100.00
u_in_stall_endpoint_11 96.30 100.00 88.89 100.00
u_in_stall_endpoint_2 96.30 100.00 88.89 100.00
u_in_stall_endpoint_3 96.30 100.00 88.89 100.00
u_in_stall_endpoint_4 96.30 100.00 88.89 100.00
u_in_stall_endpoint_5 96.30 100.00 88.89 100.00
u_in_stall_endpoint_6 96.30 100.00 88.89 100.00
u_in_stall_endpoint_7 96.30 100.00 88.89 100.00
u_in_stall_endpoint_8 96.30 100.00 88.89 100.00
u_in_stall_endpoint_9 96.30 100.00 88.89 100.00
u_intr_enable_av_empty 100.00 100.00 100.00 100.00
u_intr_enable_av_overflow 100.00 100.00 100.00 100.00
u_intr_enable_disconnected 100.00 100.00 100.00 100.00
u_intr_enable_frame 100.00 100.00 100.00 100.00
u_intr_enable_host_lost 100.00 100.00 100.00 100.00
u_intr_enable_link_in_err 100.00 100.00 100.00 100.00
u_intr_enable_link_out_err 100.00 100.00 100.00 100.00
u_intr_enable_link_reset 100.00 100.00 100.00 100.00
u_intr_enable_link_resume 100.00 100.00 100.00 100.00
u_intr_enable_link_suspend 100.00 100.00 100.00 100.00
u_intr_enable_pkt_received 100.00 100.00 100.00 100.00
u_intr_enable_pkt_sent 100.00 100.00 100.00 100.00
u_intr_enable_powered 100.00 100.00 100.00 100.00
u_intr_enable_rx_bitstuff_err 100.00 100.00 100.00 100.00
u_intr_enable_rx_crc_err 100.00 100.00 100.00 100.00
u_intr_enable_rx_full 100.00 100.00 100.00 100.00
u_intr_enable_rx_pid_err 100.00 100.00 100.00 100.00
u_intr_state_av_empty 100.00 100.00 100.00 100.00
u_intr_state_av_overflow 100.00 100.00 100.00 100.00
u_intr_state_disconnected 100.00 100.00 100.00 100.00
u_intr_state_frame 100.00 100.00 100.00 100.00
u_intr_state_host_lost 100.00 100.00 100.00 100.00
u_intr_state_link_in_err 100.00 100.00 100.00 100.00
u_intr_state_link_out_err 100.00 100.00 100.00 100.00
u_intr_state_link_reset 100.00 100.00 100.00 100.00
u_intr_state_link_resume 100.00 100.00 100.00 100.00
u_intr_state_link_suspend 100.00 100.00 100.00 100.00
u_intr_state_pkt_received 100.00 100.00 100.00 100.00
u_intr_state_pkt_sent 100.00 100.00 100.00 100.00
u_intr_state_powered 100.00 100.00 100.00 100.00
u_intr_state_rx_bitstuff_err 100.00 100.00 100.00 100.00
u_intr_state_rx_crc_err 100.00 100.00 100.00 100.00
u_intr_state_rx_full 100.00 100.00 100.00 100.00
u_intr_state_rx_pid_err 100.00 100.00 100.00 100.00
u_intr_test_av_empty 100.00 100.00
u_intr_test_av_overflow 100.00 100.00
u_intr_test_disconnected 100.00 100.00
u_intr_test_frame 100.00 100.00
u_intr_test_host_lost 100.00 100.00
u_intr_test_link_in_err 100.00 100.00
u_intr_test_link_out_err 100.00 100.00
u_intr_test_link_reset 100.00 100.00
u_intr_test_link_resume 100.00 100.00
u_intr_test_link_suspend 100.00 100.00
u_intr_test_pkt_received 100.00 100.00
u_intr_test_pkt_sent 100.00 100.00
u_intr_test_powered 100.00 100.00
u_intr_test_rx_bitstuff_err 100.00 100.00
u_intr_test_rx_crc_err 100.00 100.00
u_intr_test_rx_full 100.00 100.00
u_intr_test_rx_pid_err 100.00 100.00
u_out_iso_iso_0 100.00 100.00 100.00 100.00
u_out_iso_iso_1 100.00 100.00 100.00 100.00
u_out_iso_iso_10 100.00 100.00 100.00 100.00
u_out_iso_iso_11 100.00 100.00 100.00 100.00
u_out_iso_iso_2 100.00 100.00 100.00 100.00
u_out_iso_iso_3 100.00 100.00 100.00 100.00
u_out_iso_iso_4 100.00 100.00 100.00 100.00
u_out_iso_iso_5 100.00 100.00 100.00 100.00
u_out_iso_iso_6 100.00 100.00 100.00 100.00
u_out_iso_iso_7 100.00 100.00 100.00 100.00
u_out_iso_iso_8 100.00 100.00 100.00 100.00
u_out_iso_iso_9 100.00 100.00 100.00 100.00
u_out_stall_endpoint_0 100.00 100.00 100.00 100.00
u_out_stall_endpoint_1 96.30 100.00 88.89 100.00
u_out_stall_endpoint_10 96.30 100.00 88.89 100.00
u_out_stall_endpoint_11 96.30 100.00 88.89 100.00
u_out_stall_endpoint_2 96.30 100.00 88.89 100.00
u_out_stall_endpoint_3 96.30 100.00 88.89 100.00
u_out_stall_endpoint_4 96.30 100.00 88.89 100.00
u_out_stall_endpoint_5 96.30 100.00 88.89 100.00
u_out_stall_endpoint_6 96.30 100.00 88.89 100.00
u_out_stall_endpoint_7 96.30 100.00 88.89 100.00
u_out_stall_endpoint_8 96.30 100.00 88.89 100.00
u_out_stall_endpoint_9 96.30 100.00 88.89 100.00
u_phy_config_eop_single_bit 100.00 100.00 100.00 100.00
u_phy_config_pinflip 100.00 100.00 100.00 100.00
u_phy_config_tx_osc_test_mode 100.00 100.00 100.00 100.00
u_phy_config_tx_use_d_se0 100.00 100.00 100.00 100.00
u_phy_config_usb_ref_disable 100.00 100.00 100.00 100.00
u_phy_config_use_diff_rcvr 100.00 100.00 100.00 100.00
u_phy_pins_drive_d_o 100.00 100.00 100.00 100.00
u_phy_pins_drive_dn_o 100.00 100.00 100.00 100.00
u_phy_pins_drive_dn_pullup_en_o 100.00 100.00 100.00 100.00
u_phy_pins_drive_dp_o 100.00 100.00 100.00 100.00
u_phy_pins_drive_dp_pullup_en_o 100.00 100.00 100.00 100.00
u_phy_pins_drive_en 100.00 100.00 100.00 100.00
u_phy_pins_drive_oe_o 100.00 100.00 100.00 100.00
u_phy_pins_drive_rx_enable_o 100.00 100.00 100.00 100.00
u_phy_pins_drive_se0_o 100.00 100.00 100.00 100.00
u_phy_pins_sense_pwr_sense 66.67 66.67
u_phy_pins_sense_rx_d_i 66.67 66.67
u_phy_pins_sense_rx_dn_i 66.67 66.67
u_phy_pins_sense_rx_dp_i 66.67 66.67
u_phy_pins_sense_tx_d_o 66.67 66.67
u_phy_pins_sense_tx_dn_o 66.67 66.67
u_phy_pins_sense_tx_dp_o 66.67 66.67
u_phy_pins_sense_tx_oe_o 66.67 66.67
u_phy_pins_sense_tx_se0_o 66.67 66.67
u_prim_reg_we_check 100.00 100.00 100.00
u_reg_if 98.69 97.14 97.62 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00
u_rxenable_out_out_0 96.30 100.00 88.89 100.00
u_rxenable_out_out_1 96.30 100.00 88.89 100.00
u_rxenable_out_out_10 96.30 100.00 88.89 100.00
u_rxenable_out_out_11 96.30 100.00 88.89 100.00
u_rxenable_out_out_2 96.30 100.00 88.89 100.00
u_rxenable_out_out_3 96.30 100.00 88.89 100.00
u_rxenable_out_out_4 96.30 100.00 88.89 100.00
u_rxenable_out_out_5 96.30 100.00 88.89 100.00
u_rxenable_out_out_6 96.30 100.00 88.89 100.00
u_rxenable_out_out_7 96.30 100.00 88.89 100.00
u_rxenable_out_out_8 96.30 100.00 88.89 100.00
u_rxenable_out_out_9 96.30 100.00 88.89 100.00
u_rxenable_setup_setup_0 100.00 100.00 100.00 100.00
u_rxenable_setup_setup_1 100.00 100.00 100.00 100.00
u_rxenable_setup_setup_10 100.00 100.00 100.00 100.00
u_rxenable_setup_setup_11 100.00 100.00 100.00 100.00
u_rxenable_setup_setup_2 100.00 100.00 100.00 100.00
u_rxenable_setup_setup_3 100.00 100.00 100.00 100.00
u_rxenable_setup_setup_4 100.00 100.00 100.00 100.00
u_rxenable_setup_setup_5 100.00 100.00 100.00 100.00
u_rxenable_setup_setup_6 100.00 100.00 100.00 100.00
u_rxenable_setup_setup_7 100.00 100.00 100.00 100.00
u_rxenable_setup_setup_8 100.00 100.00 100.00 100.00
u_rxenable_setup_setup_9 100.00 100.00 100.00 100.00
u_rxfifo_buffer 100.00 100.00
u_rxfifo_ep 100.00 100.00
u_rxfifo_setup 100.00 100.00
u_rxfifo_size 100.00 100.00
u_set_nak_out_enable_0 100.00 100.00 100.00 100.00
u_set_nak_out_enable_1 100.00 100.00 100.00 100.00
u_set_nak_out_enable_10 100.00 100.00 100.00 100.00
u_set_nak_out_enable_11 100.00 100.00 100.00 100.00
u_set_nak_out_enable_2 100.00 100.00 100.00 100.00
u_set_nak_out_enable_3 100.00 100.00 100.00 100.00
u_set_nak_out_enable_4 100.00 100.00 100.00 100.00
u_set_nak_out_enable_5 100.00 100.00 100.00 100.00
u_set_nak_out_enable_6 100.00 100.00 100.00 100.00
u_set_nak_out_enable_7 100.00 100.00 100.00 100.00
u_set_nak_out_enable_8 100.00 100.00 100.00 100.00
u_set_nak_out_enable_9 100.00 100.00 100.00 100.00
u_socket 98.24 98.75 98.21 96.00 100.00
u_usbctrl0_qe 100.00 100.00 100.00
u_usbctrl_device_address 96.30 100.00 88.89 100.00
u_usbctrl_enable 100.00 100.00 100.00 100.00
u_usbctrl_resume_link_active 100.00 100.00 100.00 100.00
u_usbstat_av_depth 66.67 66.67
u_usbstat_av_full 66.67 66.67
u_usbstat_frame 66.67 66.67
u_usbstat_host_lost 66.67 66.67
u_usbstat_link_state 66.67 66.67
u_usbstat_rx_depth 66.67 66.67
u_usbstat_rx_empty 66.67 66.67
u_usbstat_sense 66.67 66.67
u_wake_control_cdc 98.13 96.08 96.43 100.00 100.00
u_wake_control_suspend_req 100.00 100.00
u_wake_control_wake_ack 100.00 100.00
u_wake_events_bus_reset 58.89 66.67 50.00 60.00
u_wake_events_cdc 45.74 76.56 25.00 61.40 20.00
u_wake_events_disconnected 58.89 66.67 50.00 60.00
u_wake_events_module_active 58.89 66.67 50.00 60.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : usbdev_reg_top
Line No.TotalCoveredPercent
TOTAL70770599.72
ALWAYS7544100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN10211100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10611100.00
ALWAYS13233100.00
CONT_ASSIGN16911100.00
CONT_ASSIGN17011100.00
ALWAYS714100.00
CONT_ASSIGN74111100.00
ALWAYS75588100.00
CONT_ASSIGN171611100.00
CONT_ASSIGN173111100.00
CONT_ASSIGN174711100.00
CONT_ASSIGN176311100.00
CONT_ASSIGN177911100.00
CONT_ASSIGN179511100.00
CONT_ASSIGN181111100.00
CONT_ASSIGN182711100.00
CONT_ASSIGN184311100.00
CONT_ASSIGN185911100.00
CONT_ASSIGN187511100.00
CONT_ASSIGN189111100.00
CONT_ASSIGN190711100.00
CONT_ASSIGN192311100.00
CONT_ASSIGN193911100.00
CONT_ASSIGN195511100.00
CONT_ASSIGN197111100.00
CONT_ASSIGN198711100.00
CONT_ASSIGN199311100.00
CONT_ASSIGN200711100.00
CONT_ASSIGN207511100.00
CONT_ASSIGN291811100.00
CONT_ASSIGN697011100.00
CONT_ASSIGN699811100.00
CONT_ASSIGN702611100.00
CONT_ASSIGN705411100.00
CONT_ASSIGN708211100.00
CONT_ASSIGN711011100.00
CONT_ASSIGN713811100.00
CONT_ASSIGN716611100.00
CONT_ASSIGN719411100.00
CONT_ASSIGN722211100.00
CONT_ASSIGN725011100.00
CONT_ASSIGN727811100.00
CONT_ASSIGN783011100.00
CONT_ASSIGN784511100.00
CONT_ASSIGN786111100.00
CONT_ASSIGN7866100.00
ALWAYS79523737100.00
CONT_ASSIGN799111100.00
ALWAYS799511100.00
CONT_ASSIGN803511100.00
CONT_ASSIGN803711100.00
CONT_ASSIGN803911100.00
CONT_ASSIGN804111100.00
CONT_ASSIGN804311100.00
CONT_ASSIGN804511100.00
CONT_ASSIGN804711100.00
CONT_ASSIGN804911100.00
CONT_ASSIGN805111100.00
CONT_ASSIGN805311100.00
CONT_ASSIGN805511100.00
CONT_ASSIGN805711100.00
CONT_ASSIGN805911100.00
CONT_ASSIGN806111100.00
CONT_ASSIGN806311100.00
CONT_ASSIGN806511100.00
CONT_ASSIGN806711100.00
CONT_ASSIGN806911100.00
CONT_ASSIGN807011100.00
CONT_ASSIGN807211100.00
CONT_ASSIGN807411100.00
CONT_ASSIGN807611100.00
CONT_ASSIGN807811100.00
CONT_ASSIGN808011100.00
CONT_ASSIGN808211100.00
CONT_ASSIGN808411100.00
CONT_ASSIGN808611100.00
CONT_ASSIGN808811100.00
CONT_ASSIGN809011100.00
CONT_ASSIGN809211100.00
CONT_ASSIGN809411100.00
CONT_ASSIGN809611100.00
CONT_ASSIGN809811100.00
CONT_ASSIGN810011100.00
CONT_ASSIGN810211100.00
CONT_ASSIGN810411100.00
CONT_ASSIGN810511100.00
CONT_ASSIGN810711100.00
CONT_ASSIGN810911100.00
CONT_ASSIGN811111100.00
CONT_ASSIGN811311100.00
CONT_ASSIGN811511100.00
CONT_ASSIGN811711100.00
CONT_ASSIGN811911100.00
CONT_ASSIGN812111100.00
CONT_ASSIGN812311100.00
CONT_ASSIGN812511100.00
CONT_ASSIGN812711100.00
CONT_ASSIGN812911100.00
CONT_ASSIGN813111100.00
CONT_ASSIGN813311100.00
CONT_ASSIGN813511100.00
CONT_ASSIGN813711100.00
CONT_ASSIGN813911100.00
CONT_ASSIGN814011100.00
CONT_ASSIGN814211100.00
CONT_ASSIGN814311100.00
CONT_ASSIGN814511100.00
CONT_ASSIGN814711100.00
CONT_ASSIGN814911100.00
CONT_ASSIGN815011100.00
CONT_ASSIGN815211100.00
CONT_ASSIGN815411100.00
CONT_ASSIGN815611100.00
CONT_ASSIGN815811100.00
CONT_ASSIGN816011100.00
CONT_ASSIGN816211100.00
CONT_ASSIGN816411100.00
CONT_ASSIGN816611100.00
CONT_ASSIGN816811100.00
CONT_ASSIGN817011100.00
CONT_ASSIGN817211100.00
CONT_ASSIGN817411100.00
CONT_ASSIGN817511100.00
CONT_ASSIGN817711100.00
CONT_ASSIGN817911100.00
CONT_ASSIGN818111100.00
CONT_ASSIGN818311100.00
CONT_ASSIGN818511100.00
CONT_ASSIGN818711100.00
CONT_ASSIGN818911100.00
CONT_ASSIGN819111100.00
CONT_ASSIGN819311100.00
CONT_ASSIGN819511100.00
CONT_ASSIGN819711100.00
CONT_ASSIGN819911100.00
CONT_ASSIGN820011100.00
CONT_ASSIGN820111100.00
CONT_ASSIGN820311100.00
CONT_ASSIGN820411100.00
CONT_ASSIGN820511100.00
CONT_ASSIGN820711100.00
CONT_ASSIGN820911100.00
CONT_ASSIGN821111100.00
CONT_ASSIGN821311100.00
CONT_ASSIGN821511100.00
CONT_ASSIGN821711100.00
CONT_ASSIGN821911100.00
CONT_ASSIGN822111100.00
CONT_ASSIGN822311100.00
CONT_ASSIGN822511100.00
CONT_ASSIGN822711100.00
CONT_ASSIGN822911100.00
CONT_ASSIGN823011100.00
CONT_ASSIGN823211100.00
CONT_ASSIGN823411100.00
CONT_ASSIGN823611100.00
CONT_ASSIGN823811100.00
CONT_ASSIGN824011100.00
CONT_ASSIGN824211100.00
CONT_ASSIGN824411100.00
CONT_ASSIGN824611100.00
CONT_ASSIGN824811100.00
CONT_ASSIGN825011100.00
CONT_ASSIGN825211100.00
CONT_ASSIGN825411100.00
CONT_ASSIGN825511100.00
CONT_ASSIGN825711100.00
CONT_ASSIGN825911100.00
CONT_ASSIGN826111100.00
CONT_ASSIGN826311100.00
CONT_ASSIGN826511100.00
CONT_ASSIGN826711100.00
CONT_ASSIGN826911100.00
CONT_ASSIGN827111100.00
CONT_ASSIGN827311100.00
CONT_ASSIGN827511100.00
CONT_ASSIGN827711100.00
CONT_ASSIGN827911100.00
CONT_ASSIGN828011100.00
CONT_ASSIGN828211100.00
CONT_ASSIGN828411100.00
CONT_ASSIGN828611100.00
CONT_ASSIGN828811100.00
CONT_ASSIGN829011100.00
CONT_ASSIGN829211100.00
CONT_ASSIGN829411100.00
CONT_ASSIGN829611100.00
CONT_ASSIGN829811100.00
CONT_ASSIGN830011100.00
CONT_ASSIGN830211100.00
CONT_ASSIGN830411100.00
CONT_ASSIGN830511100.00
CONT_ASSIGN830711100.00
CONT_ASSIGN830911100.00
CONT_ASSIGN831111100.00
CONT_ASSIGN831311100.00
CONT_ASSIGN831511100.00
CONT_ASSIGN831711100.00
CONT_ASSIGN831911100.00
CONT_ASSIGN832111100.00
CONT_ASSIGN832311100.00
CONT_ASSIGN832511100.00
CONT_ASSIGN832711100.00
CONT_ASSIGN832911100.00
CONT_ASSIGN833011100.00
CONT_ASSIGN833211100.00
CONT_ASSIGN833411100.00
CONT_ASSIGN833611100.00
CONT_ASSIGN833811100.00
CONT_ASSIGN834011100.00
CONT_ASSIGN834211100.00
CONT_ASSIGN834411100.00
CONT_ASSIGN834611100.00
CONT_ASSIGN834811100.00
CONT_ASSIGN835011100.00
CONT_ASSIGN835211100.00
CONT_ASSIGN835411100.00
CONT_ASSIGN835511100.00
CONT_ASSIGN835711100.00
CONT_ASSIGN835911100.00
CONT_ASSIGN836111100.00
CONT_ASSIGN836311100.00
CONT_ASSIGN836411100.00
CONT_ASSIGN836611100.00
CONT_ASSIGN836811100.00
CONT_ASSIGN837011100.00
CONT_ASSIGN837211100.00
CONT_ASSIGN837311100.00
CONT_ASSIGN837511100.00
CONT_ASSIGN837711100.00
CONT_ASSIGN837911100.00
CONT_ASSIGN838111100.00
CONT_ASSIGN838211100.00
CONT_ASSIGN838411100.00
CONT_ASSIGN838611100.00
CONT_ASSIGN838811100.00
CONT_ASSIGN839011100.00
CONT_ASSIGN839111100.00
CONT_ASSIGN839311100.00
CONT_ASSIGN839511100.00
CONT_ASSIGN839711100.00
CONT_ASSIGN839911100.00
CONT_ASSIGN840011100.00
CONT_ASSIGN840211100.00
CONT_ASSIGN840411100.00
CONT_ASSIGN840611100.00
CONT_ASSIGN840811100.00
CONT_ASSIGN840911100.00
CONT_ASSIGN841111100.00
CONT_ASSIGN841311100.00
CONT_ASSIGN841511100.00
CONT_ASSIGN841711100.00
CONT_ASSIGN841811100.00
CONT_ASSIGN842011100.00
CONT_ASSIGN842211100.00
CONT_ASSIGN842411100.00
CONT_ASSIGN842611100.00
CONT_ASSIGN842711100.00
CONT_ASSIGN842911100.00
CONT_ASSIGN843111100.00
CONT_ASSIGN843311100.00
CONT_ASSIGN843511100.00
CONT_ASSIGN843611100.00
CONT_ASSIGN843811100.00
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CONT_ASSIGN844211100.00
CONT_ASSIGN844411100.00
CONT_ASSIGN844511100.00
CONT_ASSIGN844711100.00
CONT_ASSIGN844911100.00
CONT_ASSIGN845111100.00
CONT_ASSIGN845311100.00
CONT_ASSIGN845411100.00
CONT_ASSIGN845611100.00
CONT_ASSIGN845811100.00
CONT_ASSIGN846011100.00
CONT_ASSIGN846211100.00
CONT_ASSIGN846311100.00
CONT_ASSIGN846511100.00
CONT_ASSIGN846711100.00
CONT_ASSIGN846911100.00
CONT_ASSIGN847111100.00
CONT_ASSIGN847311100.00
CONT_ASSIGN847511100.00
CONT_ASSIGN847711100.00
CONT_ASSIGN847911100.00
CONT_ASSIGN848111100.00
CONT_ASSIGN848311100.00
CONT_ASSIGN848511100.00
CONT_ASSIGN848711100.00
CONT_ASSIGN848811100.00
CONT_ASSIGN849011100.00
CONT_ASSIGN849211100.00
CONT_ASSIGN849411100.00
CONT_ASSIGN849611100.00
CONT_ASSIGN849811100.00
CONT_ASSIGN850011100.00
CONT_ASSIGN850211100.00
CONT_ASSIGN850411100.00
CONT_ASSIGN850611100.00
CONT_ASSIGN850811100.00
CONT_ASSIGN851011100.00
CONT_ASSIGN851211100.00
CONT_ASSIGN851311100.00
CONT_ASSIGN851511100.00
CONT_ASSIGN851711100.00
CONT_ASSIGN851911100.00
CONT_ASSIGN852111100.00
CONT_ASSIGN852311100.00
CONT_ASSIGN852511100.00
CONT_ASSIGN852711100.00
CONT_ASSIGN852911100.00
CONT_ASSIGN853111100.00
CONT_ASSIGN853311100.00
CONT_ASSIGN853511100.00
CONT_ASSIGN853711100.00
CONT_ASSIGN853811100.00
CONT_ASSIGN853911100.00
CONT_ASSIGN854111100.00
CONT_ASSIGN854311100.00
CONT_ASSIGN854511100.00
CONT_ASSIGN854711100.00
CONT_ASSIGN854911100.00
CONT_ASSIGN855111100.00
CONT_ASSIGN855311100.00
CONT_ASSIGN855511100.00
CONT_ASSIGN855711100.00
CONT_ASSIGN855811100.00
CONT_ASSIGN856011100.00
CONT_ASSIGN856211100.00
CONT_ASSIGN856411100.00
CONT_ASSIGN856611100.00
CONT_ASSIGN856811100.00
CONT_ASSIGN857011100.00
CONT_ASSIGN857111100.00
ALWAYS85773737100.00
ALWAYS8618276276100.00
CONT_ASSIGN901211100.00
ALWAYS901444100.00
CONT_ASSIGN903511100.00
CONT_ASSIGN903611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
75 1 1
76 1 1
77 1 1
78 1 1
MISSING_ELSE
84 1 1
102 1 1
103 1 1
105 1 1
106 1 1
132 1 1
138 1 1
139 1 1
MISSING_ELSE
169 1 1
170 1 1
714 0 1
741 1 1
755 1 1
756 1 1
757 1 1
758 1 1
759 1 1
760 1 1
761 1 1
762 1 1
1716 1 1
1731 1 1
1747 1 1
1763 1 1
1779 1 1
1795 1 1
1811 1 1
1827 1 1
1843 1 1
1859 1 1
1875 1 1
1891 1 1
1907 1 1
1923 1 1
1939 1 1
1955 1 1
1971 1 1
1987 1 1
1993 1 1
2007 1 1
2075 1 1
2918 1 1
6970 1 1
6998 1 1
7026 1 1
7054 1 1
7082 1 1
7110 1 1
7138 1 1
7166 1 1
7194 1 1
7222 1 1
7250 1 1
7278 1 1
7830 1 1
7845 1 1
7861 1 1
7866 0 1
7952 1 1
7953 1 1
7954 1 1
7955 1 1
7956 1 1
7957 1 1
7958 1 1
7959 1 1
7960 1 1
7961 1 1
7962 1 1
7963 1 1
7964 1 1
7965 1 1
7966 1 1
7967 1 1
7968 1 1
7969 1 1
7970 1 1
7971 1 1
7972 1 1
7973 1 1
7974 1 1
7975 1 1
7976 1 1
7977 1 1
7978 1 1
7979 1 1
7980 1 1
7981 1 1
7982 1 1
7983 1 1
7984 1 1
7985 1 1
7986 1 1
7987 1 1
7988 1 1
7991 1 1
7995 1 1
8035 1 1
8037 1 1
8039 1 1
8041 1 1
8043 1 1
8045 1 1
8047 1 1
8049 1 1
8051 1 1
8053 1 1
8055 1 1
8057 1 1
8059 1 1
8061 1 1
8063 1 1
8065 1 1
8067 1 1
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8070 1 1
8072 1 1
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8076 1 1
8078 1 1
8080 1 1
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8084 1 1
8086 1 1
8088 1 1
8090 1 1
8092 1 1
8094 1 1
8096 1 1
8098 1 1
8100 1 1
8102 1 1
8104 1 1
8105 1 1
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8109 1 1
8111 1 1
8113 1 1
8115 1 1
8117 1 1
8119 1 1
8121 1 1
8123 1 1
8125 1 1
8127 1 1
8129 1 1
8131 1 1
8133 1 1
8135 1 1
8137 1 1
8139 1 1
8140 1 1
8142 1 1
8143 1 1
8145 1 1
8147 1 1
8149 1 1
8150 1 1
8152 1 1
8154 1 1
8156 1 1
8158 1 1
8160 1 1
8162 1 1
8164 1 1
8166 1 1
8168 1 1
8170 1 1
8172 1 1
8174 1 1
8175 1 1
8177 1 1
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8181 1 1
8183 1 1
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8187 1 1
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8191 1 1
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8195 1 1
8197 1 1
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8200 1 1
8201 1 1
8203 1 1
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8205 1 1
8207 1 1
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8211 1 1
8213 1 1
8215 1 1
8217 1 1
8219 1 1
8221 1 1
8223 1 1
8225 1 1
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8229 1 1
8230 1 1
8232 1 1
8234 1 1
8236 1 1
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8240 1 1
8242 1 1
8244 1 1
8246 1 1
8248 1 1
8250 1 1
8252 1 1
8254 1 1
8255 1 1
8257 1 1
8259 1 1
8261 1 1
8263 1 1
8265 1 1
8267 1 1
8269 1 1
8271 1 1
8273 1 1
8275 1 1
8277 1 1
8279 1 1
8280 1 1
8282 1 1
8284 1 1
8286 1 1
8288 1 1
8290 1 1
8292 1 1
8294 1 1
8296 1 1
8298 1 1
8300 1 1
8302 1 1
8304 1 1
8305 1 1
8307 1 1
8309 1 1
8311 1 1
8313 1 1
8315 1 1
8317 1 1
8319 1 1
8321 1 1
8323 1 1
8325 1 1
8327 1 1
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8330 1 1
8332 1 1
8334 1 1
8336 1 1
8338 1 1
8340 1 1
8342 1 1
8344 1 1
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8348 1 1
8350 1 1
8352 1 1
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8355 1 1
8357 1 1
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8361 1 1
8363 1 1
8364 1 1
8366 1 1
8368 1 1
8370 1 1
8372 1 1
8373 1 1
8375 1 1
8377 1 1
8379 1 1
8381 1 1
8382 1 1
8384 1 1
8386 1 1
8388 1 1
8390 1 1
8391 1 1
8393 1 1
8395 1 1
8397 1 1
8399 1 1
8400 1 1
8402 1 1
8404 1 1
8406 1 1
8408 1 1
8409 1 1
8411 1 1
8413 1 1
8415 1 1
8417 1 1
8418 1 1
8420 1 1
8422 1 1
8424 1 1
8426 1 1
8427 1 1
8429 1 1
8431 1 1
8433 1 1
8435 1 1
8436 1 1
8438 1 1
8440 1 1
8442 1 1
8444 1 1
8445 1 1
8447 1 1
8449 1 1
8451 1 1
8453 1 1
8454 1 1
8456 1 1
8458 1 1
8460 1 1
8462 1 1
8463 1 1
8465 1 1
8467 1 1
8469 1 1
8471 1 1
8473 1 1
8475 1 1
8477 1 1
8479 1 1
8481 1 1
8483 1 1
8485 1 1
8487 1 1
8488 1 1
8490 1 1
8492 1 1
8494 1 1
8496 1 1
8498 1 1
8500 1 1
8502 1 1
8504 1 1
8506 1 1
8508 1 1
8510 1 1
8512 1 1
8513 1 1
8515 1 1
8517 1 1
8519 1 1
8521 1 1
8523 1 1
8525 1 1
8527 1 1
8529 1 1
8531 1 1
8533 1 1
8535 1 1
8537 1 1
8538 1 1
8539 1 1
8541 1 1
8543 1 1
8545 1 1
8547 1 1
8549 1 1
8551 1 1
8553 1 1
8555 1 1
8557 1 1
8558 1 1
8560 1 1
8562 1 1
8564 1 1
8566 1 1
8568 1 1
8570 1 1
8571 1 1
8577 1 1
8578 1 1
8579 1 1
8580 1 1
8581 1 1
8582 1 1
8583 1 1
8584 1 1
8585 1 1
8586 1 1
8587 1 1
8588 1 1
8589 1 1
8590 1 1
8591 1 1
8592 1 1
8593 1 1
8594 1 1
8595 1 1
8596 1 1
8597 1 1
8598 1 1
8599 1 1
8600 1 1
8601 1 1
8602 1 1
8603 1 1
8604 1 1
8605 1 1
8606 1 1
8607 1 1
8608 1 1
8609 1 1
8610 1 1
8611 1 1
8612 1 1
8613 1 1
8618 1 1
8619 1 1
8621 1 1
8622 1 1
8623 1 1
8624 1 1
8625 1 1
8626 1 1
8627 1 1
8628 1 1
8629 1 1
8630 1 1
8631 1 1
8632 1 1
8633 1 1
8634 1 1
8635 1 1
8636 1 1
8637 1 1
8641 1 1
8642 1 1
8643 1 1
8644 1 1
8645 1 1
8646 1 1
8647 1 1
8648 1 1
8649 1 1
8650 1 1
8651 1 1
8652 1 1
8653 1 1
8654 1 1
8655 1 1
8656 1 1
8657 1 1
8661 1 1
8662 1 1
8663 1 1
8664 1 1
8665 1 1
8666 1 1
8667 1 1
8668 1 1
8669 1 1
8670 1 1
8671 1 1
8672 1 1
8673 1 1
8674 1 1
8675 1 1
8676 1 1
8677 1 1
8681 1 1
8685 1 1
8686 1 1
8687 1 1
8691 1 1
8692 1 1
8693 1 1
8694 1 1
8695 1 1
8696 1 1
8697 1 1
8698 1 1
8699 1 1
8700 1 1
8701 1 1
8702 1 1
8706 1 1
8707 1 1
8708 1 1
8709 1 1
8710 1 1
8711 1 1
8712 1 1
8713 1 1
8714 1 1
8715 1 1
8716 1 1
8717 1 1
8721 1 1
8722 1 1
8723 1 1
8724 1 1
8725 1 1
8726 1 1
8727 1 1
8728 1 1
8732 1 1
8736 1 1
8737 1 1
8738 1 1
8739 1 1
8743 1 1
8744 1 1
8745 1 1
8746 1 1
8747 1 1
8748 1 1
8749 1 1
8750 1 1
8751 1 1
8752 1 1
8753 1 1
8754 1 1
8758 1 1
8759 1 1
8760 1 1
8761 1 1
8762 1 1
8763 1 1
8764 1 1
8765 1 1
8766 1 1
8767 1 1
8768 1 1
8769 1 1
8773 1 1
8774 1 1
8775 1 1
8776 1 1
8777 1 1
8778 1 1
8779 1 1
8780 1 1
8781 1 1
8782 1 1
8783 1 1
8784 1 1
8788 1 1
8789 1 1
8790 1 1
8791 1 1
8792 1 1
8793 1 1
8794 1 1
8795 1 1
8796 1 1
8797 1 1
8798 1 1
8799 1 1
8803 1 1
8804 1 1
8805 1 1
8806 1 1
8807 1 1
8808 1 1
8809 1 1
8810 1 1
8811 1 1
8812 1 1
8813 1 1
8814 1 1
8818 1 1
8819 1 1
8820 1 1
8821 1 1
8822 1 1
8823 1 1
8824 1 1
8825 1 1
8826 1 1
8827 1 1
8828 1 1
8829 1 1
8833 1 1
8834 1 1
8835 1 1
8836 1 1
8840 1 1
8841 1 1
8842 1 1
8843 1 1
8847 1 1
8848 1 1
8849 1 1
8850 1 1
8854 1 1
8855 1 1
8856 1 1
8857 1 1
8861 1 1
8862 1 1
8863 1 1
8864 1 1
8868 1 1
8869 1 1
8870 1 1
8871 1 1
8875 1 1
8876 1 1
8877 1 1
8878 1 1
8882 1 1
8883 1 1
8884 1 1
8885 1 1
8889 1 1
8890 1 1
8891 1 1
8892 1 1
8896 1 1
8897 1 1
8898 1 1
8899 1 1
8903 1 1
8904 1 1
8905 1 1
8906 1 1
8910 1 1
8911 1 1
8912 1 1
8913 1 1
8917 1 1
8918 1 1
8919 1 1
8920 1 1
8921 1 1
8922 1 1
8923 1 1
8924 1 1
8925 1 1
8926 1 1
8927 1 1
8928 1 1
8932 1 1
8933 1 1
8934 1 1
8935 1 1
8936 1 1
8937 1 1
8938 1 1
8939 1 1
8940 1 1
8941 1 1
8942 1 1
8943 1 1
8947 1 1
8948 1 1
8949 1 1
8950 1 1
8951 1 1
8952 1 1
8953 1 1
8954 1 1
8955 1 1
8956 1 1
8957 1 1
8958 1 1
8962 1 1
8963 1 1
8964 1 1
8965 1 1
8966 1 1
8967 1 1
8968 1 1
8969 1 1
8970 1 1
8974 1 1
8975 1 1
8976 1 1
8977 1 1
8978 1 1
8979 1 1
8980 1 1
8981 1 1
8982 1 1
8986 1 1
8987 1 1
8988 1 1
8989 1 1
8990 1 1
8991 1 1
8995 1 1
8998 1 1
9012 1 1
9014 1 1
9015 1 1
9017 1 1
9020 1 1
9035 1 1
9036 1 1


Cond Coverage for Module : usbdev_reg_top
TotalCoveredPercent
Conditions38337898.69
Logical38337898.69
Non-Logical00
Event00

 LINE       65
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT14,T15,T16
11CoveredT1,T2,T3

 LINE       77
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T18,T19
10CoveredT15,T64,T77

 LINE       84
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT17,T18,T19
010CoveredT15,T64,T77
100CoveredT17,T18,T19

 LINE       132
 EXPRESSION ((tl_i.a_address[(AW - 1):0] inside {[2048:4095]}) ? 1'b0 : 1'b1)
             ------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       170
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT15,T64,T77
010CoveredT14,T16,T52
100CoveredT14,T16,T52

 LINE       7953
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_INTR_STATE_OFFSET)
            ---------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       7954
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_INTR_ENABLE_OFFSET)
            ---------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       7955
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_INTR_TEST_OFFSET)
            --------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT25,T21,T61

 LINE       7956
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_ALERT_TEST_OFFSET)
            ---------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T61,T24

 LINE       7957
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_USBCTRL_OFFSET)
            -------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       7958
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_EP_OUT_ENABLE_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       7959
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_EP_IN_ENABLE_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T61,T24

 LINE       7960
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_USBSTAT_OFFSET)
            -------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T61,T24

 LINE       7961
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_AVBUFFER_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       7962
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_RXFIFO_OFFSET)
            -------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       7963
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_RXENABLE_SETUP_OFFSET)
            -----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       7964
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_RXENABLE_OUT_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       7965
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_SET_NAK_OUT_OFFSET)
            ---------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT78,T21,T24

 LINE       7966
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_IN_SENT_OFFSET)
            -------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT38,T79,T80

 LINE       7967
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_OUT_STALL_OFFSET)
            --------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T61,T24

 LINE       7968
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_IN_STALL_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT81,T19,T21

 LINE       7969
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_0_OFFSET)
            ---------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T61,T24

 LINE       7970
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_1_OFFSET)
            ---------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT82,T21,T61

 LINE       7971
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_2_OFFSET)
            ---------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T24,T14

 LINE       7972
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_3_OFFSET)
            ---------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T61,T24

 LINE       7973
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_4_OFFSET)
            ---------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT83,T21,T61

 LINE       7974
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_5_OFFSET)
            ---------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T61,T24

 LINE       7975
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_6_OFFSET)
            ---------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T61,T24

 LINE       7976
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_7_OFFSET)
            ---------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T61,T24

 LINE       7977
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_8_OFFSET)
            ---------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T61,T24

 LINE       7978
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_9_OFFSET)
            ---------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T61,T24

 LINE       7979
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_10_OFFSET)
            ---------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT81,T21,T24

 LINE       7980
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_11_OFFSET)
            ---------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T84,T21

 LINE       7981
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_OUT_ISO_OFFSET)
            -------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T21,T24

 LINE       7982
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_IN_ISO_OFFSET)
            -------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT35,T78,T21

 LINE       7983
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_DATA_TOGGLE_CLEAR_OFFSET)
            ------------------------------1------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT85,T21,T61

 LINE       7984
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_PHY_PINS_SENSE_OFFSET)
            -----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T24,T14

 LINE       7985
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_PHY_PINS_DRIVE_OFFSET)
            -----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T61,T24

 LINE       7986
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_PHY_CONFIG_OFFSET)
            ---------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T61,T24

 LINE       7987
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_WAKE_CONTROL_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT86,T21,T61

 LINE       7988
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_WAKE_EVENTS_OFFSET)
            ---------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T61,T24

 LINE       7991
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       7991
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       7995
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[1] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[2] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[11] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[12] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[13] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[14] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[28] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[29] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[30] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[31] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[32] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[33] & ((|(4'b1 & (~reg_be))))) | (addr_hit[34] & ((|(4'b1 & (~reg_be))))) | (addr_hit[35] & ((|(4'b0011 & (~reg_be)))))))
-1--2-StatusTests
01CoveredT1,T2,T7
10CoveredT1,T2,T3
11CoveredT14,T16,T52

 LINE       7995
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b0111 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b0111 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b0111 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b0111 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b0111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b0011 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b0011 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b0011 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b0011 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b0011 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b0011 & (~reg_be))))) | 
     30  (addr_hit[29] & ((|(4'b0011 & (~reg_be))))) | 
     31  (addr_hit[30] & ((|(4'b0011 & (~reg_be))))) | 
     32  (addr_hit[31] & ((|(4'b0111 & (~reg_be))))) | 
     33  (addr_hit[32] & ((|(4'b0111 & (~reg_be))))) | 
     34  (addr_hit[33] & ((|(4'b1 & (~reg_be))))) | 
     35  (addr_hit[34] & ((|(4'b1 & (~reg_be))))) | 
     36  (addr_hit[35] & ((|(4'b0011 & (~reg_be))))))
Sensitive Expression == 1StatusTests
ALL ZEROSCoveredT1,T2,T3
36 (addr_hit[35] & ((|(4'...CoveredT21,T61,T24
35 (addr_hit[34] & ((|(4'...CoveredT86,T24,T14
34 (addr_hit[33] & ((|(4'...CoveredT61,T24,T14
33 (addr_hit[32] & ((|(4'...CoveredT21,T61,T24
32 (addr_hit[31] & ((|(4'...CoveredT21,T14,T16
31 (addr_hit[30] & ((|(4'...CoveredT85,T21,T61
30 (addr_hit[29] & ((|(4'...CoveredT78,T24,T14
29 (addr_hit[28] & ((|(4'...CoveredT4,T21,T24
28 (addr_hit[27] & ((|(4'...CoveredT4,T84,T21
27 (addr_hit[26] & ((|(4'...CoveredT81,T24,T14
26 (addr_hit[25] & ((|(4'...CoveredT21,T61,T24
25 (addr_hit[24] & ((|(4'...CoveredT21,T61,T24
24 (addr_hit[23] & ((|(4'...CoveredT61,T24,T14
23 (addr_hit[22] & ((|(4'...CoveredT21,T61,T24
22 (addr_hit[21] & ((|(4'...CoveredT21,T61,T24
21 (addr_hit[20] & ((|(4'...CoveredT83,T21,T61
20 (addr_hit[19] & ((|(4'...CoveredT21,T61,T24
19 (addr_hit[18] & ((|(4'...CoveredT21,T24,T14
18 (addr_hit[17] & ((|(4'...CoveredT21,T61,T24
17 (addr_hit[16] & ((|(4'...CoveredT24,T14,T15
16 (addr_hit[15] & ((|(4'...CoveredT81,T19,T21
15 (addr_hit[14] & ((|(4'...CoveredT21,T24,T14
14 (addr_hit[13] & ((|(4'...CoveredT79,T80,T21
13 (addr_hit[12] & ((|(4'...CoveredT21,T24,T14
12 (addr_hit[11] & ((|(4'...CoveredT24,T14,T15
11 (addr_hit[10] & ((|(4'...CoveredT21,T61,T24
10 (addr_hit[9] & ((|(4'b...CoveredT2,T7,T39
9 (addr_hit[8] & ((|(4'b...CoveredT24,T14,T22
8 (addr_hit[7] & ((|(4'b...CoveredT61,T24,T14
7 (addr_hit[6] & ((|(4'b...CoveredT21,T61,T24
6 (addr_hit[5] & ((|(4'b...CoveredT21,T61,T24
5 (addr_hit[4] & ((|(4'b...CoveredT21,T61,T24
4 (addr_hit[3] & ((|(4'b...CoveredT61,T24,T14
3 (addr_hit[2] & ((|(4'b...CoveredT25,T21,T61
2 (addr_hit[1] & ((|(4'b...CoveredT25,T61,T24
1 (addr_hit[0] & ((|(4'b...CoveredT1,T2,T7

 LINE       7995
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T7

 LINE       7995
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T6
11CoveredT25,T61,T24

 LINE       7995
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT25,T21,T24
11CoveredT25,T21,T61

 LINE       7995
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT21,T24,T15
11CoveredT61,T24,T14

 LINE       7995
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT21,T61,T24

 LINE       7995
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT21,T61,T24

 LINE       7995
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT21,T61,T24
11CoveredT21,T61,T24

 LINE       7995
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT21,T24,T15
11CoveredT61,T24,T14

 LINE       7995
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT24,T14,T22

 LINE       7995
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T8
11CoveredT2,T7,T39

 LINE       7995
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T6
11CoveredT21,T61,T24

 LINE       7995
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT24,T14,T15

 LINE       7995
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT78,T21,T24
11CoveredT21,T24,T14

 LINE       7995
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT38,T21,T24
11CoveredT79,T80,T21

 LINE       7995
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT21,T61,T24
11CoveredT21,T24,T14

 LINE       7995
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT21,T24,T15
11CoveredT81,T19,T21

 LINE       7995
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT21,T61,T24
11CoveredT24,T14,T15

 LINE       7995
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT82,T21,T24
11CoveredT21,T61,T24

 LINE       7995
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT21,T24,T15
11CoveredT21,T24,T14

 LINE       7995
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT21,T24,T15
11CoveredT21,T61,T24

 LINE       7995
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT21,T24,T14
11CoveredT83,T21,T61

 LINE       7995
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT21,T24,T14
11CoveredT21,T61,T24

 LINE       7995
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT21,T24,T15
11CoveredT21,T61,T24

 LINE       7995
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT21,T61,T24
11CoveredT61,T24,T14

 LINE       7995
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT21,T24,T15
11CoveredT21,T61,T24

 LINE       7995
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT21,T24,T14
11CoveredT21,T61,T24

 LINE       7995
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT21,T24,T15
11CoveredT81,T24,T14

 LINE       7995
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT21,T24,T15
11CoveredT4,T84,T21

 LINE       7995
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT21,T24,T15
11CoveredT4,T21,T24

 LINE       7995
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT35,T21,T24
11CoveredT78,T24,T14

 LINE       7995
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT21,T24,T15
11CoveredT85,T21,T61

 LINE       7995
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT21,T24,T15
11CoveredT21,T14,T16

 LINE       7995
 SUB-EXPRESSION (addr_hit[32] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT21,T24,T15
11CoveredT21,T61,T24

 LINE       7995
 SUB-EXPRESSION (addr_hit[33] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT21,T24,T15
11CoveredT61,T24,T14

 LINE       7995
 SUB-EXPRESSION (addr_hit[34] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT21,T61,T24
11CoveredT86,T24,T14

 LINE       7995
 SUB-EXPRESSION (addr_hit[35] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT21,T24,T15
11CoveredT21,T61,T24

 LINE       8035
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT14,T52,T53
111CoveredT1,T2,T3

 LINE       8070
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T5,T6
110CoveredT16,T52,T53
111CoveredT4,T5,T6

 LINE       8105
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT25,T21,T61
110CoveredT16,T52,T53
111CoveredT25,T26,T27

 LINE       8140
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT21,T61,T24
110CoveredT14,T16,T53
111CoveredT21,T24,T15

 LINE       8143
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT14,T16,T52
111CoveredT1,T2,T3

 LINE       8150
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT14,T53,T54
111CoveredT1,T2,T3

 LINE       8175
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT21,T61,T24
110CoveredT16,T52,T53
111CoveredT21,T24,T15

 LINE       8200
 EXPRESSION (addr_hit[7] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT21,T61,T24
110Not Covered
111Not Covered

 LINE       8201
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT14,T16,T52
111CoveredT1,T2,T3

 LINE       8204
 EXPRESSION (addr_hit[9] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       8205
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T5,T6
110CoveredT16,T53,T54
111CoveredT4,T5,T6

 LINE       8230
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT16,T53,T54
111CoveredT1,T2,T3

 LINE       8255
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT78,T21,T24
110CoveredT14,T16,T53
111CoveredT21,T24,T15

 LINE       8280
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT38,T79,T80
110CoveredT14,T16,T52
111CoveredT21,T24,T15

 LINE       8305
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT21,T61,T24
110CoveredT16,T52,T53
111CoveredT21,T24,T15

 LINE       8330
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT81,T19,T21
110CoveredT52,T53,T54
111CoveredT21,T24,T15

 LINE       8355
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT21,T61,T24
110CoveredT14,T16,T54
111CoveredT21,T24,T15

 LINE       8364
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT82,T21,T61
110CoveredT14,T16,T52
111CoveredT21,T24,T15

 LINE       8373
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT21,T24,T14
110CoveredT16,T52,T53
111CoveredT21,T24,T15

 LINE       8382
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT21,T61,T24
110CoveredT16,T53,T56
111CoveredT21,T24,T15

 LINE       8391
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT83,T21,T61
110CoveredT16,T52,T53
111CoveredT21,T24,T15

 LINE       8400
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT87,T21,T61
110CoveredT16,T53,T54
111CoveredT21,T24,T15

 LINE       8409
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT88,T21,T61
110CoveredT14,T53,T54
111CoveredT21,T24,T15

 LINE       8418
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT21,T61,T24
110CoveredT14,T16,T52
111CoveredT21,T24,T15

 LINE       8427
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT21,T61,T24
110CoveredT14,T53,T54
111CoveredT21,T24,T15

 LINE       8436
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT21,T61,T24
110CoveredT16,T53,T54
111CoveredT21,T24,T15

 LINE       8445
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT81,T21,T24
110CoveredT14,T16,T52
111CoveredT21,T24,T15

 LINE       8454
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T84,T21
110CoveredT14,T16,T53
111CoveredT21,T24,T15

 LINE       8463
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T21,T24
110CoveredT16,T52,T53
111CoveredT21,T24,T15

 LINE       8488
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT35,T78,T21
110CoveredT14,T16,T52
111CoveredT21,T24,T15

 LINE       8513
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT85,T21,T61
110CoveredT16,T56,T89
111CoveredT21,T24,T15

 LINE       8538
 EXPRESSION (addr_hit[31] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT21,T24,T14
110Not Covered
111Not Covered

 LINE       8539
 EXPRESSION (addr_hit[32] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT21,T61,T24
110CoveredT16,T52,T53
111CoveredT21,T24,T15

 LINE       8558
 EXPRESSION (addr_hit[33] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT21,T61,T24
110CoveredT16,T53,T56
111CoveredT21,T24,T15

 LINE       8571
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT86,T21,T61
110CoveredT14,T54,T56
111CoveredT21,T24,T15

 LINE       9012
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT21,T24,T15

Branch Coverage for Module : usbdev_reg_top
Line No.TotalCoveredPercent
Branches 49 49 100.00
TERNARY 7991 2 2 100.00
IF 75 3 3 100.00
TERNARY 132 2 2 100.00
IF 138 2 2 100.00
CASE 8619 37 37 100.00
CASE 9015 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 7991 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 75 if ((!rst_ni)) -2-: 77 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T17,T18,T19
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 132 ((tl_i.a_address[(AW - 1):0] inside {[2048:4095]})) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 if (intg_err)

Branches:
-1-StatusTests
1 Covered T15,T64,T77
0 Covered T1,T2,T3


LineNo. Expression -1-: 8619 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T1,T2,T3
addr_hit[1] Covered T1,T7,T8
addr_hit[2] Covered T1,T7,T8
addr_hit[3] Covered T1,T7,T8
addr_hit[4] Covered T1,T2,T3
addr_hit[5] Covered T1,T2,T3
addr_hit[6] Covered T1,T7,T8
addr_hit[7] Covered T1,T7,T8
addr_hit[8] Covered T1,T2,T3
addr_hit[9] Covered T1,T2,T3
addr_hit[10] Covered T1,T7,T8
addr_hit[11] Covered T1,T2,T3
addr_hit[12] Covered T1,T7,T8
addr_hit[13] Covered T1,T7,T8
addr_hit[14] Covered T1,T7,T8
addr_hit[15] Covered T1,T7,T8
addr_hit[16] Covered T1,T7,T8
addr_hit[17] Covered T1,T7,T8
addr_hit[18] Covered T1,T7,T8
addr_hit[19] Covered T1,T7,T8
addr_hit[20] Covered T1,T7,T8
addr_hit[21] Covered T1,T7,T8
addr_hit[22] Covered T1,T7,T8
addr_hit[23] Covered T1,T7,T8
addr_hit[24] Covered T1,T7,T8
addr_hit[25] Covered T1,T7,T8
addr_hit[26] Covered T1,T7,T8
addr_hit[27] Covered T1,T7,T8
addr_hit[28] Covered T1,T7,T8
addr_hit[29] Covered T1,T7,T8
addr_hit[30] Covered T1,T7,T8
addr_hit[31] Covered T1,T7,T8
addr_hit[32] Covered T1,T7,T8
addr_hit[33] Covered T1,T7,T8
addr_hit[34] Covered T1,T7,T8
addr_hit[35] Covered T1,T7,T8
default Covered T1,T2,T3


LineNo. Expression -1-: 9015 case (1'b1)

Branches:
-1-StatusTests
addr_hit[34] Covered T1,T7,T8
addr_hit[35] Covered T1,T7,T8
default Covered T1,T2,T3


Assert Coverage for Module : usbdev_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 51341712 60777 0 0
reAfterRv 51341712 60772 0 0
rePulse 51341712 42792 0 0
wePulse 51341712 17980 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 51341712 60777 0 0
T1 401813 10 0 0
T2 401865 10 0 0
T3 401831 10 0 0
T4 401855 12 0 0
T5 401821 12 0 0
T6 401892 12 0 0
T7 401795 10 0 0
T8 401784 10 0 0
T9 401890 10 0 0
T10 401706 10 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 51341712 60772 0 0
T1 401813 10 0 0
T2 401865 10 0 0
T3 401831 10 0 0
T4 401855 12 0 0
T5 401821 12 0 0
T6 401892 12 0 0
T7 401795 10 0 0
T8 401784 10 0 0
T9 401890 10 0 0
T10 401706 10 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 51341712 42792 0 0
T1 401813 3 0 0
T2 401865 3 0 0
T3 401831 3 0 0
T4 401855 3 0 0
T5 401821 3 0 0
T6 401892 3 0 0
T7 401795 3 0 0
T8 401784 3 0 0
T9 401890 3 0 0
T10 401706 3 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 51341712 17980 0 0
T1 401813 7 0 0
T2 401865 7 0 0
T3 401831 7 0 0
T4 401855 9 0 0
T5 401821 9 0 0
T6 401892 9 0 0
T7 401795 7 0 0
T8 401784 7 0 0
T9 401890 7 0 0
T10 401706 7 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%