Unified Coverage Report :: Module :: usbdev_usbif

Module : usbdev_usbif

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.61	97.06	94.20			91.18	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_usbif.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_impl	95.61	97.06	94.20			91.18	100.00

---

Module Instance : tb.dut.usbdev_impl

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.61	97.06	94.20			91.18	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.55	91.16	82.62		45.31	83.65	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.49	96.38	62.63	93.46		85.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_usb_fs_nb_pe	83.38	92.86	82.89		54.05	87.08	100.00
u_usbdev_linkstate	70.19	79.69	71.76		33.33	66.18	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : usbdev_usbif

	Line No.	Total	Covered	Percent
TOTAL		68	66	97.06
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	140	0	0
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
ALWAYS	148	6	6	100.00
CONT_ASSIGN	170	1	1	100.00
ALWAYS	174	6	6	100.00
ALWAYS	186	8	8	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	204	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	215	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
ALWAYS	234	5	5	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	264	0	0
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
ALWAYS	271	2	2	100.00
ALWAYS	278	3	3	100.00
CONT_ASSIGN	285	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
CONT_ASSIGN	379	1	1	100.00
CONT_ASSIGN	380	1	1	100.00
ALWAYS	383	5	3	60.00
ALWAYS	392	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_usbif.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_usbif.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
122	1	1
140		unreachable
141	1	1
143	1	1
144	1	1
145	1	1
148	1	1
149	1	1
151	1	1
155	1	1
156	1	1
157		unreachable
158		unreachable
160		unreachable
164	1	1
170	1	1
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
186	1	1
187	1	1
188	1	1
189	1	1
191	1	1
192	1	1
194	1	1
195	1	1
			MISSING_ELSE
203	1	1
204	1	1
209	1	1
212	1	1
214	1	1
215	1	1
216	1	1
217	1	1
219	1	1
223	1	1
225	1	1
231	1	1
234	1	1
235	1	1
236	1	1
238	1	1
239	1	1
244	1	1
246	1	1
248	1	1
249	1	1
254	1	1
264		unreachable
265	1	1
269	1	1
271	1	1
272	1	1
278	1	1
279	1	1
281	1	1
285	1	1
286	1	1
288	1	1
379	1	1
380	1	1
383	1	1
384	1	1
385	0	1
386	1	1
387	0	1
			MISSING_ELSE
392	1	1
393	1	1
395	1	1

---

Cond Coverage for Module : usbdev_usbif

	Total	Covered	Percent
Conditions	69	65	94.20
Logical	69	65	94.20
Non-Logical	0	0
Event	0	0

 LINE       122
 EXPRESSION (connect_en_i & usb_sense_i)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       141
 EXPRESSION (out_endpoint_val_o ? out_ep_current : '0)
             ---------1--------

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (((~connect_en_i)) | link_reset)
             --------1--------   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION (out_ep_acked || out_ep_rollback)
             ------1-----    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T2,T4

 LINE       170
 EXPRESSION (out_ep_data_put & (int'(out_max_used_q) < (MaxPktSizeByte - 1)) & (out_ep_put_addr[1:0] == 2'b11))
             -------1-------   ----------------------2----------------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Unreachable	T20,T21,T22
1	1	0	Covered	T1,T2,T4
1	1	1	Covered	T2,T4,T5

 LINE       170
 SUB-EXPRESSION (out_ep_put_addr[1:0] == 2'b11)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       203
 EXPRESSION (current_setup ? avsetup_rvalid_i : avout_rvalid_i)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T9,T142

 LINE       204
 EXPRESSION (current_setup ? avsetup_rdata_i : avout_rdata_i)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T9,T142

 LINE       209
 EXPRESSION (current_setup ? rx_wready_setup_i : rx_wready_out_i)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T9,T142

 LINE       212
 EXPRESSION (av_rvalid & (std_write_q | (((~out_max_used_q[PktW])) & (out_max_used_q[1:0] != 2'b11) & out_ep_acked)))
             ----1----   ---------------------------------------------2---------------------------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       212
 SUB-EXPRESSION (std_write_q | (((~out_max_used_q[PktW])) & (out_max_used_q[1:0] != 2'b11) & out_ep_acked))
                 -----1-----   -------------------------------------2-------------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T4,T5

 LINE       212
 SUB-EXPRESSION (((~out_max_used_q[PktW])) & (out_max_used_q[1:0] != 2'b11) & out_ep_acked)
                 ------------1------------   ---------------2--------------   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T20,T21,T22
1	0	1	Covered	T6,T10,T105
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T4

 LINE       212
 SUB-EXPRESSION (out_max_used_q[1:0] != 2'b11)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       216
 EXPRESSION (mem_write_o ? mem_waddr : mem_raddr)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       217
 EXPRESSION (mem_read | mem_write_o)
             ----1---   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T4,T5,T6

 LINE       238
 EXPRESSION (rx_wvalid_o & current_setup)
             -----1-----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T9,T142
1	0	Covered	T1,T2,T4
1	1	Covered	T7,T9,T16

 LINE       239
 EXPRESSION (rx_wvalid_o & ((~current_setup)))
             -----1-----   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T9,T16
1	1	Covered	T1,T2,T4

 LINE       246
 EXPRESSION (((~rx_wready)) | ((~av_rvalid)))
             -------1------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       254
 EXPRESSION (current_setup & rx_wvalid_o)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T7,T9,T142
1	1	Covered	T7,T9,T16

 LINE       265
 EXPRESSION (in_endpoint_val_o ? in_ep_current : '0)
             --------1--------

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       269
 EXPRESSION ({1'b0, in_ep_get_addr} == in_size_i)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 EXPRESSION (pkt_start_rd | (in_ep_data_get & (in_ep_get_addr[1:0] == 2'b0)))
             ------1-----   ------------------------2-----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       286
 SUB-EXPRESSION (in_ep_data_get & (in_ep_get_addr[1:0] == 2'b0))
                 -------1------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       286
 SUB-EXPRESSION (in_ep_get_addr[1:0] == 2'b0)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       288
 EXPRESSION (in_ep_get_addr[1] ? (in_ep_get_addr[0] ? mem_rdata_i[31:24] : mem_rdata_i[23:16]) : (in_ep_get_addr[0] ? mem_rdata_i[15:8] : mem_rdata_i[7:0]))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       288
 SUB-EXPRESSION (in_ep_get_addr[0] ? mem_rdata_i[31:24] : mem_rdata_i[23:16])
                 --------1--------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       288
 SUB-EXPRESSION (in_ep_get_addr[0] ? mem_rdata_i[15:8] : mem_rdata_i[7:0])
                 --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       380
 EXPRESSION (frame_q != frame_d)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Module : usbdev_usbif

	Line No.	Total	Covered	Percent
Branches		34	31	91.18
TERNARY	141	1	1	100.00
TERNARY	203	2	2	100.00
TERNARY	204	2	2	100.00
TERNARY	209	2	2	100.00
TERNARY	216	2	2	100.00
TERNARY	265	1	1	100.00
TERNARY	288	4	4	100.00
IF	148	3	3	100.00
CASE	176	5	4	80.00
IF	186	3	3	100.00
IF	234	2	2	100.00
IF	278	2	2	100.00
IF	384	3	1	33.33
IF	392	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_usbif.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_usbif.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	141	(out_endpoint_val_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	203	(current_setup) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T142
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	204	(current_setup) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T142
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	209	(current_setup) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T142
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	216	(mem_write_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	265	(in_endpoint_val_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	288	(in_ep_get_addr[1]) ? 
-2-:	288	(in_ep_get_addr[0]) ? 
-3-:	288	(in_ep_get_addr[0]) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T4,T5,T6
1	0	-	Covered	T4,T5,T6
0	-	1	Covered	T4,T5,T6
0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	if ((out_ep_acked || out_ep_rollback))
-2-:	151	if (out_ep_data_put)
-3-:	155	if ((int'(out_max_used_q) < (MaxPktSizeByte - 1)))
-4-:	157	if ((int'(out_max_used_q) < (MaxPktSizeByte + 1)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T4
0	1	1	-	Covered	T1,T2,T4
0	1	0	1	Unreachable	T20,T21,T22
0	1	0	0	Unreachable
0	0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	176	case (out_ep_put_addr[1:0])

Branches:

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4
2	Covered	T1,T2,T4
3	Covered	T1,T2,T4
default	Not Covered

	LineNo.	Expression
-1-:	186	if ((!rst_ni))
-2-:	194	if (out_ep_data_put)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	234	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	278	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	384	if (sof_valid_o)
-2-:	386	if (do_internal_sof)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	392	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : usbdev_usbif

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ParamAVFifoWidthValid	289	289	0	0
ParamMaxPktSizeByteValid	289	289	0	0
ParamNBufValid	289	289	0	0
ParamNEndpointsValid	289	289	0	0
ParamRXFifoWidthValid	289	289	0	0
ParamSramAwValid	289	289	0	0

ParamAVFifoWidthValid

Name	Attempts	Real Successes	Failures	Incomplete
Total	289	289	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

ParamMaxPktSizeByteValid

Name	Attempts	Real Successes	Failures	Incomplete
Total	289	289	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

ParamNBufValid

Name	Attempts	Real Successes	Failures	Incomplete
Total	289	289	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

ParamNEndpointsValid

Name	Attempts	Real Successes	Failures	Incomplete
Total	289	289	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

ParamRXFifoWidthValid

Name	Attempts	Real Successes	Failures	Incomplete
Total	289	289	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

ParamSramAwValid

Name	Attempts	Real Successes	Failures	Incomplete
Total	289	289	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0