Module Definition
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Module : usbdev_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.usbdev_csr_assert 100.00 100.00



Module Instance : tb.dut.usbdev_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
89.25 96.75 68.07 93.93 87.50 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : usbdev_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 10 10 100.00 10 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 10 10 100.00 10 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
TlulOOBAddrErr_A 238619403 10492 0 0
ep_in_enable_rd_A 238619403 1018 0 0
ep_out_enable_rd_A 238619403 820 0 0
in_iso_rd_A 238619403 1016 0 0
intr_enable_rd_A 238619403 1197 0 0
out_iso_rd_A 238619403 990 0 0
phy_config_rd_A 238619403 822 0 0
phy_pins_drive_rd_A 238619403 852 0 0
rxenable_setup_rd_A 238619403 910 0 0
set_nak_out_rd_A 238619403 777 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238619403 10492 0 0
T45 5491 291 0 0
T46 2815 15 0 0
T47 3836 713 0 0
T53 3494 10 0 0
T81 3975 8 0 0
T183 2358 227 0 0
T184 4529 768 0 0
T185 11759 517 0 0
T186 8782 451 0 0
T187 5836 17 0 0

ep_in_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238619403 1018 0 0
T54 6514 37 0 0
T56 18023 93 0 0
T81 3975 41 0 0
T190 10075 66 0 0
T193 4458 43 0 0
T195 2578 36 0 0
T200 4803 39 0 0
T235 3943 23 0 0
T236 3917 2 0 0
T237 3776 10 0 0

ep_out_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238619403 820 0 0
T54 6514 14 0 0
T56 18023 99 0 0
T57 2758 1 0 0
T58 2663 10 0 0
T81 3975 6 0 0
T190 10075 45 0 0
T193 4458 11 0 0
T195 2578 3 0 0
T200 4803 22 0 0
T235 3943 46 0 0

in_iso_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238619403 1016 0 0
T54 6514 17 0 0
T56 18023 132 0 0
T57 2758 7 0 0
T58 2663 6 0 0
T81 3975 10 0 0
T186 8782 9 0 0
T190 10075 59 0 0
T193 4458 49 0 0
T200 4803 29 0 0
T235 3943 33 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238619403 1197 0 0
T54 6514 10 0 0
T56 18023 131 0 0
T58 2663 5 0 0
T60 1246 13 0 0
T81 3975 76 0 0
T190 10075 60 0 0
T193 4458 158 0 0
T195 2578 71 0 0
T200 4803 4 0 0
T235 3943 32 0 0

out_iso_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238619403 990 0 0
T54 6514 10 0 0
T56 18023 124 0 0
T58 2663 6 0 0
T81 3975 3 0 0
T190 10075 60 0 0
T193 4458 82 0 0
T195 2578 45 0 0
T200 4803 24 0 0
T235 3943 26 0 0
T236 3917 4 0 0

phy_config_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238619403 822 0 0
T54 6514 12 0 0
T56 18023 127 0 0
T57 2758 8 0 0
T58 2663 2 0 0
T81 3975 25 0 0
T190 10075 80 0 0
T193 4458 24 0 0
T195 2578 16 0 0
T200 4803 19 0 0
T235 3943 41 0 0

phy_pins_drive_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238619403 852 0 0
T54 6514 28 0 0
T56 18023 142 0 0
T57 2758 1 0 0
T58 2663 9 0 0
T81 3975 7 0 0
T190 10075 79 0 0
T193 4458 38 0 0
T195 2578 31 0 0
T200 4803 25 0 0
T235 3943 23 0 0

rxenable_setup_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238619403 910 0 0
T54 6514 10 0 0
T56 18023 173 0 0
T57 2758 9 0 0
T58 2663 10 0 0
T81 3975 49 0 0
T190 10075 65 0 0
T193 4458 39 0 0
T195 2578 5 0 0
T200 4803 39 0 0
T235 3943 10 0 0

set_nak_out_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238619403 777 0 0
T56 18023 159 0 0
T57 2758 3 0 0
T58 2663 6 0 0
T81 3975 52 0 0
T190 10075 72 0 0
T193 4458 7 0 0
T195 2578 47 0 0
T200 4803 23 0 0
T235 3943 26 0 0
T236 3917 3 0 0