Unified Coverage Report :: Module :: usbdev

Module : usbdev

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.25	96.75	68.07	93.93		87.50	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	89.25	96.75	68.07	93.93		87.50	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.25	96.75	68.07	93.93		87.50	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.73	96.31	88.57	97.17	46.88	94.11	97.36

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_event	100.00	100.00				100.00
gen_no_stubbed_memory.u_memory_1p	98.96	95.83	100.00			100.00	100.00
gen_no_stubbed_memory.u_tlul2sram	83.77	85.71	70.94			78.41	100.00
i_usbdev_iomux	82.50	100.00	80.00			100.00	50.00
intr_av_out_empty	81.39	90.00	55.56			80.00	100.00
intr_av_overflow	81.25	100.00	25.00			100.00	100.00
intr_av_setup_empty	81.39	90.00	55.56			80.00	100.00
intr_disconnected	89.58	100.00	58.33			100.00	100.00
intr_frame	81.25	100.00	25.00			100.00	100.00
intr_host_lost	81.25	100.00	25.00			100.00	100.00
intr_hw_pkt_received	86.94	90.00	77.78			80.00	100.00
intr_hw_pkt_sent	86.94	90.00	77.78			80.00	100.00
intr_link_in_err	81.25	100.00	25.00			100.00	100.00
intr_link_out_err	89.58	100.00	58.33			100.00	100.00
intr_link_reset	89.58	100.00	58.33			100.00	100.00
intr_link_resume	81.25	100.00	25.00			100.00	100.00
intr_link_suspend	81.25	100.00	25.00			100.00	100.00
intr_powered	89.58	100.00	58.33			100.00	100.00
intr_rx_bitstuff_err	81.25	100.00	25.00			100.00	100.00
intr_rx_crc_err	81.25	100.00	25.00			100.00	100.00
intr_rx_full	73.06	90.00	22.22			80.00	100.00
intr_rx_pid_err	81.25	100.00	25.00			100.00	100.00
tlul_assert_device	95.24	100.00				85.71	100.00
u_reg	95.88	98.13	96.53	100.00		97.63	87.10
usbdev_avoutfifo	89.34	97.62	70.83			88.89	100.00
usbdev_avsetupfifo	89.34	97.62	70.83			88.89	100.00
usbdev_csr_assert	100.00						100.00
usbdev_impl	80.98	91.70	82.08		46.88	84.22	100.00
usbdev_rxfifo	80.50	90.48	61.54			70.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : usbdev

	Line No.	Total	Covered	Percent
TOTAL		154	149	96.75
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	210	1	1	100.00
ALWAYS	212	5	5	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	253	1	1	100.00
CONT_ASSIGN	254	1	1	100.00
CONT_ASSIGN	256	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	306	1	1	100.00
CONT_ASSIGN	311	1	1	100.00
CONT_ASSIGN	314	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	343	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	345	1	1	100.00
CONT_ASSIGN	346	1	1	100.00
CONT_ASSIGN	350	1	0	0.00
ALWAYS	373	0	0
ALWAYS	373	3	3	100.00
ALWAYS	381	0	0
ALWAYS	381	4	4	100.00
ALWAYS	390	0	0
ALWAYS	390	3	3	100.00
ALWAYS	397	0	0
ALWAYS	397	3	3	100.00
ALWAYS	404	0	0
ALWAYS	404	3	3	100.00
ALWAYS	411	0	0
ALWAYS	411	2	2	100.00
ALWAYS	424	5	5	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	437	1	0	0.00
CONT_ASSIGN	438	1	1	100.00
CONT_ASSIGN	439	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
CONT_ASSIGN	446	1	0	0.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	448	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
ALWAYS	454	3	3	100.00
ALWAYS	461	0	0
ALWAYS	461	3	3	100.00
ALWAYS	470	3	3	100.00
ALWAYS	482	3	3	100.00
ALWAYS	489	0	0
ALWAYS	489	3	3	100.00
ALWAYS	496	10	10	100.00
ALWAYS	515	3	3	100.00
ALWAYS	522	0	0
ALWAYS	522	3	3	100.00
ALWAYS	530	0	0
ALWAYS	530	3	3	100.00
ALWAYS	539	0	0
ALWAYS	539	3	3	100.00
CONT_ASSIGN	549	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	665	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	668	1	1	100.00
CONT_ASSIGN	686	1	1	100.00
CONT_ASSIGN	689	1	1	100.00
ALWAYS	695	0	0
ALWAYS	695	8	8	100.00
CONT_ASSIGN	775	1	1	100.00
CONT_ASSIGN	776	1	1	100.00
CONT_ASSIGN	777	1	1	100.00
CONT_ASSIGN	778	1	1	100.00
CONT_ASSIGN	786	1	1	100.00
ALWAYS	795	8	8	100.00
CONT_ASSIGN	809	1	1	100.00
CONT_ASSIGN	810	0	0
CONT_ASSIGN	813	1	1	100.00
CONT_ASSIGN	814	1	1	100.00
CONT_ASSIGN	871	1	1	100.00
CONT_ASSIGN	872	1	1	100.00
CONT_ASSIGN	876	1	1	100.00
CONT_ASSIGN	1139	1	1	100.00
CONT_ASSIGN	1140	1	1	100.00
CONT_ASSIGN	1141	1	1	100.00
CONT_ASSIGN	1142	1	1	100.00
CONT_ASSIGN	1182	1	1	100.00
CONT_ASSIGN	1185	1	1	100.00
CONT_ASSIGN	1194	1	1	100.00
ALWAYS	1197	5	3	60.00
ALWAYS	1206	3	3	100.00
CONT_ASSIGN	1219	1	1	100.00
CONT_ASSIGN	1222	1	1	100.00
CONT_ASSIGN	1229	1	1	100.00
ALWAYS	1233	3	3	100.00
CONT_ASSIGN	1240	1	1	100.00
CONT_ASSIGN	1245	1	1	100.00
CONT_ASSIGN	1247	1	1	100.00
CONT_ASSIGN	1255	0	0
CONT_ASSIGN	1257	0	0
CONT_ASSIGN	1259	0	0
CONT_ASSIGN	1261	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
123	1	1
210	1	1
212	1	1
213	1	1
215	1	1
216	1	1
218	1	1
247	1	1
248	1	1
249	1	1
253	1	1
254	1	1
256	1	1
258	1	1
306	1	1
311	1	1
314	1	1
317	1	1
342	1	1
343	1	1
344	1	1
345	1	1
346	1	1
350	0	1
373	1	1
374	1	1
375	1	1
381	1	1
382	1	1
383	1	1
384	1	1
390	1	1
391	1	1
392	1	1
397	1	1
398	1	1
399	1	1
404	1	1
405	1	1
406	1	1
411	1	1
412	1	1
424	1	1
425	1	1
426	1	1
428	1	1
429	1	1
432	1	1
433	1	1
437	0	1
438	1	1
439	1	1
441	1	1
446	0	1
447	1	1
448	1	1
450	1	1
454	1	1
455	1	1
456	1	1
			MISSING_ELSE
461	1	1
462	1	1
463	1	1
470	1	1
471	1	1
472	1	1
482	1	1
483	1	1
484	1	1
			MISSING_ELSE
489	1	1
490	1	1
491	1	1
496	1	1
497	1	1
498	1	1
499	1	1
500	1	1
502	1	1
504	1	1
505	1	1
506	1	1
508	1	1
			MISSING_ELSE
515	1	1
516	2	2
			MISSING_ELSE
522	1	1
523	1	1
524	1	1
530	1	1
531	1	1
532	1	1
539	1	1
540	1	1
541	1	1
549	1	1
550	1	1
551	1	1
664	1	1
665	1	1
667	1	1
668	1	1
686	1	1
689	1	1
695	1	1
696	1	1
697	1	1
698	1	1
699	1	1
700	1	1
702	1	1
703	1	1
775	1	1
776	1	1
777	1	1
778	1	1
786	1	1
795	1	1
796	1	1
797	1	1
798	1	1
800	1	1
801	1	1
803	1	1
804	1	1
			MISSING_ELSE
809	1	1
810		unreachable
813	1	1
814	1	1
871	1	1
872	1	1
876	1	1
1139	1	1
1140	1	1
1141	1	1
1142	1	1
1182	1	1
1185	1	1
1194	1	1
1197	1	1
1198	1	1
1199	0	1
1200	1	1
1201	0	1
			MISSING_ELSE
1206	1	1
1207	1	1
1209	1	1
1219	1	1
1222	1	1
1229	1	1
1233	1	1
1234	1	1
1236	1	1
1240	1	1
1245	1	1
1247	1	1
1255		unreachable
1257		unreachable
1259		unreachable
1261		unreachable

---

Cond Coverage for Module : usbdev

	Total	Covered	Percent
Conditions	119	81	68.07
Logical	119	81	68.07
Non-Logical	0	0
Event	0	0

 LINE       210
 EXPRESSION (ns_cnt == 6'd47)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       247
 EXPRESSION (reg2hw.fifo_ctrl.avsetup_rst.qe & reg2hw.fifo_ctrl.avsetup_rst.q)
             ---------------1---------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T43,T44
1	0	Covered	T10,T43,T44
1	1	Covered	T10,T43,T44

 LINE       248
 EXPRESSION (reg2hw.fifo_ctrl.avout_rst.qe & reg2hw.fifo_ctrl.avout_rst.q)
             --------------1--------------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T43,T44
1	0	Covered	T10,T43,T44
1	1	Covered	T10,T43,T44

 LINE       249
 EXPRESSION (reg2hw.fifo_ctrl.rx_rst.qe & reg2hw.fifo_ctrl.rx_rst.q)
             -------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T10,T43,T44
1	1	Not Covered

 LINE       253
 EXPRESSION (connect_en & ((~avsetup_rvalid)))
             -----1----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T10
1	1	Covered	T1,T2,T3

 LINE       254
 EXPRESSION (connect_en & ((~avout_rvalid)))
             -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       256
 EXPRESSION ((reg2hw.avsetupbuffer.qe & ((~avsetup_fifo_wready))) | (reg2hw.avoutbuffer.qe & ((~avout_fifo_wready))))
             --------------------------1-------------------------   ------------------------2-----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       256
 SUB-EXPRESSION (reg2hw.avsetupbuffer.qe & ((~avsetup_fifo_wready)))
                 -----------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T10
1	1	Not Covered

 LINE       256
 SUB-EXPRESSION (reg2hw.avoutbuffer.qe & ((~avout_fifo_wready)))
                 ----------1----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       258
 EXPRESSION (connect_en & ((~rx_fifo_rvalid)))
             -----1----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

 LINE       306
 EXPRESSION (reg2hw.rxfifo.ep.re | reg2hw.rxfifo.setup.re | reg2hw.rxfifo.size.re | reg2hw.rxfifo.buffer.re)
             ---------1---------   -----------2----------   ----------3----------   -----------4-----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Not Covered

 LINE       317
 EXPRESSION (rx_wready & (rx_depth < 4'((RXFifoDepth - 1))))
             ----1----   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       432
 EXPRESSION (in_xact_starting ? in_buf[in_xact_start_ep] : in_buf_q)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T9

 LINE       433
 EXPRESSION (in_xact_starting ? in_size[in_xact_start_ep] : in_size_q)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T9

 LINE       437
 EXPRESSION (reg2hw.out_data_toggle.status.qe & reg2hw.out_data_toggle.mask.qe)
             ----------------1---------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       446
 EXPRESSION (reg2hw.in_data_toggle.status.qe & reg2hw.in_data_toggle.mask.qe)
             ---------------1---------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       455
 EXPRESSION (in_ep_xact_end && in_endpoint_val)
             -------1------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T5,T9

 LINE       483
 EXPRESSION (rx_wvalid && out_endpoint_val)
             ----1----    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T5

 LINE       502
 EXPRESSION (setup_received & out_endpoint_val)
             -------1------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T5,T12

 LINE       506
 EXPRESSION (in_ep_xact_end & in_endpoint_val)
             -------1------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T5,T9

 LINE       532
 EXPRESSION (reg2hw.configin[i].rdy.q | reg2hw.configin[i].pend.q)
             ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T22,T23
1	0	Covered	T1,T5,T9

 LINE       540
 EXPRESSION (set_sending[i] | set_sentbit[i] | update_pend[i])
             -------1------   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T5,T9
1	0	0	Covered	T1,T5,T9

 LINE       541
 EXPRESSION (((~set_sentbit[i])) & ((~update_pend[i])))
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       550
 EXPRESSION (cfg_pinflip ? 1'b0 : usb_pullup_en)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       551
 EXPRESSION (((!cfg_pinflip)) ? 1'b0 : usb_pullup_en)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       668
 EXPRESSION (reg2hw.usbctrl.resume_link_active.qe & reg2hw.usbctrl.resume_link_active.q)
             ------------------1-----------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       775
 EXPRESSION (usb_mem_b_req | sw_mem_a_req)
             ------1------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T32
1	0	Covered	T1,T3,T5

 LINE       776
 EXPRESSION (usb_mem_b_req ? usb_mem_b_write : sw_mem_a_write)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       777
 EXPRESSION (usb_mem_b_req ? usb_mem_b_addr : sw_mem_a_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       778
 EXPRESSION (usb_mem_b_req ? usb_mem_b_wdata : sw_mem_a_wdata)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       801
 EXPRESSION (usb_mem_b_req & ((!usb_mem_b_write)))
             ------1------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T5,T9

 LINE       809
 EXPRESSION (gen_no_stubbed_memory.mem_rvalid & ((!gen_no_stubbed_memory.mem_rsteering)))
             ----------------1---------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T9
1	1	Covered	T1,T5,T32

 LINE       814
 EXPRESSION (gen_no_stubbed_memory.mem_b_read_q ? gen_no_stubbed_memory.mem_rdata : gen_no_stubbed_memory.mem_b_rdata_q)
             -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T9

 LINE       876
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       1185
 EXPRESSION (use_diff_rcvr & ((~link_suspend)))
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       1194
 EXPRESSION (usb_rcvr_ok_counter_q == '0)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1198
 EXPRESSION (use_diff_rcvr & ((!usb_rx_enable_o)))
             ------1------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       1200
 EXPRESSION (us_tick && (usb_rcvr_ok_counter_q > '0))
             ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       1222
 EXPRESSION (usb_ref_disable ? 1'b0 : event_sof)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       1229
 EXPRESSION (usb_ref_pulse_o ? 1'b1 : ((((!link_active)) || host_lost || usb_ref_disable) ? 1'b0 : usb_ref_val_q))
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       1229
 SUB-EXPRESSION ((((!link_active)) || host_lost || usb_ref_disable) ? 1'b0 : usb_ref_val_q)
                 -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1229
 SUB-EXPRESSION (((!link_active)) || host_lost || usb_ref_disable)
                 --------1-------    ----2----    -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Covered	T1,T2,T3

 LINE       1245
 EXPRESSION (reg2hw.wake_control.suspend_req.qe & reg2hw.wake_control.suspend_req.q)
             -----------------1----------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1247
 EXPRESSION (reg2hw.wake_control.wake_ack.qe & reg2hw.wake_control.wake_ack.q)
             ---------------1---------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Toggle Coverage for Module : usbdev

	Total	Covered	Percent
Totals	68	61	89.71
Total Bits	428	402	93.93
Total Bits 0->1	214	201	93.93
Total Bits 1->0	214	201	93.93

Ports	68	61	89.71
Port Bits	428	402	93.93
Port Bits 0->1	214	201	93.93
Port Bits 1->0	214	201	93.93

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
clk_aon_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_aon_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T7,T11	Yes	T3,T7,T11	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T3,T5,T7	Yes	T1,T3,T5	INPUT
tl_i.a_source[7:0]	Yes	Yes	T3,T5,T7	Yes	T3,T5,T7	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T45,T46,T47	Yes	T45,T46,T47	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T5,T7	Yes	T1,T5,T6	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	OUTPUT
cio_usb_dp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_usb_dn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
usb_rx_d_i	No	No		No		INPUT
cio_usb_dp_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cio_usb_dp_en_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cio_usb_dn_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cio_usb_dn_en_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
usb_tx_se0_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
usb_tx_d_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cio_sense_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
usb_dp_pullup_o	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
usb_dn_pullup_o	Yes	Yes	T51,T52	Yes	T51,T52	OUTPUT
usb_rx_enable_o	Yes	Yes	T46,T53,T54	Yes	T46,T53,T55	OUTPUT
usb_tx_use_d_se0_o	Yes	Yes	T46,T56,T54	Yes	T46,T56,T54	OUTPUT
usb_aon_suspend_req_o	Yes	Yes	T57,T58,T59	Yes	T57,T58,T59	OUTPUT
usb_aon_wake_ack_o	Yes	Yes	T46,T53,T55	Yes	T46,T53,T55	OUTPUT
usb_aon_bus_reset_i	Unreachable	Unreachable		Unreachable		INPUT
usb_aon_sense_lost_i	Unreachable	Unreachable		Unreachable		INPUT
usb_aon_bus_not_idle_i	Unreachable	Unreachable		Unreachable		INPUT
usb_aon_wake_detect_active_i	Unreachable	Unreachable		Unreachable		INPUT
usb_ref_val_o	No	No		No		OUTPUT
usb_ref_pulse_o	No	No		No		OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
intr_pkt_received_o	Yes	Yes	T1,T5,T12	Yes	T1,T5,T12	OUTPUT
intr_pkt_sent_o	Yes	Yes	T9,T19,T20	Yes	T9,T19,T20	OUTPUT
intr_powered_o	Yes	Yes	T60,T46,T61	Yes	T60,T46,T61	OUTPUT
intr_disconnected_o	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
intr_host_lost_o	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
intr_link_reset_o	Yes	Yes	T60,T46,T62	Yes	T60,T46,T62	OUTPUT
intr_link_suspend_o	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
intr_link_resume_o	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
intr_av_out_empty_o	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
intr_rx_full_o	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
intr_av_overflow_o	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
intr_link_in_err_o	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
intr_link_out_err_o	Yes	Yes	T60,T63,T57	Yes	T60,T63,T57	OUTPUT
intr_rx_crc_err_o	Yes	Yes	T60,T62,T65	Yes	T60,T62,T65	OUTPUT
intr_rx_pid_err_o	Yes	Yes	T60,T63,T66	Yes	T60,T63,T66	OUTPUT
intr_rx_bitstuff_err_o	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
intr_frame_o	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
intr_av_setup_empty_o	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : usbdev

	Line No.	Total	Covered	Percent
Branches		48	42	87.50
TERNARY	432	2	2	100.00
TERNARY	433	2	2	100.00
TERNARY	550	2	1	50.00
TERNARY	551	2	1	50.00
TERNARY	1222	2	1	50.00
TERNARY	1229	3	2	66.67
TERNARY	776	2	2	100.00
TERNARY	777	2	2	100.00
TERNARY	778	2	2	100.00
TERNARY	814	2	2	100.00
IF	212	3	3	100.00
IF	424	2	2	100.00
IF	455	2	2	100.00
IF	483	2	2	100.00
IF	498	4	4	100.00
IF	516	2	2	100.00
IF	698	2	2	100.00
IF	1198	3	1	33.33
IF	1206	2	2	100.00
IF	1233	2	2	100.00
IF	795	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	432	(in_xact_starting) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	433	(in_xact_starting) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	550	(cfg_pinflip) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	551	((!cfg_pinflip)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	1222	(usb_ref_disable) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1229	(usb_ref_pulse_o) ? 
-2-:	1229	((((!link_active) || host_lost) || usb_ref_disable)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	776	(usb_mem_b_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	777	(usb_mem_b_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	778	(usb_mem_b_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	814	(gen_no_stubbed_memory.mem_b_read_q) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	212	if ((!rst_n))
-2-:	215	if (us_tick)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	424	if ((!rst_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	455	if ((in_ep_xact_end && in_endpoint_val))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	483	if ((rx_wvalid && out_endpoint_val))

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	498	if (event_link_reset)
-2-:	502	if ((setup_received & out_endpoint_val))
-3-:	506	if ((in_ep_xact_end & in_endpoint_val))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T5,T12
0	0	1	Covered	T1,T5,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	516	if (in_xact_starting)

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	698	if (((setup_received && out_endpoint_val) && (out_endpoint == 4'((unsigned'(i))))))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1198	if ((use_diff_rcvr & (!usb_rx_enable_o)))
-2-:	1200	if ((us_tick && (usb_rcvr_ok_counter_q > '0)))

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1206	if ((!rst_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1233	if ((!rst_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	795	if ((!rst_ni))
-2-:	803	if (gen_no_stubbed_memory.mem_b_read_q)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T5,T9
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : usbdev

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	35	35	100.00	35	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	35	35	100.00	35	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertsKnown_A	238170803	238073777	0	0
CIODnEnKnown_A	238170803	238073777	0	0
CIODnKnown_A	238170803	238073777	0	0
CIODpEnKnown_A	238170803	238073777	0	0
CIODpKnown_A	238170803	238073777	0	0
FpvSecCmRegWeOnehotCheck_A	238170803	60	0	0
TlOAReadyKnown_A	238170803	238073777	0	0
TlODValidKnown_A	238170803	238073777	0	0
USBAonSuspendReqKnown_A	238170803	238073777	0	0
USBAonWakeAckKnown_A	238170803	238073777	0	0
USBDnPUKnown_A	238170803	238073777	0	0
USBDpPUKnown_A	238170803	238073777	0	0
USBIntrAvOutEmptyKnown_A	238170803	238073777	0	0
USBIntrAvOverKnown_A	238170803	238073777	0	0
USBIntrAvSetupEmptyKnown_A	238170803	238073777	0	0
USBIntrDisConKnown_A	238170803	238073777	0	0
USBIntrFrameKnown_A	238170803	238073777	0	0
USBIntrHostLostKnown_A	238170803	238073777	0	0
USBIntrLinkInErrKnown_A	238170803	238073777	0	0
USBIntrLinkOutErrKnown_A	238170803	238073777	0	0
USBIntrLinkResKnown_A	238170803	238073777	0	0
USBIntrLinkRstKnown_A	238170803	238073777	0	0
USBIntrLinkSusKnown_A	238170803	238073777	0	0
USBIntrPktRcvdKnown_A	238170803	238073777	0	0
USBIntrPktSentKnown_A	238170803	238073777	0	0
USBIntrPwrdKnown_A	238170803	238073777	0	0
USBIntrRxBitstuffErrKnown_A	238170803	238073777	0	0
USBIntrRxCrCErrKnown_A	238170803	238073777	0	0
USBIntrRxFullKnown_A	238170803	238073777	0	0
USBIntrRxPidErrKnown_A	238170803	238073777	0	0
USBRefPulseKnown_A	238170803	238073777	0	0
USBRefValKnown_A	238170803	238073777	0	0
USBRxEnableKnown_A	238170803	238073777	0	0
USBTxDKnown_A	238170803	238073777	0	0
USBTxSe0Known_A	238170803	238073777	0	0

AlertsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238170803	238073777	0	0
T1	406890	406698	0	0
T2	402104	401970	0	0
T3	401528	401465	0	0
T4	1298	1167	0	0
T5	406609	406362	0	0
T6	401468	401416	0	0
T7	404742	404610	0	0
T8	403339	403179	0	0
T9	403549	403401	0	0
T10	13556	13496	0	0

CIODnEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238170803	238073777	0	0
T1	406890	406698	0	0
T2	402104	401970	0	0
T3	401528	401465	0	0
T4	1298	1167	0	0
T5	406609	406362	0	0
T6	401468	401416	0	0
T7	404742	404610	0	0
T8	403339	403179	0	0
T9	403549	403401	0	0
T10	13556	13496	0	0

CIODnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238170803	238073777	0	0
T1	406890	406698	0	0
T2	402104	401970	0	0
T3	401528	401465	0	0
T4	1298	1167	0	0
T5	406609	406362	0	0
T6	401468	401416	0	0
T7	404742	404610	0	0
T8	403339	403179	0	0
T9	403549	403401	0	0
T10	13556	13496	0	0

CIODpEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238170803	238073777	0	0
T1	406890	406698	0	0
T2	402104	401970	0	0
T3	401528	401465	0	0
T4	1298	1167	0	0
T5	406609	406362	0	0
T6	401468	401416	0	0
T7	404742	404610	0	0
T8	403339	403179	0	0
T9	403549	403401	0	0
T10	13556	13496	0	0

CIODpKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238170803	238073777	0	0
T1	406890	406698	0	0
T2	402104	401970	0	0
T3	401528	401465	0	0
T4	1298	1167	0	0
T5	406609	406362	0	0
T6	401468	401416	0	0
T7	404742	404610	0	0
T8	403339	403179	0	0
T9	403549	403401	0	0
T10	13556	13496	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238170803	60	0	0
T48	5100	10	0	0
T49	0	10	0	0
T50	0	20	0	0
T67	0	10	0	0
T68	0	10	0	0
T69	8684	0	0	0
T70	401429	0	0	0
T71	407023	0	0	0
T72	401577	0	0	0
T73	401164	0	0	0
T74	1280	0	0	0
T75	401838	0	0	0
T76	401152	0	0	0
T77	403503	0	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238170803	238073777	0	0
T1	406890	406698	0	0
T2	402104	401970	0	0
T3	401528	401465	0	0
T4	1298	1167	0	0
T5	406609	406362	0	0
T6	401468	401416	0	0
T7	404742	404610	0	0
T8	403339	403179	0	0
T9	403549	403401	0	0
T10	13556	13496	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238170803	238073777	0	0
T1	406890	406698	0	0
T2	402104	401970	0	0
T3	401528	401465	0	0
T4	1298	1167	0	0
T5	406609	406362	0	0
T6	401468	401416	0	0
T7	404742	404610	0	0
T8	403339	403179	0	0
T9	403549	403401	0	0
T10	13556	13496	0	0

USBAonSuspendReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238170803	238073777	0	0
T1	406890	406698	0	0
T2	402104	401970	0	0
T3	401528	401465	0	0
T4	1298	1167	0	0
T5	406609	406362	0	0
T6	401468	401416	0	0
T7	404742	404610	0	0
T8	403339	403179	0	0
T9	403549	403401	0	0
T10	13556	13496	0	0

USBAonWakeAckKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238170803	238073777	0	0
T1	406890	406698	0	0
T2	402104	401970	0	0
T3	401528	401465	0	0
T4	1298	1167	0	0
T5	406609	406362	0	0
T6	401468	401416	0	0
T7	404742	404610	0	0
T8	403339	403179	0	0
T9	403549	403401	0	0
T10	13556	13496	0	0

USBDnPUKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238170803	238073777	0	0
T1	406890	406698	0	0
T2	402104	401970	0	0
T3	401528	401465	0	0
T4	1298	1167	0	0
T5	406609	406362	0	0
T6	401468	401416	0	0
T7	404742	404610	0	0
T8	403339	403179	0	0
T9	403549	403401	0	0
T10	13556	13496	0	0

USBDpPUKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238170803	238073777	0	0
T1	406890	406698	0	0
T2	402104	401970	0	0
T3	401528	401465	0	0
T4	1298	1167	0	0
T5	406609	406362	0	0
T6	401468	401416	0	0
T7	404742	404610	0	0
T8	403339	403179	0	0
T9	403549	403401	0	0
T10	13556	13496	0	0

USBIntrAvOutEmptyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238170803	238073777	0	0
T1	406890	406698	0	0
T2	402104	401970	0	0
T3	401528	401465	0	0
T4	1298	1167	0	0
T5	406609	406362	0	0
T6	401468	401416	0	0
T7	404742	404610	0	0
T8	403339	403179	0	0
T9	403549	403401	0	0
T10	13556	13496	0	0

USBIntrAvOverKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238170803	238073777	0	0
T1	406890	406698	0	0
T2	402104	401970	0	0
T3	401528	401465	0	0
T4	1298	1167	0	0
T5	406609	406362	0	0
T6	401468	401416	0	0
T7	404742	404610	0	0
T8	403339	403179	0	0
T9	403549	403401	0	0
T10	13556	13496	0	0

USBIntrAvSetupEmptyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238170803	238073777	0	0
T1	406890	406698	0	0
T2	402104	401970	0	0
T3	401528	401465	0	0
T4	1298	1167	0	0
T5	406609	406362	0	0
T6	401468	401416	0	0
T7	404742	404610	0	0
T8	403339	403179	0	0
T9	403549	403401	0	0
T10	13556	13496	0	0

USBIntrDisConKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238170803	238073777	0	0
T1	406890	406698	0	0
T2	402104	401970	0	0
T3	401528	401465	0	0
T4	1298	1167	0	0
T5	406609	406362	0	0
T6	401468	401416	0	0
T7	404742	404610	0	0
T8	403339	403179	0	0
T9	403549	403401	0	0
T10	13556	13496	0	0

USBIntrFrameKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238170803	238073777	0	0
T1	406890	406698	0	0
T2	402104	401970	0	0
T3	401528	401465	0	0
T4	1298	1167	0	0
T5	406609	406362	0	0
T6	401468	401416	0	0
T7	404742	404610	0	0
T8	403339	403179	0	0
T9	403549	403401	0	0
T10	13556	13496	0	0

USBIntrHostLostKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238170803	238073777	0	0
T1	406890	406698	0	0
T2	402104	401970	0	0
T3	401528	401465	0	0
T4	1298	1167	0	0
T5	406609	406362	0	0
T6	401468	401416	0	0
T7	404742	404610	0	0
T8	403339	403179	0	0
T9	403549	403401	0	0
T10	13556	13496	0	0

USBIntrLinkInErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238170803	238073777	0	0
T1	406890	406698	0	0
T2	402104	401970	0	0
T3	401528	401465	0	0
T4	1298	1167	0	0
T5	406609	406362	0	0
T6	401468	401416	0	0
T7	404742	404610	0	0
T8	403339	403179	0	0
T9	403549	403401	0	0
T10	13556	13496	0	0

USBIntrLinkOutErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238170803	238073777	0	0
T1	406890	406698	0	0
T2	402104	401970	0	0
T3	401528	401465	0	0
T4	1298	1167	0	0
T5	406609	406362	0	0
T6	401468	401416	0	0
T7	404742	404610	0	0
T8	403339	403179	0	0
T9	403549	403401	0	0
T10	13556	13496	0	0

USBIntrLinkResKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238170803	238073777	0	0
T1	406890	406698	0	0
T2	402104	401970	0	0
T3	401528	401465	0	0
T4	1298	1167	0	0
T5	406609	406362	0	0
T6	401468	401416	0	0
T7	404742	404610	0	0
T8	403339	403179	0	0
T9	403549	403401	0	0
T10	13556	13496	0	0

USBIntrLinkRstKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238170803	238073777	0	0
T1	406890	406698	0	0
T2	402104	401970	0	0
T3	401528	401465	0	0
T4	1298	1167	0	0
T5	406609	406362	0	0
T6	401468	401416	0	0
T7	404742	404610	0	0
T8	403339	403179	0	0
T9	403549	403401	0	0
T10	13556	13496	0	0

USBIntrLinkSusKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238170803	238073777	0	0
T1	406890	406698	0	0
T2	402104	401970	0	0
T3	401528	401465	0	0
T4	1298	1167	0	0
T5	406609	406362	0	0
T6	401468	401416	0	0
T7	404742	404610	0	0
T8	403339	403179	0	0
T9	403549	403401	0	0
T10	13556	13496	0	0

USBIntrPktRcvdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238170803	238073777	0	0
T1	406890	406698	0	0
T2	402104	401970	0	0
T3	401528	401465	0	0
T4	1298	1167	0	0
T5	406609	406362	0	0
T6	401468	401416	0	0
T7	404742	404610	0	0
T8	403339	403179	0	0
T9	403549	403401	0	0
T10	13556	13496	0	0

USBIntrPktSentKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238170803	238073777	0	0
T1	406890	406698	0	0
T2	402104	401970	0	0
T3	401528	401465	0	0
T4	1298	1167	0	0
T5	406609	406362	0	0
T6	401468	401416	0	0
T7	404742	404610	0	0
T8	403339	403179	0	0
T9	403549	403401	0	0
T10	13556	13496	0	0

USBIntrPwrdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238170803	238073777	0	0
T1	406890	406698	0	0
T2	402104	401970	0	0
T3	401528	401465	0	0
T4	1298	1167	0	0
T5	406609	406362	0	0
T6	401468	401416	0	0
T7	404742	404610	0	0
T8	403339	403179	0	0
T9	403549	403401	0	0
T10	13556	13496	0	0

USBIntrRxBitstuffErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238170803	238073777	0	0
T1	406890	406698	0	0
T2	402104	401970	0	0
T3	401528	401465	0	0
T4	1298	1167	0	0
T5	406609	406362	0	0
T6	401468	401416	0	0
T7	404742	404610	0	0
T8	403339	403179	0	0
T9	403549	403401	0	0
T10	13556	13496	0	0

USBIntrRxCrCErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238170803	238073777	0	0
T1	406890	406698	0	0
T2	402104	401970	0	0
T3	401528	401465	0	0
T4	1298	1167	0	0
T5	406609	406362	0	0
T6	401468	401416	0	0
T7	404742	404610	0	0
T8	403339	403179	0	0
T9	403549	403401	0	0
T10	13556	13496	0	0

USBIntrRxFullKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238170803	238073777	0	0
T1	406890	406698	0	0
T2	402104	401970	0	0
T3	401528	401465	0	0
T4	1298	1167	0	0
T5	406609	406362	0	0
T6	401468	401416	0	0
T7	404742	404610	0	0
T8	403339	403179	0	0
T9	403549	403401	0	0
T10	13556	13496	0	0

USBIntrRxPidErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238170803	238073777	0	0
T1	406890	406698	0	0
T2	402104	401970	0	0
T3	401528	401465	0	0
T4	1298	1167	0	0
T5	406609	406362	0	0
T6	401468	401416	0	0
T7	404742	404610	0	0
T8	403339	403179	0	0
T9	403549	403401	0	0
T10	13556	13496	0	0

USBRefPulseKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238170803	238073777	0	0
T1	406890	406698	0	0
T2	402104	401970	0	0
T3	401528	401465	0	0
T4	1298	1167	0	0
T5	406609	406362	0	0
T6	401468	401416	0	0
T7	404742	404610	0	0
T8	403339	403179	0	0
T9	403549	403401	0	0
T10	13556	13496	0	0

USBRefValKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238170803	238073777	0	0
T1	406890	406698	0	0
T2	402104	401970	0	0
T3	401528	401465	0	0
T4	1298	1167	0	0
T5	406609	406362	0	0
T6	401468	401416	0	0
T7	404742	404610	0	0
T8	403339	403179	0	0
T9	403549	403401	0	0
T10	13556	13496	0	0

USBRxEnableKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238170803	238073777	0	0
T1	406890	406698	0	0
T2	402104	401970	0	0
T3	401528	401465	0	0
T4	1298	1167	0	0
T5	406609	406362	0	0
T6	401468	401416	0	0
T7	404742	404610	0	0
T8	403339	403179	0	0
T9	403549	403401	0	0
T10	13556	13496	0	0

USBTxDKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238170803	238073777	0	0
T1	406890	406698	0	0
T2	402104	401970	0	0
T3	401528	401465	0	0
T4	1298	1167	0	0
T5	406609	406362	0	0
T6	401468	401416	0	0
T7	404742	404610	0	0
T8	403339	403179	0	0
T9	403549	403401	0	0
T10	13556	13496	0	0

USBTxSe0Known_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238170803	238073777	0	0
T1	406890	406698	0	0
T2	402104	401970	0	0
T3	401528	401465	0	0
T4	1298	1167	0	0
T5	406609	406362	0	0
T6	401468	401416	0	0
T7	404742	404610	0	0
T8	403339	403179	0	0
T9	403549	403401	0	0
T10	13556	13496	0	0