USBDEV Simulation Results

Thursday March 28 2024 19:02:20 UTC

GitHub Revision: 4ee21f808f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29834210046083588839632889378999422318513504283488100050460647435812066910143

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 10.170s 8.438ms 50 50 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 0.870s 56.153us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.030s 59.546us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 6.640s 275.441us 2 5 40.00
V1 csr_aliasing usbdev_csr_aliasing 3.440s 371.342us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.600s 78.071us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.030s 59.546us 20 20 100.00
usbdev_csr_aliasing 3.440s 371.342us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.020s 148.691us 3 5 60.00
V1 mem_partial_access usbdev_mem_partial_access 2.320s 181.881us 5 5 100.00
V1 TOTAL 110 115 95.65
V2 in_trans usbdev_in_trans 9.640s 8.378ms 50 50 100.00
V2 data_toggle_clear data_toggle_clear 0 0 --
V2 phy_pins_sense usbdev_phy_pins_sense 0.730s 24.150us 50 50 100.00
V2 av_buffer usbdev_av_buffer 9.680s 8.371ms 50 50 100.00
V2 rx_fifo rx_fifo 0 0 --
V2 phy_config_tx_osc_test_mode phy_config_tx_osc_test_mode 0 0 --
V2 phy_config_eop_single_bit_handling phy_config_eop_single_bit_handling 0 0 --
V2 phy_config_pinflip phy_config_pinflip 0 0 --
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 0 0 --
V2 max_length_out_transaction usbdev_max_length_out_transaction 10.100s 8.410ms 50 50 100.00
V2 max_length_in_transaction max_length_in_transaction 0 0 --
V2 min_length_out_transaction usbdev_min_length_out_transaction 9.570s 8.360ms 50 50 100.00
V2 min_length_in_transaction min_length_in_transaction 0 0 --
V2 random_length_out_trans usbdev_random_length_out_trans 9.630s 8.408ms 50 50 100.00
V2 random_length_in_trans random_length_in_trans 0 0 --
V2 out_stall usbdev_out_stall 9.920s 8.380ms 50 50 100.00
V2 in_stall usbdev_in_stall 9.830s 8.366ms 50 50 100.00
V2 out_iso out_iso 0 0 --
V2 in_iso in_iso 0 0 --
V2 pkt_received usbdev_pkt_received 9.960s 8.383ms 50 50 100.00
V2 pkt_sent usbdev_pkt_sent 9.530s 8.418ms 50 50 100.00
V2 disconnected disconnected 0 0 --
V2 host_lost host_lost 0 0 --
V2 link_reset link_reset 0 0 --
V2 link_suspend link_suspend 0 0 --
V2 link_resume link_resume 0 0 --
V2 av_empty av_empty 0 0 --
V2 rx_full rx_full 0 0 --
V2 av_overflow av_overflow 0 0 --
V2 link_in_err link_in_err 0 0 --
V2 rx_crc_err rx_crc_err 0 0 --
V2 rx_pid_err rx_pid_err 0 0 --
V2 rx_bitstuff_err rx_bitstuff_err 0 0 --
V2 link_out_err link_out_err 0 0 --
V2 enable usbdev_enable 10.120s 8.375ms 50 50 100.00
V2 resume_link_active resume_link_active 0 0 --
V2 device_address device_address 0 0 --
V2 invalid_data1_data0_toggle_test invalid_data1_data0_toggle_test 0 0 --
V2 setup_stage setup_stage 0 0 --
V2 in_data_stage in_data_stage 0 0 --
V2 out_data_stage out_data_stage 0 0 --
V2 endpoint_access endpoint_access 0 0 --
V2 disable_endpoint disable_endpoint 0 0 --
V2 out_trans_nak usbdev_out_trans_nak 10.220s 8.384ms 50 50 100.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 9.870s 8.362ms 50 50 100.00
V2 nak_trans usbdev_nak_trans 9.750s 8.399ms 48 50 96.00
V2 stall_trans stall_trans 0 0 --
V2 setup_priority_over_stall_response setup_priority_over_stall_response 0 0 --
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 9.940s 8.407ms 50 50 100.00
V2 pending_in_trans pending_in_trans 0 0 --
V2 streaming_test streaming_test 0 0 --
V2 max_clock_error_untracked max_clock_error_untracked 0 0 --
V2 max_clock_error_tracking max_clock_error_tracking 0 0 --
V2 max_phase_error max_phase_error 0 0 --
V2 min_inter_pkt_delay min_inter_pkt_delay 0 0 --
V2 max_inter_pkt_delay max_inter_pkt_delay 0 0 --
V2 device_timeout_missing_host_handshake device_timeout_missing_host_handshake 0 0 --
V2 device_timeout device_timeout 0 0 --
V2 packet_buffer usbdev_pkt_buffer 1.179m 30.862ms 50 50 100.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full nak_to_out_trans_when_avbuffer_empty_rxfifo_full 0 0 --
V2 aon_wake_resume aon_wake_resume 0 0 --
V2 aon_wake_reset aon_wake_reset 0 0 --
V2 aon_wake_disconnect aon_wake_disconnect 0 0 --
V2 invalid_sync invalid_sync 0 0 --
V2 spurious_tokens_ignored spurious_tokens_ignored 0 0 --
V2 low_speed_traffic low_speed_traffic 0 0 --
V2 rand_bus_resets rand_bus_resets 0 0 --
V2 rand_disconnects rand_disconnects 0 0 --
V2 max_usb_traffic max_usb_traffic 0 0 --
V2 stress_usb_traffic stress_usb_traffic 0 0 --
V2 in_packet_retraction in_packet_retraction 0 0 --
V2 data_toggle_restore data_toggle_restore 0 0 --
V2 setup_priority setup_priority 0 0 --
V2 fifo_resets usbdev_fifo_rst 2.320s 283.479us 50 50 100.00
V2 intr_test usbdev_intr_test 0.750s 21.302us 36 50 72.00
V2 alert_test usbdev_alert_test 0 0 --
V2 tl_d_oob_addr_access usbdev_tl_errors 3.580s 336.623us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.580s 336.623us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 0.870s 56.153us 5 5 100.00
usbdev_csr_rw 1.030s 59.546us 20 20 100.00
usbdev_csr_aliasing 3.440s 371.342us 5 5 100.00
usbdev_same_csr_outstanding 1.620s 151.961us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 0.870s 56.153us 5 5 100.00
usbdev_csr_rw 1.030s 59.546us 20 20 100.00
usbdev_csr_aliasing 3.440s 371.342us 5 5 100.00
usbdev_same_csr_outstanding 1.620s 151.961us 20 20 100.00
V2 TOTAL 924 940 98.30
V2S tl_intg_err usbdev_sec_cm 1.070s 163.706us 5 5 100.00
usbdev_tl_intg_err 4.910s 439.747us 15 20 75.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 4.910s 439.747us 15 20 75.00
V2S TOTAL 20 25 80.00
V3 TOTAL 0 0 --
Unmapped tests phy_config_usb_ref_disable 9.030s 8.364ms 49 50 98.00
in_iso 9.470s 8.424ms 50 50 100.00
usbdev_stress_all_with_rand_reset 0.700s 2.596us 0 50 0.00
usbdev_stress_all 0.630s 0 50 0.00
TOTAL 1103 1230 89.67

Testplan Progress

Items Total Written Passing Progress
N.A. 3 3 0 0.00
V1 8 8 6 75.00
V2 78 20 18 23.08
V2S 2 2 1 50.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
88.75 96.43 89.11 97.62 50.00 94.13 97.36 96.58

Failure Buckets

Past Results