1fbe1ece8d| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | usbdev_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | usbdev_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | usbdev_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | usbdev_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | usbdev_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | usbdev_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | usbdev_csr_rw | 0 | 20 | 0.00 | ||
| usbdev_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | mem_walk | usbdev_mem_walk | 0 | 5 | 0.00 | ||
| V1 | mem_partial_access | usbdev_mem_partial_access | 0 | 5 | 0.00 | ||
| V1 | TOTAL | 0 | 115 | 0.00 | |||
| V2 | in_trans | usbdev_in_trans | 0 | 50 | 0.00 | ||
| V2 | data_toggle_clear | data_toggle_clear | 0 | 0 | -- | ||
| V2 | phy_pins_sense | usbdev_phy_pins_sense | 0 | 50 | 0.00 | ||
| V2 | av_buffer | usbdev_av_buffer | 0 | 50 | 0.00 | ||
| V2 | rx_fifo | rx_fifo | 0 | 0 | -- | ||
| V2 | phy_config_tx_osc_test_mode | phy_config_tx_osc_test_mode | 0 | 0 | -- | ||
| V2 | phy_config_eop_single_bit_handling | phy_config_eop_single_bit_handling | 0 | 0 | -- | ||
| V2 | phy_config_pinflip | phy_config_pinflip | 0 | 0 | -- | ||
| V2 | phy_config_usb_ref_disable | usbdev_phy_config_usb_ref_disable | 0 | 50 | 0.00 | ||
| V2 | max_length_out_transaction | usbdev_max_length_out_transaction | 0 | 50 | 0.00 | ||
| V2 | max_length_in_transaction | max_length_in_transaction | 0 | 0 | -- | ||
| V2 | min_length_out_transaction | usbdev_min_length_out_transaction | 0 | 50 | 0.00 | ||
| V2 | min_length_in_transaction | min_length_in_transaction | 0 | 0 | -- | ||
| V2 | random_length_out_trans | usbdev_random_length_out_trans | 0 | 50 | 0.00 | ||
| V2 | random_length_in_trans | random_length_in_trans | 0 | 0 | -- | ||
| V2 | out_stall | usbdev_out_stall | 0 | 50 | 0.00 | ||
| V2 | in_stall | usbdev_in_stall | 0 | 50 | 0.00 | ||
| V2 | out_iso | out_iso | 0 | 0 | -- | ||
| V2 | in_iso | in_iso | 0 | 0 | -- | ||
| V2 | pkt_received | usbdev_pkt_received | 0 | 50 | 0.00 | ||
| V2 | pkt_sent | usbdev_pkt_sent | 0 | 50 | 0.00 | ||
| V2 | disconnected | disconnected | 0 | 0 | -- | ||
| V2 | host_lost | host_lost | 0 | 0 | -- | ||
| V2 | link_reset | link_reset | 0 | 0 | -- | ||
| V2 | link_suspend | link_suspend | 0 | 0 | -- | ||
| V2 | link_resume | link_resume | 0 | 0 | -- | ||
| V2 | av_empty | av_empty | 0 | 0 | -- | ||
| V2 | rx_full | rx_full | 0 | 0 | -- | ||
| V2 | av_overflow | av_overflow | 0 | 0 | -- | ||
| V2 | link_in_err | link_in_err | 0 | 0 | -- | ||
| V2 | rx_crc_err | rx_crc_err | 0 | 0 | -- | ||
| V2 | rx_pid_err | rx_pid_err | 0 | 0 | -- | ||
| V2 | rx_bitstuff_err | rx_bitstuff_err | 0 | 0 | -- | ||
| V2 | link_out_err | link_out_err | 0 | 0 | -- | ||
| V2 | enable | usbdev_enable | 0 | 50 | 0.00 | ||
| V2 | resume_link_active | resume_link_active | 0 | 0 | -- | ||
| V2 | device_address | device_address | 0 | 0 | -- | ||
| V2 | invalid_data1_data0_toggle_test | invalid_data1_data0_toggle_test | 0 | 0 | -- | ||
| V2 | setup_stage | setup_stage | 0 | 0 | -- | ||
| V2 | in_data_stage | in_data_stage | 0 | 0 | -- | ||
| V2 | out_data_stage | out_data_stage | 0 | 0 | -- | ||
| V2 | endpoint_access | endpoint_access | 0 | 0 | -- | ||
| V2 | disable_endpoint | disable_endpoint | 0 | 0 | -- | ||
| V2 | out_trans_nak | usbdev_out_trans_nak | 0 | 50 | 0.00 | ||
| V2 | setup_trans_ignored | usbdev_setup_trans_ignored | 0 | 50 | 0.00 | ||
| V2 | nak_trans | usbdev_nak_trans | 0 | 50 | 0.00 | ||
| V2 | stall_trans | usbdev_stall_trans | 0 | 50 | 0.00 | ||
| V2 | setup_priority_over_stall_response | setup_priority_over_stall_response | 0 | 0 | -- | ||
| V2 | stall_priority_over_nak | usbdev_stall_priority_over_nak | 0 | 50 | 0.00 | ||
| V2 | pending_in_trans | pending_in_trans | 0 | 0 | -- | ||
| V2 | streaming_test | streaming_test | 0 | 0 | -- | ||
| V2 | max_clock_error_untracked | max_clock_error_untracked | 0 | 0 | -- | ||
| V2 | max_clock_error_tracking | max_clock_error_tracking | 0 | 0 | -- | ||
| V2 | max_phase_error | max_phase_error | 0 | 0 | -- | ||
| V2 | min_inter_pkt_delay | min_inter_pkt_delay | 0 | 0 | -- | ||
| V2 | max_inter_pkt_delay | max_inter_pkt_delay | 0 | 0 | -- | ||
| V2 | device_timeout_missing_host_handshake | device_timeout_missing_host_handshake | 0 | 0 | -- | ||
| V2 | device_timeout | device_timeout | 0 | 0 | -- | ||
| V2 | packet_buffer | usbdev_pkt_buffer | 0 | 50 | 0.00 | ||
| V2 | nak_to_out_trans_when_avbuffer_empty_rxfifo_full | nak_to_out_trans_when_avbuffer_empty_rxfifo_full | 0 | 0 | -- | ||
| V2 | aon_wake_resume | aon_wake_resume | 0 | 0 | -- | ||
| V2 | aon_wake_reset | aon_wake_reset | 0 | 0 | -- | ||
| V2 | aon_wake_disconnect | aon_wake_disconnect | 0 | 0 | -- | ||
| V2 | invalid_sync | invalid_sync | 0 | 0 | -- | ||
| V2 | spurious_tokens_ignored | spurious_tokens_ignored | 0 | 0 | -- | ||
| V2 | low_speed_traffic | low_speed_traffic | 0 | 0 | -- | ||
| V2 | rand_bus_resets | rand_bus_resets | 0 | 0 | -- | ||
| V2 | rand_disconnects | rand_disconnects | 0 | 0 | -- | ||
| V2 | max_usb_traffic | max_usb_traffic | 0 | 0 | -- | ||
| V2 | stress_usb_traffic | stress_usb_traffic | 0 | 0 | -- | ||
| V2 | in_packet_retraction | in_packet_retraction | 0 | 0 | -- | ||
| V2 | data_toggle_restore | data_toggle_restore | 0 | 0 | -- | ||
| V2 | setup_priority | setup_priority | 0 | 0 | -- | ||
| V2 | fifo_resets | usbdev_fifo_rst | 0 | 50 | 0.00 | ||
| V2 | intr_test | usbdev_intr_test | 0 | 50 | 0.00 | ||
| V2 | alert_test | usbdev_alert_test | 0 | 0 | -- | ||
| V2 | tl_d_oob_addr_access | usbdev_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | usbdev_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | usbdev_csr_hw_reset | 0 | 5 | 0.00 | ||
| usbdev_csr_rw | 0 | 20 | 0.00 | ||||
| usbdev_csr_aliasing | 0 | 5 | 0.00 | ||||
| usbdev_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | usbdev_csr_hw_reset | 0 | 5 | 0.00 | ||
| usbdev_csr_rw | 0 | 20 | 0.00 | ||||
| usbdev_csr_aliasing | 0 | 5 | 0.00 | ||||
| usbdev_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 1040 | 0.00 | |||
| V2S | tl_intg_err | usbdev_sec_cm | 0 | 5 | 0.00 | ||
| usbdev_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | usbdev_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | TOTAL | 0 | 25 | 0.00 | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| Unmapped tests | usbdev_dpi_config_host | 0 | 1 | 0.00 | |||
| usbdev_in_iso | 0 | 50 | 0.00 | ||||
| usbdev_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||||
| usbdev_stress_all | 0 | 50 | 0.00 | ||||
| TOTAL | 0 | 1331 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 4 | 4 | 0 | 0.00 |
| V1 | 8 | 8 | 0 | 0.00 |
| V2 | 78 | 22 | 0 | 0.00 |
| V2S | 2 | 2 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 1333 failures:
Test usbdev_smoke has 50 failures.
0.usbdev_smoke.68437033175397324305032350578057497269369130926073923791537522789873569177533
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_smoke/latest/run.log
1.usbdev_smoke.99992893325735870323665872056218218789472667020991141235837676591171862089854
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/1.usbdev_smoke/latest/run.log
... and 48 more failures.
Test usbdev_av_buffer has 50 failures.
0.usbdev_av_buffer.78199357322772581984013904495655101596913679114254055788785474668161077852340
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_av_buffer/latest/run.log
1.usbdev_av_buffer.106870320685851828728610538971908169975306664676669245566766331892835837243555
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/1.usbdev_av_buffer/latest/run.log
... and 48 more failures.
Test usbdev_dpi_config_host has 1 failures.
Test usbdev_enable has 50 failures.
0.usbdev_enable.23458926412998171325516758686965183542922146186696367132744507699731745171062
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_enable/latest/run.log
1.usbdev_enable.74044711660430020275884705771642529029554556083269300361814845462410461542464
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/1.usbdev_enable/latest/run.log
... and 48 more failures.
Test usbdev_fifo_rst has 50 failures.
0.usbdev_fifo_rst.14505970316825757774882837320282894376877940026667741638664212504069165903496
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_fifo_rst/latest/run.log
1.usbdev_fifo_rst.13348182004530554169705863282373938824201884939891678697009731435771358307161
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/1.usbdev_fifo_rst/latest/run.log
... and 48 more failures.
... and 32 more tests.
Exit reason: Error: User command failed Error-[NYI-NS] Not Yet Implemented has 2 failures:
Test default has 1 failures.
default
Line 1344, in log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/default/build.log
Error-[NYI-NS] Not Yet Implemented
The following feature is not yet supported: Replacing interface cell in
logical library not yet supported
"../src/lowrisc_dv_usb20_agent_0.1/usb20_if.sv", 5: token is 'usb20_if'
Test cover_reg_top has 1 failures.
cover_reg_top
Line 1344, in log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/cover_reg_top/build.log
Error-[NYI-NS] Not Yet Implemented
The following feature is not yet supported: Replacing interface cell in
logical library not yet supported
"../src/lowrisc_dv_usb20_agent_0.1/usb20_if.sv", 5: token is 'usb20_if'