USBDEV Simulation Results

Thursday May 16 2024 19:02:11 UTC

GitHub Revision: 349bab6601

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60729333463373082946889975499553948547086354767408862399987151421185145065082

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 14.680s 8.467ms 50 50 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 1.000s 191.641us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.040s 91.020us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 10.530s 1.990ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 2.220s 213.909us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 3.030s 118.303us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.040s 91.020us 20 20 100.00
usbdev_csr_aliasing 2.220s 213.909us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.620s 718.313us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.240s 80.132us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 in_trans usbdev_in_trans 14.350s 8.429ms 50 50 100.00
V2 data_toggle_clear data_toggle_clear 0 0 --
V2 phy_pins_sense usbdev_phy_pins_sense 14.090s 8.370ms 50 50 100.00
V2 av_buffer usbdev_av_buffer 14.320s 8.405ms 49 50 98.00
V2 rx_fifo rx_fifo 0 0 --
V2 phy_config_tx_osc_test_mode phy_config_tx_osc_test_mode 0 0 --
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 14.470s 8.401ms 49 50 98.00
V2 phy_config_pinflip phy_config_pinflip 0 0 --
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 14.290s 8.375ms 50 50 100.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 13.920s 8.418ms 49 50 98.00
V2 max_length_in_transaction max_length_in_transaction 0 0 --
V2 min_length_out_transaction usbdev_min_length_out_transaction 14.260s 8.374ms 50 50 100.00
V2 min_length_in_transaction min_length_in_transaction 0 0 --
V2 random_length_out_trans usbdev_random_length_out_trans 14.230s 8.408ms 50 50 100.00
V2 random_length_in_trans random_length_in_trans 0 0 --
V2 out_stall usbdev_out_stall 14.280s 8.434ms 49 50 98.00
V2 in_stall usbdev_in_stall 14.630s 8.371ms 50 50 100.00
V2 out_iso out_iso 0 0 --
V2 in_iso usbdev_in_iso 14.640s 8.492ms 48 50 96.00
V2 pkt_received usbdev_pkt_received 15.150s 8.449ms 49 50 98.00
V2 pkt_sent usbdev_pkt_sent 13.930s 8.444ms 49 50 98.00
V2 disconnected usbdev_disconnected 13.930s 8.396ms 50 50 100.00
V2 host_lost host_lost 0 0 --
V2 link_reset link_reset 0 0 --
V2 link_suspend usbdev_link_suspend 18.760s 11.544ms 50 50 100.00
V2 link_resume link_resume 0 0 --
V2 av_empty av_empty 0 0 --
V2 rx_full rx_full 0 0 --
V2 av_overflow av_overflow 0 0 --
V2 link_in_err usbdev_link_in_err 14.300s 8.347ms 49 50 98.00
V2 rx_crc_err usbdev_rx_crc_err 14.380s 8.369ms 50 50 100.00
V2 rx_pid_err rx_pid_err 0 0 --
V2 rx_bitstuff_err usbdev_bitstuff_err 14.480s 8.420ms 25 50 50.00
V2 link_out_err link_out_err 0 0 --
V2 enable usbdev_enable 14.100s 8.388ms 50 50 100.00
V2 resume_link_active resume_link_active 0 0 --
V2 device_address device_address 0 0 --
V2 invalid_data1_data0_toggle_test invalid_data1_data0_toggle_test 0 0 --
V2 setup_stage usbdev_setup_stage 13.530s 8.383ms 48 50 96.00
V2 endpoint_access usbdev_endpoint_access 15.360s 9.192ms 40 50 80.00
V2 disable_endpoint disable_endpoint 0 0 --
V2 out_trans_nak usbdev_out_trans_nak 13.980s 8.407ms 49 50 98.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 14.320s 8.400ms 50 50 100.00
V2 nak_trans usbdev_nak_trans 13.820s 8.408ms 50 50 100.00
V2 stall_trans usbdev_stall_trans 13.820s 8.376ms 48 50 96.00
V2 setup_priority_over_stall_response setup_priority_over_stall_response 0 0 --
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 13.790s 8.378ms 48 50 96.00
V2 pending_in_trans usbdev_pending_in_trans 14.820s 8.386ms 48 50 96.00
V2 streaming_test streaming_test 0 0 --
V2 max_clock_error_untracked max_clock_error_untracked 0 0 --
V2 max_clock_error_tracking max_clock_error_tracking 0 0 --
V2 max_phase_error max_phase_error 0 0 --
V2 min_inter_pkt_delay min_inter_pkt_delay 0 0 --
V2 max_inter_pkt_delay max_inter_pkt_delay 0 0 --
V2 device_timeout_missing_host_handshake device_timeout_missing_host_handshake 0 0 --
V2 device_timeout device_timeout 0 0 --
V2 packet_buffer usbdev_pkt_buffer 1.136m 29.624ms 45 50 90.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full nak_to_out_trans_when_avbuffer_empty_rxfifo_full 0 0 --
V2 aon_wake_resume aon_wake_resume 0 0 --
V2 aon_wake_reset aon_wake_reset 0 0 --
V2 aon_wake_disconnect aon_wake_disconnect 0 0 --
V2 invalid_sync invalid_sync 0 0 --
V2 spurious_tokens_ignored spurious_tokens_ignored 0 0 --
V2 low_speed_traffic low_speed_traffic 0 0 --
V2 rand_bus_resets rand_bus_resets 0 0 --
V2 rand_disconnects rand_disconnects 0 0 --
V2 max_usb_traffic max_usb_traffic 0 0 --
V2 stress_usb_traffic stress_usb_traffic 0 0 --
V2 in_packet_retraction in_packet_retraction 0 0 --
V2 data_toggle_restore usbdev_data_toggle_restore 15.360s 9.513ms 45 50 90.00
V2 setup_priority setup_priority 0 0 --
V2 fifo_resets usbdev_fifo_rst 15.010s 8.582ms 50 50 100.00
V2 intr_test usbdev_intr_test 0.780s 77.462us 50 50 100.00
V2 alert_test usbdev_alert_test 0 0 --
V2 tl_d_oob_addr_access usbdev_tl_errors 3.640s 344.791us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.640s 344.791us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 1.000s 191.641us 5 5 100.00
usbdev_csr_rw 1.040s 91.020us 20 20 100.00
usbdev_csr_aliasing 2.220s 213.909us 5 5 100.00
usbdev_same_csr_outstanding 1.880s 249.246us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 1.000s 191.641us 5 5 100.00
usbdev_csr_rw 1.040s 91.020us 20 20 100.00
usbdev_csr_aliasing 2.220s 213.909us 5 5 100.00
usbdev_same_csr_outstanding 1.880s 249.246us 20 20 100.00
V2 TOTAL 1527 1590 96.04
V2S tl_intg_err usbdev_sec_cm 2.090s 1.307ms 5 5 100.00
usbdev_tl_intg_err 5.990s 1.248ms 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 5.990s 1.248ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
Unmapped tests usbdev_dpi_config_host 2.275m 5.102ms 1 1 100.00
usbdev_out_iso 14.280s 8.418ms 50 50 100.00
random_length_in_trans 15.110s 8.473ms 50 50 100.00
min_length_in_transaction 14.830s 8.379ms 50 50 100.00
max_length_in_transaction 14.420s 8.537ms 50 50 100.00
usbdev_stress_all_with_rand_reset 0.710s 11.123us 0 50 0.00
usbdev_stress_all 0.610s 0 50 0.00
TOTAL 1718 1881 91.33

Testplan Progress

Items Total Written Passing Progress
N.A. 4 4 2 50.00
V1 8 8 8 100.00
V2 76 33 16 21.05
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
90.57 96.68 90.75 97.00 60.94 94.71 97.35 96.58

Failure Buckets

Past Results