Line Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Module :
prim_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T8 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T8,T9,T45 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T8 |
1 | 0 | Covered | T8,T9,T45 |
1 | 1 | Covered | T1,T3,T8 |
Branch Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_pulse_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1993313 |
1772 |
0 |
0 |
T1 |
4174 |
2 |
0 |
0 |
T2 |
6130 |
0 |
0 |
0 |
T3 |
2453 |
2 |
0 |
0 |
T4 |
60432 |
18 |
0 |
0 |
T5 |
66 |
4 |
0 |
0 |
T6 |
12976 |
0 |
0 |
0 |
T7 |
1750 |
0 |
0 |
0 |
T8 |
2183 |
4 |
0 |
0 |
T9 |
254 |
128 |
0 |
0 |
T13 |
0 |
39 |
0 |
0 |
T15 |
2685 |
0 |
0 |
0 |
T16 |
3016 |
0 |
0 |
0 |
T18 |
1911 |
0 |
0 |
0 |
T26 |
0 |
17 |
0 |
0 |
T31 |
0 |
188 |
0 |
0 |
T32 |
0 |
4 |
0 |
0 |
T45 |
0 |
26 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3925735 |
1811 |
0 |
0 |
T1 |
4254 |
4 |
0 |
0 |
T2 |
6213 |
0 |
0 |
0 |
T3 |
2453 |
2 |
0 |
0 |
T4 |
60432 |
18 |
0 |
0 |
T5 |
0 |
4 |
0 |
0 |
T6 |
12976 |
0 |
0 |
0 |
T7 |
1750 |
0 |
0 |
0 |
T8 |
2183 |
4 |
0 |
0 |
T9 |
0 |
128 |
0 |
0 |
T13 |
0 |
40 |
0 |
0 |
T15 |
2685 |
0 |
0 |
0 |
T16 |
3016 |
0 |
0 |
0 |
T18 |
1911 |
0 |
0 |
0 |
T31 |
0 |
188 |
0 |
0 |
T32 |
0 |
4 |
0 |
0 |
T45 |
0 |
26 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 6 | 85.71 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
0 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 6 | 2 | 33.33 |
Logical | 6 | 2 | 33.33 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Not Covered | |
1 | 1 | Unreachable | |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
20297 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1952719 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T8 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T8,T9,T45 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T8 |
1 | 0 | Covered | T8,T9,T45 |
1 | 1 | Covered | T1,T3,T8 |
Branch Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
20297 |
875 |
0 |
0 |
T3 |
25 |
1 |
0 |
0 |
T4 |
227 |
9 |
0 |
0 |
T5 |
66 |
2 |
0 |
0 |
T6 |
101 |
0 |
0 |
0 |
T7 |
35 |
0 |
0 |
0 |
T8 |
39 |
2 |
0 |
0 |
T9 |
254 |
64 |
0 |
0 |
T13 |
0 |
19 |
0 |
0 |
T15 |
24 |
0 |
0 |
0 |
T16 |
30 |
0 |
0 |
0 |
T18 |
29 |
0 |
0 |
0 |
T26 |
0 |
17 |
0 |
0 |
T31 |
0 |
94 |
0 |
0 |
T32 |
0 |
2 |
0 |
0 |
T45 |
0 |
13 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1952719 |
914 |
0 |
0 |
T1 |
4174 |
2 |
0 |
0 |
T2 |
6130 |
0 |
0 |
0 |
T3 |
2428 |
1 |
0 |
0 |
T4 |
60205 |
9 |
0 |
0 |
T5 |
0 |
2 |
0 |
0 |
T6 |
12875 |
0 |
0 |
0 |
T7 |
1715 |
0 |
0 |
0 |
T8 |
2144 |
2 |
0 |
0 |
T9 |
0 |
64 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T15 |
2661 |
0 |
0 |
0 |
T16 |
2986 |
0 |
0 |
0 |
T18 |
1882 |
0 |
0 |
0 |
T31 |
0 |
94 |
0 |
0 |
T32 |
0 |
2 |
0 |
0 |
T45 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T8 |
1 | 0 | Covered | T3,T8,T4 |
1 | 1 | Covered | T8,T9,T45 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T8 |
1 | 0 | Covered | T8,T9,T45 |
1 | 1 | Covered | T1,T3,T8 |
Branch Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1952719 |
897 |
0 |
0 |
T1 |
4174 |
2 |
0 |
0 |
T2 |
6130 |
0 |
0 |
0 |
T3 |
2428 |
1 |
0 |
0 |
T4 |
60205 |
9 |
0 |
0 |
T5 |
0 |
2 |
0 |
0 |
T6 |
12875 |
0 |
0 |
0 |
T7 |
1715 |
0 |
0 |
0 |
T8 |
2144 |
2 |
0 |
0 |
T9 |
0 |
64 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T15 |
2661 |
0 |
0 |
0 |
T16 |
2986 |
0 |
0 |
0 |
T18 |
1882 |
0 |
0 |
0 |
T31 |
0 |
94 |
0 |
0 |
T32 |
0 |
2 |
0 |
0 |
T45 |
0 |
13 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
20297 |
897 |
0 |
0 |
T1 |
80 |
2 |
0 |
0 |
T2 |
83 |
0 |
0 |
0 |
T3 |
25 |
1 |
0 |
0 |
T4 |
227 |
9 |
0 |
0 |
T5 |
0 |
2 |
0 |
0 |
T6 |
101 |
0 |
0 |
0 |
T7 |
35 |
0 |
0 |
0 |
T8 |
39 |
2 |
0 |
0 |
T9 |
0 |
64 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T15 |
24 |
0 |
0 |
0 |
T16 |
30 |
0 |
0 |
0 |
T18 |
29 |
0 |
0 |
0 |
T31 |
0 |
94 |
0 |
0 |
T32 |
0 |
2 |
0 |
0 |
T45 |
0 |
13 |
0 |
0 |