Line Coverage for Module :
prim_reg_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Module :
prim_reg_cdc
| Total | Covered | Percent |
Conditions | 14 | 10 | 71.43 |
Logical | 14 | 10 | 71.43 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T8 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T3,T8 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T8 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T3,T8 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
Branch Coverage for Module :
prim_reg_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T8 |
0 |
0 |
1 |
Covered |
T1,T3,T8 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T8 |
0 |
0 |
1 |
Covered |
T1,T3,T8 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_reg_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3905438 |
294072 |
0 |
0 |
T1 |
4174 |
251 |
0 |
0 |
T2 |
6130 |
0 |
0 |
0 |
T3 |
2428 |
239 |
0 |
0 |
T4 |
60205 |
6595 |
0 |
0 |
T5 |
0 |
346 |
0 |
0 |
T6 |
12875 |
0 |
0 |
0 |
T7 |
1715 |
0 |
0 |
0 |
T8 |
2144 |
267 |
0 |
0 |
T9 |
0 |
43607 |
0 |
0 |
T13 |
0 |
3026 |
0 |
0 |
T15 |
2661 |
0 |
0 |
0 |
T16 |
2986 |
0 |
0 |
0 |
T18 |
1882 |
0 |
0 |
0 |
T31 |
0 |
18951 |
0 |
0 |
T32 |
0 |
338 |
0 |
0 |
T45 |
0 |
2084 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
40594 |
32358 |
0 |
0 |
T1 |
160 |
110 |
0 |
0 |
T2 |
166 |
154 |
0 |
0 |
T3 |
50 |
40 |
0 |
0 |
T4 |
454 |
290 |
0 |
0 |
T6 |
202 |
180 |
0 |
0 |
T7 |
70 |
58 |
0 |
0 |
T8 |
78 |
60 |
0 |
0 |
T15 |
48 |
28 |
0 |
0 |
T16 |
60 |
42 |
0 |
0 |
T18 |
58 |
46 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3905438 |
897 |
0 |
0 |
T1 |
4174 |
2 |
0 |
0 |
T2 |
6130 |
0 |
0 |
0 |
T3 |
2428 |
1 |
0 |
0 |
T4 |
60205 |
9 |
0 |
0 |
T5 |
0 |
2 |
0 |
0 |
T6 |
12875 |
0 |
0 |
0 |
T7 |
1715 |
0 |
0 |
0 |
T8 |
2144 |
2 |
0 |
0 |
T9 |
0 |
64 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T15 |
2661 |
0 |
0 |
0 |
T16 |
2986 |
0 |
0 |
0 |
T18 |
1882 |
0 |
0 |
0 |
T31 |
0 |
94 |
0 |
0 |
T32 |
0 |
2 |
0 |
0 |
T45 |
0 |
13 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3905438 |
3785580 |
0 |
0 |
T1 |
8348 |
7868 |
0 |
0 |
T2 |
12260 |
12112 |
0 |
0 |
T3 |
4856 |
4744 |
0 |
0 |
T4 |
120410 |
118724 |
0 |
0 |
T6 |
25750 |
25576 |
0 |
0 |
T7 |
3430 |
3244 |
0 |
0 |
T8 |
4288 |
4166 |
0 |
0 |
T15 |
5322 |
5216 |
0 |
0 |
T16 |
5972 |
5828 |
0 |
0 |
T18 |
3764 |
3596 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 17 | 14 | 82.35 |
CONT_ASSIGN | 65 | 0 | 0 | |
ALWAYS | 71 | 5 | 4 | 80.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 7 | 5 | 71.43 |
CONT_ASSIGN | 150 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
|
unreachable |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
|
unreachable |
75 |
1 |
1 |
76 |
0 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
|
unreachable |
124 |
|
unreachable |
125 |
1 |
1 |
134 |
0 |
1 |
135 |
0 |
1 |
|
|
|
MISSING_ELSE |
150 |
|
unreachable |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
| Total | Covered | Percent |
Conditions | 13 | 4 | 30.77 |
Logical | 13 | 4 | 30.77 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
4 |
66.67 |
IF |
71 |
3 |
2 |
66.67 |
IF |
115 |
3 |
2 |
66.67 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Unreachable |
|
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Unreachable |
|
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1952719 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
20297 |
16179 |
0 |
0 |
T1 |
80 |
55 |
0 |
0 |
T2 |
83 |
77 |
0 |
0 |
T3 |
25 |
20 |
0 |
0 |
T4 |
227 |
145 |
0 |
0 |
T6 |
101 |
90 |
0 |
0 |
T7 |
35 |
29 |
0 |
0 |
T8 |
39 |
30 |
0 |
0 |
T15 |
24 |
14 |
0 |
0 |
T16 |
30 |
21 |
0 |
0 |
T18 |
29 |
23 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1952719 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1952719 |
1892790 |
0 |
0 |
T1 |
4174 |
3934 |
0 |
0 |
T2 |
6130 |
6056 |
0 |
0 |
T3 |
2428 |
2372 |
0 |
0 |
T4 |
60205 |
59362 |
0 |
0 |
T6 |
12875 |
12788 |
0 |
0 |
T7 |
1715 |
1622 |
0 |
0 |
T8 |
2144 |
2083 |
0 |
0 |
T15 |
2661 |
2608 |
0 |
0 |
T16 |
2986 |
2914 |
0 |
0 |
T18 |
1882 |
1798 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T8 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T3,T8 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T3,T8 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T3,T8 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T8 |
0 |
0 |
1 |
Covered |
T1,T3,T8 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T3,T8 |
0 |
0 |
1 |
Covered |
T1,T3,T8 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1952719 |
294072 |
0 |
0 |
T1 |
4174 |
251 |
0 |
0 |
T2 |
6130 |
0 |
0 |
0 |
T3 |
2428 |
239 |
0 |
0 |
T4 |
60205 |
6595 |
0 |
0 |
T5 |
0 |
346 |
0 |
0 |
T6 |
12875 |
0 |
0 |
0 |
T7 |
1715 |
0 |
0 |
0 |
T8 |
2144 |
267 |
0 |
0 |
T9 |
0 |
43607 |
0 |
0 |
T13 |
0 |
3026 |
0 |
0 |
T15 |
2661 |
0 |
0 |
0 |
T16 |
2986 |
0 |
0 |
0 |
T18 |
1882 |
0 |
0 |
0 |
T31 |
0 |
18951 |
0 |
0 |
T32 |
0 |
338 |
0 |
0 |
T45 |
0 |
2084 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
20297 |
16179 |
0 |
0 |
T1 |
80 |
55 |
0 |
0 |
T2 |
83 |
77 |
0 |
0 |
T3 |
25 |
20 |
0 |
0 |
T4 |
227 |
145 |
0 |
0 |
T6 |
101 |
90 |
0 |
0 |
T7 |
35 |
29 |
0 |
0 |
T8 |
39 |
30 |
0 |
0 |
T15 |
24 |
14 |
0 |
0 |
T16 |
30 |
21 |
0 |
0 |
T18 |
29 |
23 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1952719 |
897 |
0 |
0 |
T1 |
4174 |
2 |
0 |
0 |
T2 |
6130 |
0 |
0 |
0 |
T3 |
2428 |
1 |
0 |
0 |
T4 |
60205 |
9 |
0 |
0 |
T5 |
0 |
2 |
0 |
0 |
T6 |
12875 |
0 |
0 |
0 |
T7 |
1715 |
0 |
0 |
0 |
T8 |
2144 |
2 |
0 |
0 |
T9 |
0 |
64 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T15 |
2661 |
0 |
0 |
0 |
T16 |
2986 |
0 |
0 |
0 |
T18 |
1882 |
0 |
0 |
0 |
T31 |
0 |
94 |
0 |
0 |
T32 |
0 |
2 |
0 |
0 |
T45 |
0 |
13 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1952719 |
1892790 |
0 |
0 |
T1 |
4174 |
3934 |
0 |
0 |
T2 |
6130 |
6056 |
0 |
0 |
T3 |
2428 |
2372 |
0 |
0 |
T4 |
60205 |
59362 |
0 |
0 |
T6 |
12875 |
12788 |
0 |
0 |
T7 |
1715 |
1622 |
0 |
0 |
T8 |
2144 |
2083 |
0 |
0 |
T15 |
2661 |
2608 |
0 |
0 |
T16 |
2986 |
2914 |
0 |
0 |
T18 |
1882 |
1798 |
0 |
0 |