Unified Coverage Report :: Module :: tlul_adapter_sram

Module : tlul_adapter_sram

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_no_stubbed_memory.u_tlul2sram	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
23.39	0.00	0.00	93.58		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_err	0.00	0.00	0.00			0.00
u_reqfifo	0.00	0.00	0.00			0.00
u_rsp_gen	0.00	0.00
u_rspfifo	0.00	0.00	0.00			0.00
u_sram_byte	0.00	0.00
u_sramreqfifo	0.00	0.00	0.00			0.00
u_tlul_data_integ_enc_data	0.00	0.00
u_tlul_data_integ_enc_instr	0.00	0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : tlul_adapter_sram

	Line No.	Total	Covered	Percent
TOTAL		69	0	0.00
CONT_ASSIGN	102	0	0
CONT_ASSIGN	109	0	0
ALWAYS	124	3	0	0.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	138	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	170	1	0	0.00
CONT_ASSIGN	182	1	0	0.00
CONT_ASSIGN	259	1	0	0.00
CONT_ASSIGN	260	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
ALWAYS	266	8	0	0.00
ALWAYS	286	6	0	0.00
CONT_ASSIGN	300	1	0	0.00
CONT_ASSIGN	304	1	0	0.00
CONT_ASSIGN	323	1	0	0.00
CONT_ASSIGN	328	1	0	0.00
CONT_ASSIGN	334	1	0	0.00
CONT_ASSIGN	346	1	0	0.00
ALWAYS	349	3	0	0.00
CONT_ASSIGN	356	1	0	0.00
CONT_ASSIGN	376	1	0	0.00
CONT_ASSIGN	377	1	0	0.00
CONT_ASSIGN	378	1	0	0.00
CONT_ASSIGN	379	1	0	0.00
ALWAYS	409	6	0	0.00
ALWAYS	421	5	0	0.00
CONT_ASSIGN	436	1	0	0.00
CONT_ASSIGN	437	1	0	0.00
CONT_ASSIGN	438	1	0	0.00
CONT_ASSIGN	442	1	0	0.00
CONT_ASSIGN	443	1	0	0.00
CONT_ASSIGN	445	1	0	0.00
CONT_ASSIGN	446	1	0	0.00
CONT_ASSIGN	453	1	0	0.00
CONT_ASSIGN	456	1	0	0.00
CONT_ASSIGN	460	1	0	0.00
CONT_ASSIGN	461	1	0	0.00
CONT_ASSIGN	463	1	0	0.00
CONT_ASSIGN	470	1	0	0.00
ALWAYS	488	3	0	0.00
CONT_ASSIGN	494	1	0	0.00
CONT_ASSIGN	497	1	0	0.00
CONT_ASSIGN	502	1	0	0.00
CONT_ASSIGN	507	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
102		unreachable
109		unreachable
124	0	1
125	0	1
126	0	1
127		unreachable
			==> MISSING_ELSE
133	0	1
138	0	1
145	0	1
170	0	1
182	0	1
259	0	1
260	0	1
261	0	1
266	0	1
268	0	1
269	0	1
271	0	1
272	0	1
273	0	1
276	0	1
279	0	1
286	0	1
288	0	1
289	0	1
290	0	1
292	0	1
295	0	1
300	0	1
304	0	1
323	0	1
328	0	1
334	0	1
346	0	1
349	0	1
350	0	1
352	0	1
356	0	1
376	0	1
377	0	1
378	0	1
379	0	1
409	0	1
410	0	1
412	0	1
413	0	1
414	0	1
415	0	1
			==> MISSING_ELSE
421	0	1
422	0	1
424	0	1
425	0	1
426	0	1
			==> MISSING_ELSE
436	0	1
437	0	1
438	0	1
442	0	1
443	0	1
445	0	1
446	0	1
453	0	1
456	0	1
460	0	1
461	0	1
463	0	1
470	0	1
488	0	1
489	0	1
490	0	1
494	0	1
497	0	1
502	0	1
507		unreachable

---

Cond Coverage for Module : tlul_adapter_sram

	Total	Covered	Percent
Conditions	118	0	0.00
Logical	118	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       109
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Unreachable
1	0	Unreachable

 LINE       126
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Unreachable
1	0	Unreachable

 LINE       133
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Not Covered
0	1	0	Unreachable
1	0	0	Unreachable

 LINE       138
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       138
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       138
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       138
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       138
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       138
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       138
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       170
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Not Covered
0	0	0	0	0	1	Unreachable
0	0	0	0	1	0	Not Covered
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Unreachable
0	1	0	0	0	0	Unreachable
1	0	0	0	0	0	Not Covered

 LINE       259
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       260
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       261
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       272
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       289
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       290
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       300
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Not Covered

 LINE       300
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       328
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       328
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       334
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       334
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       334
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       346
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       356
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       356
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       356
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       356
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       356
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       356
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       356
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready)
             -------------1------------   -------2------   ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       356
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       376
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       378
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       379
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       415
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       415
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       438
 EXPRESSION (((|wmask_intg)) & ((|wdata_intg)))
             -------1-------   -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       446
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       446
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       460
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       463
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       502
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       502
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       502
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Module : tlul_adapter_sram

	Line No.	Total	Covered	Percent
Branches		26	0	0.00
TERNARY	138	2	0	0.00
TERNARY	328	2	0	0.00
TERNARY	334	3	0	0.00
TERNARY	379	2	0	0.00
TERNARY	502	2	0	0.00
IF	124	2	0	0.00
IF	268	4	0	0.00
IF	288	3	0	0.00
IF	349	2	0	0.00
IF	412	2	0	0.00
IF	424	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	328	((vld_rd_rsp & (~d_error))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	334	((vld_rd_rsp && reqfifo_rdata.error)) ? 
-2-:	334	(vld_rd_rsp) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	379	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	502	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	124	if ((!rst_ni))
-2-:	126	if ((intg_error || rsp_fifo_error))

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Unreachable
0	0	Not Covered

	LineNo.	Expression
-1-:	268	if (reqfifo_rvalid)
-2-:	269	if (reqfifo_rdata.error)
-3-:	272	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Not Covered
1	0	1	Not Covered
1	0	0	Not Covered
0	-	-	Not Covered

	LineNo.	Expression
-1-:	288	if (reqfifo_rvalid)
-2-:	289	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	349	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	412	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	424	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered