Module Definition
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Module : tlul_sram_byte
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sram_byte 0.00 0.00



Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sram_byte

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
0.00 0.00 0.00 0.00 gen_no_stubbed_memory.u_tlul2sram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : tlul_sram_byte
Line No.TotalCoveredPercent
TOTAL300.00
CONT_ASSIGN696100.00
CONT_ASSIGN697100.00
CONT_ASSIGN698100.00
CONT_ASSIGN70400
CONT_ASSIGN71000
CONT_ASSIGN71100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
696 0 1
697 0 1
698 0 1
704 unreachable
710 unreachable
711 unreachable

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%