USBDEV Simulation Results

Saturday June 08 2024 00:41:57 UTC

GitHub Revision: 302b24f3c6

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 32491226968592963393132943636196950930602503490106290691157604759716956925599

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 16.780s 10.129ms 50 50 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 0.990s 86.969us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.120s 141.893us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 13.350s 1.992ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.670s 316.669us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.360s 94.383us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.120s 141.893us 20 20 100.00
usbdev_csr_aliasing 3.670s 316.669us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.680s 727.481us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.340s 166.282us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 in_trans usbdev_in_trans 16.390s 10.148ms 50 50 100.00
V2 data_toggle_clear data_toggle_clear 0 0 --
V2 phy_pins_sense usbdev_phy_pins_sense 15.270s 10.051ms 50 50 100.00
V2 av_buffer usbdev_av_buffer 16.420s 10.053ms 50 50 100.00
V2 rx_fifo rx_fifo 0 0 --
V2 phy_config_tx_osc_test_mode phy_config_tx_osc_test_mode 0 0 --
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 16.460s 10.097ms 50 50 100.00
V2 phy_config_pinflip phy_config_pinflip 0 0 --
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 16.790s 10.060ms 50 50 100.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 16.160s 10.101ms 50 50 100.00
V2 max_length_in_transaction max_length_in_transaction 0 0 --
V2 min_length_out_transaction usbdev_min_length_out_transaction 15.650s 10.058ms 50 50 100.00
V2 min_length_in_transaction min_length_in_transaction 0 0 --
V2 random_length_out_trans usbdev_random_length_out_trans 16.810s 10.084ms 50 50 100.00
V2 random_length_in_trans random_length_in_trans 0 0 --
V2 out_stall usbdev_out_stall 16.310s 10.055ms 50 50 100.00
V2 in_stall usbdev_in_stall 16.480s 10.038ms 50 50 100.00
V2 out_iso out_iso 0 0 --
V2 in_iso usbdev_in_iso 16.130s 10.129ms 50 50 100.00
V2 pkt_received usbdev_pkt_received 17.360s 10.075ms 50 50 100.00
V2 pkt_sent usbdev_pkt_sent 16.650s 10.122ms 50 50 100.00
V2 disconnected usbdev_disconnected 16.110s 10.044ms 50 50 100.00
V2 host_lost host_lost 0 0 --
V2 link_reset link_reset 0 0 --
V2 link_suspend usbdev_link_suspend 19.710s 13.236ms 50 50 100.00
V2 link_resume link_resume 0 0 --
V2 av_empty av_empty 0 0 --
V2 rx_full rx_full 0 0 --
V2 av_overflow av_overflow 0 0 --
V2 link_in_err usbdev_link_in_err 16.330s 10.164ms 50 50 100.00
V2 rx_crc_err usbdev_rx_crc_err 16.310s 10.066ms 50 50 100.00
V2 rx_pid_err rx_pid_err 0 0 --
V2 rx_bitstuff_err usbdev_bitstuff_err 16.270s 10.055ms 21 50 42.00
V2 link_out_err link_out_err 0 0 --
V2 enable usbdev_enable 16.460s 10.058ms 50 50 100.00
V2 resume_link_active resume_link_active 0 0 --
V2 device_address device_address 0 0 --
V2 invalid_data1_data0_toggle_test invalid_data1_data0_toggle_test 0 0 --
V2 setup_stage usbdev_setup_stage 16.770s 10.053ms 50 50 100.00
V2 endpoint_access usbdev_endpoint_access 18.910s 10.717ms 50 50 100.00
V2 disable_endpoint disable_endpoint 0 0 --
V2 out_trans_nak usbdev_out_trans_nak 16.450s 10.095ms 50 50 100.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 15.930s 10.062ms 50 50 100.00
V2 nak_trans usbdev_nak_trans 16.150s 10.100ms 50 50 100.00
V2 stall_trans usbdev_stall_trans 16.770s 10.075ms 50 50 100.00
V2 setup_priority_over_stall_response setup_priority_over_stall_response 0 0 --
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 16.010s 10.069ms 50 50 100.00
V2 pending_in_trans usbdev_pending_in_trans 16.810s 10.044ms 50 50 100.00
V2 streaming_test usbdev_streaming_out 6.654m 24.162ms 50 50 100.00
V2 max_clock_error_untracked max_clock_error_untracked 0 0 --
V2 max_clock_error_tracking max_clock_error_tracking 0 0 --
V2 max_phase_error max_phase_error 0 0 --
V2 min_inter_pkt_delay min_inter_pkt_delay 0 0 --
V2 max_inter_pkt_delay max_inter_pkt_delay 0 0 --
V2 device_timeout_missing_host_handshake device_timeout_missing_host_handshake 0 0 --
V2 device_timeout device_timeout 0 0 --
V2 packet_buffer usbdev_pkt_buffer 1.076m 30.524ms 50 50 100.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full nak_to_out_trans_when_avbuffer_empty_rxfifo_full 0 0 --
V2 aon_wake_resume usbdev_aon_wake_resume 0 50 0.00
V2 aon_wake_reset usbdev_aon_wake_reset 31.870s 23.340ms 50 50 100.00
V2 aon_wake_disconnect usbdev_aon_wake_disconnect 21.030s 14.292ms 50 50 100.00
V2 invalid_sync invalid_sync 0 0 --
V2 spurious_tokens_ignored spurious_tokens_ignored 0 0 --
V2 low_speed_traffic low_speed_traffic 0 0 --
V2 rand_bus_resets rand_bus_resets 0 0 --
V2 rand_disconnects rand_disconnects 0 0 --
V2 max_usb_traffic max_usb_traffic 0 0 --
V2 stress_usb_traffic stress_usb_traffic 0 0 --
V2 in_packet_retraction in_packet_retraction 0 0 --
V2 data_toggle_restore usbdev_data_toggle_restore 17.810s 11.098ms 50 50 100.00
V2 setup_priority setup_priority 0 0 --
V2 fifo_resets usbdev_fifo_rst 18.350s 10.223ms 50 50 100.00
V2 intr_test usbdev_intr_test 0.790s 68.027us 50 50 100.00
V2 alert_test usbdev_alert_test 0 0 --
V2 tl_d_oob_addr_access usbdev_tl_errors 3.890s 151.467us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.890s 151.467us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 0.990s 86.969us 5 5 100.00
usbdev_csr_rw 1.120s 141.893us 20 20 100.00
usbdev_csr_aliasing 3.670s 316.669us 5 5 100.00
usbdev_same_csr_outstanding 1.730s 326.931us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 0.990s 86.969us 5 5 100.00
usbdev_csr_rw 1.120s 141.893us 20 20 100.00
usbdev_csr_aliasing 3.670s 316.669us 5 5 100.00
usbdev_same_csr_outstanding 1.730s 326.931us 20 20 100.00
V2 TOTAL 1711 1790 95.59
V2S tl_intg_err usbdev_sec_cm 1.380s 629.428us 5 5 100.00
usbdev_tl_intg_err 6.740s 2.305ms 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 6.740s 2.305ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
Unmapped tests usbdev_dpi_config_host 31.030s 5.116ms 1 1 100.00
usbdev_max_usb_traffic 7.254m 24.660ms 50 50 100.00
usbdev_out_iso 16.770s 10.116ms 50 50 100.00
usbdev_rand_bus_disconnects 12.085m 38.180ms 10 10 100.00
usbdev_rand_bus_resets 9.256m 29.354ms 10 10 100.00
usbdev_rand_suspends 12.125m 38.116ms 10 10 100.00
usbdev_stress_usb_traffic 9.597m 32.931ms 5 5 100.00
random_length_in_trans 16.830s 10.123ms 50 50 100.00
min_length_in_transaction 16.500s 10.055ms 50 50 100.00
max_length_in_transaction 16.710s 10.191ms 50 50 100.00
usbdev_stress_all_with_rand_reset 0.780s 90.682us 0 50 0.00
usbdev_stress_all 0.640s 0 50 0.00
TOTAL 1987 2166 91.74

Testplan Progress

Items Total Written Passing Progress
N.A. 9 9 7 77.78
V1 8 8 8 100.00
V2 76 37 35 46.05
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
92.41 97.48 92.28 97.86 68.75 95.77 98.17 96.58

Failure Buckets

Past Results