USBDEV Simulation Results

Sunday June 02 2024 19:02:53 UTC

GitHub Revision: 01a208901a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 50418669159766293903157726892781832882154091083197082086235277423705989875584

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 17.160s 10.140ms 50 50 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 1.110s 222.329us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.160s 105.413us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 8.550s 666.621us 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.820s 289.754us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.770s 92.818us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.160s 105.413us 20 20 100.00
usbdev_csr_aliasing 3.820s 289.754us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.860s 732.090us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.300s 86.704us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 in_trans usbdev_in_trans 18.400s 10.064ms 50 50 100.00
V2 data_toggle_clear data_toggle_clear 0 0 --
V2 phy_pins_sense usbdev_phy_pins_sense 17.600s 10.046ms 50 50 100.00
V2 av_buffer usbdev_av_buffer 16.890s 10.054ms 50 50 100.00
V2 rx_fifo rx_fifo 0 0 --
V2 phy_config_tx_osc_test_mode phy_config_tx_osc_test_mode 0 0 --
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 16.390s 10.090ms 50 50 100.00
V2 phy_config_pinflip phy_config_pinflip 0 0 --
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 16.910s 10.045ms 50 50 100.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 17.500s 10.084ms 50 50 100.00
V2 max_length_in_transaction max_length_in_transaction 0 0 --
V2 min_length_out_transaction usbdev_min_length_out_transaction 18.090s 10.053ms 50 50 100.00
V2 min_length_in_transaction min_length_in_transaction 0 0 --
V2 random_length_out_trans usbdev_random_length_out_trans 16.830s 10.054ms 50 50 100.00
V2 random_length_in_trans random_length_in_trans 0 0 --
V2 out_stall usbdev_out_stall 16.810s 10.047ms 50 50 100.00
V2 in_stall usbdev_in_stall 16.300s 10.072ms 50 50 100.00
V2 out_iso out_iso 0 0 --
V2 in_iso usbdev_in_iso 16.590s 10.159ms 50 50 100.00
V2 pkt_received usbdev_pkt_received 17.530s 10.071ms 50 50 100.00
V2 pkt_sent usbdev_pkt_sent 17.200s 10.104ms 50 50 100.00
V2 disconnected usbdev_disconnected 16.520s 10.037ms 50 50 100.00
V2 host_lost host_lost 0 0 --
V2 link_reset link_reset 0 0 --
V2 link_suspend usbdev_link_suspend 21.150s 13.203ms 50 50 100.00
V2 link_resume link_resume 0 0 --
V2 av_empty av_empty 0 0 --
V2 rx_full rx_full 0 0 --
V2 av_overflow av_overflow 0 0 --
V2 link_in_err usbdev_link_in_err 16.450s 10.108ms 50 50 100.00
V2 rx_crc_err usbdev_rx_crc_err 17.490s 10.042ms 50 50 100.00
V2 rx_pid_err rx_pid_err 0 0 --
V2 rx_bitstuff_err usbdev_bitstuff_err 17.260s 10.014ms 17 50 34.00
V2 link_out_err link_out_err 0 0 --
V2 enable usbdev_enable 16.810s 10.060ms 50 50 100.00
V2 resume_link_active resume_link_active 0 0 --
V2 device_address device_address 0 0 --
V2 invalid_data1_data0_toggle_test invalid_data1_data0_toggle_test 0 0 --
V2 setup_stage usbdev_setup_stage 17.220s 10.056ms 50 50 100.00
V2 endpoint_access usbdev_endpoint_access 17.880s 10.745ms 50 50 100.00
V2 disable_endpoint disable_endpoint 0 0 --
V2 out_trans_nak usbdev_out_trans_nak 16.580s 10.083ms 50 50 100.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 16.510s 10.051ms 50 50 100.00
V2 nak_trans usbdev_nak_trans 17.670s 10.143ms 50 50 100.00
V2 stall_trans usbdev_stall_trans 17.820s 10.081ms 50 50 100.00
V2 setup_priority_over_stall_response setup_priority_over_stall_response 0 0 --
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 17.080s 10.071ms 50 50 100.00
V2 pending_in_trans usbdev_pending_in_trans 17.260s 10.057ms 50 50 100.00
V2 streaming_test usbdev_streaming_out 7.481m 25.203ms 50 50 100.00
V2 max_clock_error_untracked max_clock_error_untracked 0 0 --
V2 max_clock_error_tracking max_clock_error_tracking 0 0 --
V2 max_phase_error max_phase_error 0 0 --
V2 min_inter_pkt_delay min_inter_pkt_delay 0 0 --
V2 max_inter_pkt_delay max_inter_pkt_delay 0 0 --
V2 device_timeout_missing_host_handshake device_timeout_missing_host_handshake 0 0 --
V2 device_timeout device_timeout 0 0 --
V2 packet_buffer usbdev_pkt_buffer 1.124m 28.539ms 50 50 100.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full nak_to_out_trans_when_avbuffer_empty_rxfifo_full 0 0 --
V2 aon_wake_resume usbdev_aon_wake_resume 0 50 0.00
V2 aon_wake_reset usbdev_aon_wake_reset 33.360s 23.260ms 50 50 100.00
V2 aon_wake_disconnect usbdev_aon_wake_disconnect 21.450s 13.667ms 50 50 100.00
V2 invalid_sync invalid_sync 0 0 --
V2 spurious_tokens_ignored spurious_tokens_ignored 0 0 --
V2 low_speed_traffic low_speed_traffic 0 0 --
V2 rand_bus_resets rand_bus_resets 0 0 --
V2 rand_disconnects rand_disconnects 0 0 --
V2 max_usb_traffic max_usb_traffic 0 0 --
V2 stress_usb_traffic stress_usb_traffic 0 0 --
V2 in_packet_retraction in_packet_retraction 0 0 --
V2 data_toggle_restore usbdev_data_toggle_restore 18.010s 10.658ms 50 50 100.00
V2 setup_priority setup_priority 0 0 --
V2 fifo_resets usbdev_fifo_rst 19.400s 10.064ms 50 50 100.00
V2 intr_test usbdev_intr_test 0.860s 112.725us 50 50 100.00
V2 alert_test usbdev_alert_test 0 0 --
V2 tl_d_oob_addr_access usbdev_tl_errors 3.190s 266.049us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.190s 266.049us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 1.110s 222.329us 5 5 100.00
usbdev_csr_rw 1.160s 105.413us 20 20 100.00
usbdev_csr_aliasing 3.820s 289.754us 5 5 100.00
usbdev_same_csr_outstanding 2.250s 280.817us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 1.110s 222.329us 5 5 100.00
usbdev_csr_rw 1.160s 105.413us 20 20 100.00
usbdev_csr_aliasing 3.820s 289.754us 5 5 100.00
usbdev_same_csr_outstanding 2.250s 280.817us 20 20 100.00
V2 TOTAL 1707 1790 95.36
V2S tl_intg_err usbdev_sec_cm 1.740s 744.096us 5 5 100.00
usbdev_tl_intg_err 5.950s 1.979ms 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 5.950s 1.979ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
Unmapped tests usbdev_dpi_config_host 32.950s 5.120ms 1 1 100.00
usbdev_max_usb_traffic 7.589m 24.404ms 50 50 100.00
usbdev_out_iso 18.060s 10.091ms 50 50 100.00
usbdev_rand_bus_disconnects 10.513m 32.765ms 10 10 100.00
usbdev_rand_bus_resets 8.213m 26.926ms 10 10 100.00
usbdev_rand_suspends 13.268m 40.838ms 10 10 100.00
usbdev_stress_usb_traffic 16.285m 41.890ms 5 5 100.00
random_length_in_trans 17.230s 10.089ms 50 50 100.00
min_length_in_transaction 16.680s 10.069ms 50 50 100.00
max_length_in_transaction 16.930s 10.142ms 50 50 100.00
usbdev_stress_all_with_rand_reset 0.700s 18.312us 0 50 0.00
usbdev_stress_all 0.610s 0 50 0.00
TOTAL 1983 2166 91.55

Testplan Progress

Items Total Written Passing Progress
N.A. 9 9 7 77.78
V1 8 8 8 100.00
V2 76 37 35 46.05
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
92.43 97.48 92.37 97.86 68.75 95.77 98.17 96.58

Failure Buckets

Past Results