USBDEV Simulation Results

Tuesday May 28 2024 19:30:06 UTC

GitHub Revision: 0e5093d709

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 51604449886868634540233838791789448907774502353938218657919214072353062987195

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 0 50 0.00
V1 csr_hw_reset usbdev_csr_hw_reset 0.950s 86.975us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.080s 79.544us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 9.730s 1.217ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.540s 309.559us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.630s 103.660us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.080s 79.544us 20 20 100.00
usbdev_csr_aliasing 3.540s 309.559us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.010s 158.515us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.250s 68.360us 5 5 100.00
V1 TOTAL 65 115 56.52
V2 in_trans usbdev_in_trans 0 50 0.00
V2 data_toggle_clear data_toggle_clear 0 0 --
V2 phy_pins_sense usbdev_phy_pins_sense 0 50 0.00
V2 av_buffer usbdev_av_buffer 0 50 0.00
V2 rx_fifo rx_fifo 0 0 --
V2 phy_config_tx_osc_test_mode phy_config_tx_osc_test_mode 0 0 --
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 0 50 0.00
V2 phy_config_pinflip phy_config_pinflip 0 0 --
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 0 50 0.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 0 50 0.00
V2 max_length_in_transaction max_length_in_transaction 0 0 --
V2 min_length_out_transaction usbdev_min_length_out_transaction 0 50 0.00
V2 min_length_in_transaction min_length_in_transaction 0 0 --
V2 random_length_out_trans usbdev_random_length_out_trans 0 50 0.00
V2 random_length_in_trans random_length_in_trans 0 0 --
V2 out_stall usbdev_out_stall 0 50 0.00
V2 in_stall usbdev_in_stall 0 50 0.00
V2 out_iso out_iso 0 0 --
V2 in_iso usbdev_in_iso 0 50 0.00
V2 pkt_received usbdev_pkt_received 0 50 0.00
V2 pkt_sent usbdev_pkt_sent 0 50 0.00
V2 disconnected usbdev_disconnected 0 50 0.00
V2 host_lost host_lost 0 0 --
V2 link_reset link_reset 0 0 --
V2 link_suspend usbdev_link_suspend 0 50 0.00
V2 link_resume link_resume 0 0 --
V2 av_empty av_empty 0 0 --
V2 rx_full rx_full 0 0 --
V2 av_overflow av_overflow 0 0 --
V2 link_in_err usbdev_link_in_err 0 50 0.00
V2 rx_crc_err usbdev_rx_crc_err 0 50 0.00
V2 rx_pid_err rx_pid_err 0 0 --
V2 rx_bitstuff_err usbdev_bitstuff_err 0 50 0.00
V2 link_out_err link_out_err 0 0 --
V2 enable usbdev_enable 0 50 0.00
V2 resume_link_active resume_link_active 0 0 --
V2 device_address device_address 0 0 --
V2 invalid_data1_data0_toggle_test invalid_data1_data0_toggle_test 0 0 --
V2 setup_stage usbdev_setup_stage 0 50 0.00
V2 endpoint_access usbdev_endpoint_access 0 50 0.00
V2 disable_endpoint disable_endpoint 0 0 --
V2 out_trans_nak usbdev_out_trans_nak 0 50 0.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 0 50 0.00
V2 nak_trans usbdev_nak_trans 0 50 0.00
V2 stall_trans usbdev_stall_trans 0 50 0.00
V2 setup_priority_over_stall_response setup_priority_over_stall_response 0 0 --
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 0 50 0.00
V2 pending_in_trans usbdev_pending_in_trans 0 50 0.00
V2 streaming_test streaming_test 0 0 --
V2 max_clock_error_untracked max_clock_error_untracked 0 0 --
V2 max_clock_error_tracking max_clock_error_tracking 0 0 --
V2 max_phase_error max_phase_error 0 0 --
V2 min_inter_pkt_delay min_inter_pkt_delay 0 0 --
V2 max_inter_pkt_delay max_inter_pkt_delay 0 0 --
V2 device_timeout_missing_host_handshake device_timeout_missing_host_handshake 0 0 --
V2 device_timeout device_timeout 0 0 --
V2 packet_buffer usbdev_pkt_buffer 0 50 0.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full nak_to_out_trans_when_avbuffer_empty_rxfifo_full 0 0 --
V2 aon_wake_resume usbdev_aon_wake_resume 0 50 0.00
V2 aon_wake_reset usbdev_aon_wake_reset 0 50 0.00
V2 aon_wake_disconnect usbdev_aon_wake_disconnect 0 50 0.00
V2 invalid_sync invalid_sync 0 0 --
V2 spurious_tokens_ignored spurious_tokens_ignored 0 0 --
V2 low_speed_traffic low_speed_traffic 0 0 --
V2 rand_bus_resets rand_bus_resets 0 0 --
V2 rand_disconnects rand_disconnects 0 0 --
V2 max_usb_traffic max_usb_traffic 0 0 --
V2 stress_usb_traffic stress_usb_traffic 0 0 --
V2 in_packet_retraction in_packet_retraction 0 0 --
V2 data_toggle_restore usbdev_data_toggle_restore 0 50 0.00
V2 setup_priority setup_priority 0 0 --
V2 fifo_resets usbdev_fifo_rst 0 50 0.00
V2 intr_test usbdev_intr_test 0.780s 109.010us 50 50 100.00
V2 alert_test usbdev_alert_test 0 0 --
V2 tl_d_oob_addr_access usbdev_tl_errors 3.460s 325.892us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.460s 325.892us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 0.950s 86.975us 5 5 100.00
usbdev_csr_rw 1.080s 79.544us 20 20 100.00
usbdev_csr_aliasing 3.540s 309.559us 5 5 100.00
usbdev_same_csr_outstanding 1.860s 214.681us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 0.950s 86.975us 5 5 100.00
usbdev_csr_rw 1.080s 79.544us 20 20 100.00
usbdev_csr_aliasing 3.540s 309.559us 5 5 100.00
usbdev_same_csr_outstanding 1.860s 214.681us 20 20 100.00
V2 TOTAL 90 1740 5.17
V2S tl_intg_err usbdev_sec_cm 0 5 0.00
usbdev_tl_intg_err 6.500s 1.790ms 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 6.500s 1.790ms 20 20 100.00
V2S TOTAL 20 25 80.00
V3 TOTAL 0 0 --
Unmapped tests usbdev_dpi_config_host 0 1 0.00
usbdev_out_iso 0 50 0.00
random_length_in_trans 0 50 0.00
min_length_in_transaction 0 50 0.00
max_length_in_transaction 0 50 0.00
usbdev_stress_all_with_rand_reset 0 50 0.00
usbdev_stress_all 0 50 0.00
TOTAL 175 2031 8.62

Testplan Progress

Items Total Written Passing Progress
N.A. 4 4 0 0.00
V1 8 8 7 87.50
V2 76 36 3 3.95
V2S 2 2 1 50.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
68.38 66.22 61.10 87.37 0.00 69.99 97.77 96.22

Failure Buckets

Past Results