Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	362	1		T1	5		T3	8		T7	5
all_values[1]	362	1		T1	5		T3	8		T7	5
all_values[2]	362	1		T1	5		T3	8		T7	5
all_values[3]	362	1		T1	5		T3	8		T7	5
all_values[4]	362	1		T1	5		T3	8		T7	5
all_values[5]	362	1		T1	5		T3	8		T7	5
all_values[6]	362	1		T1	5		T3	8		T7	5
all_values[7]	362	1		T1	5		T3	8		T7	5
all_values[8]	362	1		T1	5		T3	8		T7	5
all_values[9]	362	1		T1	5		T3	8		T7	5
all_values[10]	362	1		T1	5		T3	8		T7	5
all_values[11]	362	1		T1	5		T3	8		T7	5
all_values[12]	362	1		T1	5		T3	8		T7	5
all_values[13]	362	1		T1	5		T3	8		T7	5
all_values[14]	362	1		T1	5		T3	8		T7	5
all_values[15]	362	1		T1	5		T3	8		T7	5
all_values[16]	362	1		T1	5		T3	8		T7	5
all_values[17]	362	1		T1	5		T3	8		T7	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3531	1		T1	35		T3	67		T7	48
auto[1]	2985	1		T1	55		T3	77		T7	42

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1662	1		T1	12		T3	19		T7	18
auto[1]	4854	1		T1	78		T3	125		T7	72

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	65	1		T18	2		T20	2		T21	2
all_values[0]	auto[0]	auto[1]	140	1		T1	4		T3	1		T7	3
all_values[0]	auto[1]	auto[0]	29	1		T3	3		T64	1		T65	5
all_values[0]	auto[1]	auto[1]	128	1		T1	1		T3	4		T7	2
all_values[1]	auto[0]	auto[0]	68	1		T18	2		T20	2		T21	2
all_values[1]	auto[0]	auto[1]	144	1		T1	4		T3	6		T7	1
all_values[1]	auto[1]	auto[0]	21	1		T1	1		T66	1		T67	2
all_values[1]	auto[1]	auto[1]	129	1		T3	2		T7	4		T14	2
all_values[2]	auto[0]	auto[0]	72	1		T7	1		T18	2		T20	2
all_values[2]	auto[0]	auto[1]	122	1		T1	1		T3	2		T14	8
all_values[2]	auto[1]	auto[0]	31	1		T60	1		T61	3		T68	1
all_values[2]	auto[1]	auto[1]	137	1		T1	4		T3	6		T7	4
all_values[3]	auto[0]	auto[0]	66	1		T3	1		T7	1		T18	2
all_values[3]	auto[0]	auto[1]	132	1		T1	3		T3	3		T7	3
all_values[3]	auto[1]	auto[0]	27	1		T3	3		T60	1		T64	1
all_values[3]	auto[1]	auto[1]	137	1		T1	2		T3	1		T7	1
all_values[4]	auto[0]	auto[0]	64	1		T3	1		T18	2		T20	2
all_values[4]	auto[0]	auto[1]	138	1		T3	2		T7	4		T14	2
all_values[4]	auto[1]	auto[0]	24	1		T1	1		T60	1		T69	1
all_values[4]	auto[1]	auto[1]	136	1		T1	4		T3	5		T7	1
all_values[5]	auto[0]	auto[0]	69	1		T3	1		T7	1		T18	2
all_values[5]	auto[0]	auto[1]	137	1		T1	3		T3	4		T14	4
all_values[5]	auto[1]	auto[0]	19	1		T7	1		T60	1		T62	1
all_values[5]	auto[1]	auto[1]	137	1		T1	2		T3	3		T7	3
all_values[6]	auto[0]	auto[0]	57	1		T1	1		T7	2		T18	2
all_values[6]	auto[0]	auto[1]	133	1		T1	1		T3	5		T7	3
all_values[6]	auto[1]	auto[0]	26	1		T60	1		T68	1		T66	3
all_values[6]	auto[1]	auto[1]	146	1		T1	3		T3	3		T14	6
all_values[7]	auto[0]	auto[0]	77	1		T3	2		T18	2		T20	2
all_values[7]	auto[0]	auto[1]	120	1		T1	1		T3	1		T7	3
all_values[7]	auto[1]	auto[0]	31	1		T3	1		T7	1		T14	1
all_values[7]	auto[1]	auto[1]	134	1		T1	4		T3	4		T7	1
all_values[8]	auto[0]	auto[0]	57	1		T7	1		T18	2		T20	2
all_values[8]	auto[0]	auto[1]	156	1		T1	1		T3	2		T14	5
all_values[8]	auto[1]	auto[0]	27	1		T1	1		T69	1		T64	1
all_values[8]	auto[1]	auto[1]	122	1		T1	3		T3	6		T7	4
all_values[9]	auto[0]	auto[0]	61	1		T18	2		T20	2		T21	2
all_values[9]	auto[0]	auto[1]	141	1		T3	4		T7	5		T14	2
all_values[9]	auto[1]	auto[0]	25	1		T14	2		T61	1		T68	1
all_values[9]	auto[1]	auto[1]	135	1		T1	5		T3	4		T14	4
all_values[10]	auto[0]	auto[0]	62	1		T1	2		T18	2		T20	2
all_values[10]	auto[0]	auto[1]	124	1		T3	1		T7	1		T14	5
all_values[10]	auto[1]	auto[0]	26	1		T1	3		T7	1		T14	1
all_values[10]	auto[1]	auto[1]	150	1		T3	7		T7	3		T14	2
all_values[11]	auto[0]	auto[0]	63	1		T7	4		T18	2		T20	2
all_values[11]	auto[0]	auto[1]	121	1		T1	1		T3	4		T14	6
all_values[11]	auto[1]	auto[0]	17	1		T7	1		T61	1		T68	2
all_values[11]	auto[1]	auto[1]	161	1		T1	4		T3	4		T14	2
all_values[12]	auto[0]	auto[0]	65	1		T18	2		T20	2		T21	2
all_values[12]	auto[0]	auto[1]	133	1		T1	3		T3	4		T7	1
all_values[12]	auto[1]	auto[0]	25	1		T1	2		T3	1		T61	3
all_values[12]	auto[1]	auto[1]	139	1		T3	3		T7	4		T14	2
all_values[13]	auto[0]	auto[0]	70	1		T1	1		T7	1		T18	2
all_values[13]	auto[0]	auto[1]	134	1		T1	4		T3	4		T7	3
all_values[13]	auto[1]	auto[0]	35	1		T14	1		T60	1		T61	1
all_values[13]	auto[1]	auto[1]	123	1		T3	4		T7	1		T14	5
all_values[14]	auto[0]	auto[0]	63	1		T7	1		T18	2		T20	2
all_values[14]	auto[0]	auto[1]	119	1		T1	4		T3	5		T14	5
all_values[14]	auto[1]	auto[0]	27	1		T3	2		T7	1		T68	2
all_values[14]	auto[1]	auto[1]	153	1		T1	1		T3	1		T7	3
all_values[15]	auto[0]	auto[0]	66	1		T3	2		T18	2		T20	2
all_values[15]	auto[0]	auto[1]	120	1		T3	3		T7	4		T61	5
all_values[15]	auto[1]	auto[0]	37	1		T3	2		T60	4		T69	4
all_values[15]	auto[1]	auto[1]	139	1		T1	5		T3	1		T7	1
all_values[16]	auto[0]	auto[0]	59	1		T7	1		T18	2		T20	2
all_values[16]	auto[0]	auto[1]	108	1		T1	1		T3	3		T14	2
all_values[16]	auto[1]	auto[0]	38	1		T60	5		T68	5		T70	3
all_values[16]	auto[1]	auto[1]	157	1		T1	4		T3	5		T7	4
all_values[17]	auto[0]	auto[0]	67	1		T18	2		T20	2		T21	2
all_values[17]	auto[0]	auto[1]	138	1		T3	6		T7	4		T14	5
all_values[17]	auto[1]	auto[0]	26	1		T14	1		T69	2		T71	1
all_values[17]	auto[1]	auto[1]	131	1		T1	5		T3	2		T7	1