| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 68.17 | 66.21 | 59.64 | 87.37 | 0.00 | 69.99 | 97.77 | 96.22 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 55.46 | 55.46 | 62.25 | 62.25 | 49.15 | 49.15 | 85.38 | 85.38 | 0.00 | 0.00 | 63.19 | 63.19 | 93.85 | 93.85 | 34.41 | 34.41 | /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1421628024 |
| 62.40 | 6.94 | 62.95 | 0.70 | 50.41 | 1.26 | 88.92 | 3.54 | 0.00 | 0.00 | 63.19 | 0.00 | 93.85 | 0.00 | 77.48 | 43.06 | /workspace/coverage/cover_reg_top/16.usbdev_intr_test.571416450 |
| 65.14 | 2.74 | 65.30 | 2.35 | 55.85 | 5.44 | 92.22 | 3.30 | 0.00 | 0.00 | 69.63 | 6.43 | 95.53 | 1.68 | 77.48 | 0.00 | /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3662896154 |
| 67.13 | 1.98 | 65.30 | 0.00 | 58.96 | 3.12 | 95.75 | 3.54 | 0.00 | 0.00 | 69.87 | 0.24 | 96.93 | 1.40 | 83.06 | 5.59 | /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1546037272 |
| 68.19 | 1.06 | 65.30 | 0.00 | 58.96 | 0.00 | 95.99 | 0.24 | 0.00 | 0.00 | 69.87 | 0.00 | 96.93 | 0.00 | 90.27 | 7.21 | /workspace/coverage/cover_reg_top/3.usbdev_intr_test.2922580739 |
| 68.63 | 0.44 | 65.30 | 0.00 | 58.96 | 0.00 | 95.99 | 0.00 | 0.00 | 0.00 | 69.87 | 0.00 | 96.93 | 0.00 | 93.33 | 3.06 | /workspace/coverage/cover_reg_top/42.usbdev_intr_test.3804625635 |
| 68.81 | 0.18 | 65.30 | 0.00 | 58.96 | 0.00 | 95.99 | 0.00 | 0.00 | 0.00 | 69.87 | 0.00 | 96.93 | 0.00 | 94.59 | 1.26 | /workspace/coverage/cover_reg_top/39.usbdev_intr_test.414551071 |
| 68.97 | 0.16 | 65.95 | 0.64 | 59.08 | 0.12 | 96.23 | 0.24 | 0.00 | 0.00 | 69.99 | 0.12 | 96.93 | 0.00 | 94.59 | 0.00 | /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3561430098 |
| 69.10 | 0.13 | 65.95 | 0.00 | 59.17 | 0.09 | 96.23 | 0.00 | 0.00 | 0.00 | 69.99 | 0.00 | 97.77 | 0.84 | 94.59 | 0.00 | /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.385765645 |
| 69.20 | 0.10 | 65.95 | 0.00 | 59.17 | 0.00 | 96.23 | 0.00 | 0.00 | 0.00 | 69.99 | 0.00 | 97.77 | 0.00 | 95.32 | 0.72 | /workspace/coverage/cover_reg_top/10.usbdev_intr_test.968992009 |
| 69.31 | 0.10 | 65.95 | 0.00 | 59.17 | 0.00 | 96.23 | 0.00 | 0.00 | 0.00 | 69.99 | 0.00 | 97.77 | 0.00 | 96.04 | 0.72 | /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1803029602 |
| 69.35 | 0.04 | 65.95 | 0.00 | 59.47 | 0.30 | 96.23 | 0.00 | 0.00 | 0.00 | 69.99 | 0.00 | 97.77 | 0.00 | 96.04 | 0.00 | /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3298321286 |
| 69.38 | 0.03 | 66.14 | 0.19 | 59.47 | 0.00 | 96.23 | 0.00 | 0.00 | 0.00 | 69.99 | 0.00 | 97.77 | 0.00 | 96.04 | 0.00 | /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3115767697 |
| 69.40 | 0.03 | 66.14 | 0.00 | 59.47 | 0.00 | 96.23 | 0.00 | 0.00 | 0.00 | 69.99 | 0.00 | 97.77 | 0.00 | 96.22 | 0.18 | /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1634160835 |
| 69.43 | 0.02 | 66.21 | 0.08 | 59.57 | 0.09 | 96.23 | 0.00 | 0.00 | 0.00 | 69.99 | 0.00 | 97.77 | 0.00 | 96.22 | 0.00 | /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.177589139 |
| 69.43 | 0.01 | 66.21 | 0.00 | 59.61 | 0.05 | 96.23 | 0.00 | 0.00 | 0.00 | 69.99 | 0.00 | 97.77 | 0.00 | 96.22 | 0.00 | /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.20675007 |
| 69.44 | 0.01 | 66.21 | 0.00 | 59.64 | 0.02 | 96.23 | 0.00 | 0.00 | 0.00 | 69.99 | 0.00 | 97.77 | 0.00 | 96.22 | 0.00 | /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3141989670 |
| Name |
|---|
| /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2864723306 |
| /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1171249201 |
| /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2478086360 |
| /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.855187427 |
| /workspace/coverage/cover_reg_top/0.usbdev_intr_test.2629173712 |
| /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3155181428 |
| /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3950934617 |
| /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1700940957 |
| /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2016763435 |
| /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.4001728579 |
| /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.705200048 |
| /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1462472361 |
| /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1695450393 |
| /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1513982392 |
| /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2716887468 |
| /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1143439001 |
| /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.656737547 |
| /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2864575419 |
| /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1418335087 |
| /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.226598989 |
| /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2374035110 |
| /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3339147204 |
| /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3966858316 |
| /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2544799987 |
| /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.740327231 |
| /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3272429146 |
| /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2936025688 |
| /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3137921874 |
| /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2093215148 |
| /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3000431483 |
| /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2148518823 |
| /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3708232495 |
| /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2778443417 |
| /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3670015716 |
| /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1019042192 |
| /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.427972962 |
| /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.783607333 |
| /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2543369447 |
| /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2029683093 |
| /workspace/coverage/cover_reg_top/14.usbdev_intr_test.918750805 |
| /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3030303412 |
| /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2431016802 |
| /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2400388863 |
| /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2916970410 |
| /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3457278519 |
| /workspace/coverage/cover_reg_top/15.usbdev_intr_test.959140268 |
| /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.636405848 |
| /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.359583778 |
| /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.4241146326 |
| /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.614485792 |
| /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1090559875 |
| /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3772806249 |
| /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.819072733 |
| /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3226920870 |
| /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2603929434 |
| /workspace/coverage/cover_reg_top/17.usbdev_intr_test.505396474 |
| /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.569231176 |
| /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3069504090 |
| /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2053580705 |
| /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1953027382 |
| /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3636589870 |
| /workspace/coverage/cover_reg_top/18.usbdev_intr_test.29950137 |
| /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2714966780 |
| /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.646063541 |
| /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1454852187 |
| /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2123626859 |
| /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1320335284 |
| /workspace/coverage/cover_reg_top/19.usbdev_intr_test.727528732 |
| /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.4137942115 |
| /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3752702184 |
| /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2713268448 |
| /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2300688180 |
| /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.2557795414 |
| /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2637850379 |
| /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2279525872 |
| /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2778146343 |
| /workspace/coverage/cover_reg_top/2.usbdev_intr_test.497346 |
| /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1713750655 |
| /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3148766145 |
| /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3316630158 |
| /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2547960836 |
| /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1708183007 |
| /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2528196431 |
| /workspace/coverage/cover_reg_top/21.usbdev_intr_test.3591622168 |
| /workspace/coverage/cover_reg_top/22.usbdev_intr_test.509920671 |
| /workspace/coverage/cover_reg_top/23.usbdev_intr_test.2989692466 |
| /workspace/coverage/cover_reg_top/24.usbdev_intr_test.1504023747 |
| /workspace/coverage/cover_reg_top/25.usbdev_intr_test.734861502 |
| /workspace/coverage/cover_reg_top/26.usbdev_intr_test.433630571 |
| /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2554441665 |
| /workspace/coverage/cover_reg_top/28.usbdev_intr_test.1003668133 |
| /workspace/coverage/cover_reg_top/29.usbdev_intr_test.962163112 |
| /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.836947883 |
| /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3597397433 |
| /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2529389931 |
| /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.175791105 |
| /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.216720475 |
| /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2789369010 |
| /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3094820041 |
| /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3375853666 |
| /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.692711131 |
| /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1757664526 |
| /workspace/coverage/cover_reg_top/30.usbdev_intr_test.1863667661 |
| /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3097111631 |
| /workspace/coverage/cover_reg_top/32.usbdev_intr_test.4028624746 |
| /workspace/coverage/cover_reg_top/33.usbdev_intr_test.17719142 |
| /workspace/coverage/cover_reg_top/34.usbdev_intr_test.4187757448 |
| /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3424034595 |
| /workspace/coverage/cover_reg_top/36.usbdev_intr_test.4078378863 |
| /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1218744969 |
| /workspace/coverage/cover_reg_top/38.usbdev_intr_test.1470771430 |
| /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3698291712 |
| /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2540381173 |
| /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.727575883 |
| /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1590297744 |
| /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3852792395 |
| /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1688782028 |
| /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1050751239 |
| /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.4070177680 |
| /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.68157338 |
| /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3461067432 |
| /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3018789 |
| /workspace/coverage/cover_reg_top/41.usbdev_intr_test.683663128 |
| /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3840496613 |
| /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2965442177 |
| /workspace/coverage/cover_reg_top/45.usbdev_intr_test.3154788952 |
| /workspace/coverage/cover_reg_top/46.usbdev_intr_test.1081640076 |
| /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1079043894 |
| /workspace/coverage/cover_reg_top/48.usbdev_intr_test.4019082073 |
| /workspace/coverage/cover_reg_top/49.usbdev_intr_test.596238369 |
| /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.3218855570 |
| /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1262738026 |
| /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.4074570970 |
| /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2981872096 |
| /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1264538449 |
| /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1931952541 |
| /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2841300960 |
| /workspace/coverage/cover_reg_top/6.usbdev_intr_test.130517183 |
| /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.2891162290 |
| /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2865479691 |
| /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.913985872 |
| /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1201985106 |
| /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1226963463 |
| /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2630481169 |
| /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.922541263 |
| /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1332272137 |
| /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1455544101 |
| /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.21357472 |
| /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1398127547 |
| /workspace/coverage/cover_reg_top/8.usbdev_intr_test.4044168728 |
| /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.338091638 |
| /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2482410227 |
| /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.533741490 |
| /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.4014130687 |
| /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1604781725 |
| /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1984292681 |
| /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.543358270 |
| /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1750236477 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1604781725 | Jun 09 01:05:24 PM PDT 24 | Jun 09 01:05:25 PM PDT 24 | 48420702 ps | ||
| T2 | /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1421628024 | Jun 09 01:05:47 PM PDT 24 | Jun 09 01:05:52 PM PDT 24 | 863455073 ps | ||
| T3 | /workspace/coverage/cover_reg_top/16.usbdev_intr_test.571416450 | Jun 09 01:05:39 PM PDT 24 | Jun 09 01:05:40 PM PDT 24 | 53427488 ps | ||
| T6 | /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2300688180 | Jun 09 01:04:57 PM PDT 24 | Jun 09 01:05:01 PM PDT 24 | 296393092 ps | ||
| T4 | /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.177589139 | Jun 09 01:05:23 PM PDT 24 | Jun 09 01:05:24 PM PDT 24 | 52723177 ps | ||
| T5 | /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.4241146326 | Jun 09 01:05:34 PM PDT 24 | Jun 09 01:05:36 PM PDT 24 | 79342371 ps | ||
| T8 | /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.68157338 | Jun 09 01:05:15 PM PDT 24 | Jun 09 01:05:17 PM PDT 24 | 196974873 ps | ||
| T15 | /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.385765645 | Jun 09 01:05:12 PM PDT 24 | Jun 09 01:05:14 PM PDT 24 | 72387553 ps | ||
| T16 | /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.216720475 | Jun 09 01:05:02 PM PDT 24 | Jun 09 01:05:04 PM PDT 24 | 85363944 ps | ||
| T7 | /workspace/coverage/cover_reg_top/19.usbdev_intr_test.727528732 | Jun 09 01:05:47 PM PDT 24 | Jun 09 01:05:49 PM PDT 24 | 101711375 ps | ||
| T25 | /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3339147204 | Jun 09 01:05:23 PM PDT 24 | Jun 09 01:05:28 PM PDT 24 | 1715602293 ps | ||
| T26 | /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2374035110 | Jun 09 01:05:26 PM PDT 24 | Jun 09 01:05:27 PM PDT 24 | 76371689 ps | ||
| T17 | /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2279525872 | Jun 09 01:04:56 PM PDT 24 | Jun 09 01:04:58 PM PDT 24 | 223076833 ps | ||
| T18 | /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3298321286 | Jun 09 01:05:03 PM PDT 24 | Jun 09 01:05:06 PM PDT 24 | 273307918 ps | ||
| T19 | /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2789369010 | Jun 09 01:05:03 PM PDT 24 | Jun 09 01:05:05 PM PDT 24 | 140771216 ps | ||
| T9 | /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.727575883 | Jun 09 01:05:07 PM PDT 24 | Jun 09 01:05:08 PM PDT 24 | 194038947 ps | ||
| T27 | /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1750236477 | Jun 09 01:05:24 PM PDT 24 | Jun 09 01:05:31 PM PDT 24 | 1356407050 ps | ||
| T20 | /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1546037272 | Jun 09 01:05:24 PM PDT 24 | Jun 09 01:05:28 PM PDT 24 | 275752892 ps | ||
| T21 | /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2981872096 | Jun 09 01:05:12 PM PDT 24 | Jun 09 01:05:14 PM PDT 24 | 183374379 ps | ||
| T14 | /workspace/coverage/cover_reg_top/38.usbdev_intr_test.1470771430 | Jun 09 01:05:54 PM PDT 24 | Jun 09 01:05:55 PM PDT 24 | 35876125 ps | ||
| T60 | /workspace/coverage/cover_reg_top/10.usbdev_intr_test.968992009 | Jun 09 01:05:24 PM PDT 24 | Jun 09 01:05:25 PM PDT 24 | 39209435 ps | ||
| T61 | /workspace/coverage/cover_reg_top/32.usbdev_intr_test.4028624746 | Jun 09 01:05:54 PM PDT 24 | Jun 09 01:05:55 PM PDT 24 | 50339146 ps | ||
| T22 | /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.533741490 | Jun 09 01:05:24 PM PDT 24 | Jun 09 01:05:26 PM PDT 24 | 131980801 ps | ||
| T30 | /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1226963463 | Jun 09 01:05:34 PM PDT 24 | Jun 09 01:05:35 PM PDT 24 | 45062928 ps | ||
| T69 | /workspace/coverage/cover_reg_top/6.usbdev_intr_test.130517183 | Jun 09 01:05:22 PM PDT 24 | Jun 09 01:05:23 PM PDT 24 | 95706979 ps | ||
| T23 | /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1143439001 | Jun 09 01:04:42 PM PDT 24 | Jun 09 01:04:45 PM PDT 24 | 265483546 ps | ||
| T24 | /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2864575419 | Jun 09 01:04:44 PM PDT 24 | Jun 09 01:04:47 PM PDT 24 | 188785497 ps | ||
| T28 | /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.427972962 | Jun 09 01:05:30 PM PDT 24 | Jun 09 01:05:32 PM PDT 24 | 152291766 ps | ||
| T46 | /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1019042192 | Jun 09 01:05:41 PM PDT 24 | Jun 09 01:05:42 PM PDT 24 | 122766966 ps | ||
| T47 | /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2714966780 | Jun 09 01:05:47 PM PDT 24 | Jun 09 01:05:48 PM PDT 24 | 99070516 ps | ||
| T29 | /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.692711131 | Jun 09 01:04:55 PM PDT 24 | Jun 09 01:04:57 PM PDT 24 | 112162990 ps | ||
| T68 | /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3097111631 | Jun 09 01:05:52 PM PDT 24 | Jun 09 01:05:53 PM PDT 24 | 57960689 ps | ||
| T76 | /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1634160835 | Jun 09 01:05:24 PM PDT 24 | Jun 09 01:05:27 PM PDT 24 | 394438193 ps | ||
| T49 | /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3226920870 | Jun 09 01:05:42 PM PDT 24 | Jun 09 01:05:44 PM PDT 24 | 128715065 ps | ||
| T31 | /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3030303412 | Jun 09 01:05:46 PM PDT 24 | Jun 09 01:05:49 PM PDT 24 | 182884145 ps | ||
| T64 | /workspace/coverage/cover_reg_top/42.usbdev_intr_test.3804625635 | Jun 09 01:05:53 PM PDT 24 | Jun 09 01:05:54 PM PDT 24 | 37090963 ps | ||
| T71 | /workspace/coverage/cover_reg_top/15.usbdev_intr_test.959140268 | Jun 09 01:05:34 PM PDT 24 | Jun 09 01:05:35 PM PDT 24 | 69084082 ps | ||
| T62 | /workspace/coverage/cover_reg_top/2.usbdev_intr_test.497346 | Jun 09 01:04:56 PM PDT 24 | Jun 09 01:04:57 PM PDT 24 | 49050174 ps | ||
| T56 | /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1708183007 | Jun 09 01:04:52 PM PDT 24 | Jun 09 01:04:58 PM PDT 24 | 1575542547 ps | ||
| T66 | /workspace/coverage/cover_reg_top/3.usbdev_intr_test.2922580739 | Jun 09 01:04:57 PM PDT 24 | Jun 09 01:04:58 PM PDT 24 | 44468133 ps | ||
| T83 | /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3094820041 | Jun 09 01:04:55 PM PDT 24 | Jun 09 01:04:58 PM PDT 24 | 323544751 ps | ||
| T10 | /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3662896154 | Jun 09 01:04:45 PM PDT 24 | Jun 09 01:04:46 PM PDT 24 | 91891367 ps | ||
| T32 | /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.614485792 | Jun 09 01:05:37 PM PDT 24 | Jun 09 01:05:38 PM PDT 24 | 79022530 ps | ||
| T11 | /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2637850379 | Jun 09 01:04:56 PM PDT 24 | Jun 09 01:04:57 PM PDT 24 | 126271130 ps | ||
| T70 | /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3018789 | Jun 09 01:05:51 PM PDT 24 | Jun 09 01:05:51 PM PDT 24 | 115534015 ps | ||
| T84 | /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2936025688 | Jun 09 01:05:29 PM PDT 24 | Jun 09 01:05:30 PM PDT 24 | 127426279 ps | ||
| T52 | /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3272429146 | Jun 09 01:05:27 PM PDT 24 | Jun 09 01:05:29 PM PDT 24 | 121849730 ps | ||
| T85 | /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.913985872 | Jun 09 01:05:17 PM PDT 24 | Jun 09 01:05:20 PM PDT 24 | 368416897 ps | ||
| T33 | /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.2557795414 | Jun 09 01:04:59 PM PDT 24 | Jun 09 01:05:04 PM PDT 24 | 474402383 ps | ||
| T57 | /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2123626859 | Jun 09 01:05:43 PM PDT 24 | Jun 09 01:05:45 PM PDT 24 | 250829187 ps | ||
| T55 | /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1332272137 | Jun 09 01:05:21 PM PDT 24 | Jun 09 01:05:23 PM PDT 24 | 157279973 ps | ||
| T75 | /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3424034595 | Jun 09 01:05:53 PM PDT 24 | Jun 09 01:05:54 PM PDT 24 | 90772212 ps | ||
| T86 | /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2053580705 | Jun 09 01:05:35 PM PDT 24 | Jun 09 01:05:38 PM PDT 24 | 328069040 ps | ||
| T53 | /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3772806249 | Jun 09 01:05:35 PM PDT 24 | Jun 09 01:05:37 PM PDT 24 | 72361362 ps | ||
| T48 | /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.4074570970 | Jun 09 01:05:13 PM PDT 24 | Jun 09 01:05:15 PM PDT 24 | 338664427 ps | ||
| T87 | /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1695450393 | Jun 09 01:04:50 PM PDT 24 | Jun 09 01:04:51 PM PDT 24 | 39725107 ps | ||
| T58 | /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1418335087 | Jun 09 01:04:44 PM PDT 24 | Jun 09 01:04:47 PM PDT 24 | 448884105 ps | ||
| T88 | /workspace/coverage/cover_reg_top/49.usbdev_intr_test.596238369 | Jun 09 01:06:01 PM PDT 24 | Jun 09 01:06:02 PM PDT 24 | 71507273 ps | ||
| T89 | /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3670015716 | Jun 09 01:05:29 PM PDT 24 | Jun 09 01:05:30 PM PDT 24 | 56720206 ps | ||
| T50 | /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3708232495 | Jun 09 01:05:36 PM PDT 24 | Jun 09 01:05:38 PM PDT 24 | 144764889 ps | ||
| T90 | /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1590297744 | Jun 09 01:05:14 PM PDT 24 | Jun 09 01:05:17 PM PDT 24 | 115066239 ps | ||
| T34 | /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2029683093 | Jun 09 01:05:47 PM PDT 24 | Jun 09 01:05:48 PM PDT 24 | 89705025 ps | ||
| T35 | /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.836947883 | Jun 09 01:05:03 PM PDT 24 | Jun 09 01:05:07 PM PDT 24 | 290619695 ps | ||
| T91 | /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1931952541 | Jun 09 01:05:34 PM PDT 24 | Jun 09 01:05:37 PM PDT 24 | 129726467 ps | ||
| T59 | /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.922541263 | Jun 09 01:05:21 PM PDT 24 | Jun 09 01:05:23 PM PDT 24 | 261610541 ps | ||
| T36 | /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2778443417 | Jun 09 01:05:30 PM PDT 24 | Jun 09 01:05:32 PM PDT 24 | 69550512 ps | ||
| T92 | /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1953027382 | Jun 09 01:05:42 PM PDT 24 | Jun 09 01:05:45 PM PDT 24 | 190011128 ps | ||
| T93 | /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.226598989 | Jun 09 01:05:26 PM PDT 24 | Jun 09 01:05:27 PM PDT 24 | 65669700 ps | ||
| T94 | /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2016763435 | Jun 09 01:04:43 PM PDT 24 | Jun 09 01:04:47 PM PDT 24 | 644109961 ps | ||
| T95 | /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.21357472 | Jun 09 01:05:24 PM PDT 24 | Jun 09 01:05:25 PM PDT 24 | 88593497 ps | ||
| T37 | /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.855187427 | Jun 09 01:04:39 PM PDT 24 | Jun 09 01:04:40 PM PDT 24 | 71979817 ps | ||
| T38 | /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3852792395 | Jun 09 01:05:10 PM PDT 24 | Jun 09 01:05:12 PM PDT 24 | 63269706 ps | ||
| T67 | /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1513982392 | Jun 09 01:04:45 PM PDT 24 | Jun 09 01:04:46 PM PDT 24 | 72213618 ps | ||
| T77 | /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1803029602 | Jun 09 01:05:19 PM PDT 24 | Jun 09 01:05:24 PM PDT 24 | 1123103482 ps | ||
| T96 | /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1171249201 | Jun 09 01:04:42 PM PDT 24 | Jun 09 01:04:47 PM PDT 24 | 686837778 ps | ||
| T73 | /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2630481169 | Jun 09 01:05:19 PM PDT 24 | Jun 09 01:05:20 PM PDT 24 | 48408765 ps | ||
| T97 | /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.4070177680 | Jun 09 01:05:09 PM PDT 24 | Jun 09 01:05:14 PM PDT 24 | 708582707 ps | ||
| T98 | /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.636405848 | Jun 09 01:05:40 PM PDT 24 | Jun 09 01:05:42 PM PDT 24 | 98899396 ps | ||
| T63 | /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1984292681 | Jun 09 01:05:22 PM PDT 24 | Jun 09 01:05:24 PM PDT 24 | 118806846 ps | ||
| T99 | /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2841300960 | Jun 09 01:05:16 PM PDT 24 | Jun 09 01:05:17 PM PDT 24 | 42156909 ps | ||
| T51 | /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1264538449 | Jun 09 01:05:12 PM PDT 24 | Jun 09 01:05:17 PM PDT 24 | 832287342 ps | ||
| T100 | /workspace/coverage/cover_reg_top/22.usbdev_intr_test.509920671 | Jun 09 01:05:46 PM PDT 24 | Jun 09 01:05:47 PM PDT 24 | 108381018 ps | ||
| T101 | /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3375853666 | Jun 09 01:05:00 PM PDT 24 | Jun 09 01:05:01 PM PDT 24 | 196527331 ps | ||
| T65 | /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1079043894 | Jun 09 01:05:52 PM PDT 24 | Jun 09 01:05:53 PM PDT 24 | 38123654 ps | ||
| T39 | /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3636589870 | Jun 09 01:05:48 PM PDT 24 | Jun 09 01:05:49 PM PDT 24 | 75971173 ps | ||
| T40 | /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2716887468 | Jun 09 01:04:42 PM PDT 24 | Jun 09 01:04:43 PM PDT 24 | 105965962 ps | ||
| T41 | /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1713750655 | Jun 09 01:04:55 PM PDT 24 | Jun 09 01:04:57 PM PDT 24 | 116515712 ps | ||
| T102 | /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.175791105 | Jun 09 01:05:04 PM PDT 24 | Jun 09 01:05:06 PM PDT 24 | 139157507 ps | ||
| T103 | /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2864723306 | Jun 09 01:04:44 PM PDT 24 | Jun 09 01:04:47 PM PDT 24 | 204687283 ps | ||
| T104 | /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1090559875 | Jun 09 01:05:39 PM PDT 24 | Jun 09 01:05:41 PM PDT 24 | 346106817 ps | ||
| T74 | /workspace/coverage/cover_reg_top/8.usbdev_intr_test.4044168728 | Jun 09 01:05:22 PM PDT 24 | Jun 09 01:05:23 PM PDT 24 | 42459165 ps | ||
| T12 | /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2529389931 | Jun 09 01:05:03 PM PDT 24 | Jun 09 01:05:04 PM PDT 24 | 176900728 ps | ||
| T105 | /workspace/coverage/cover_reg_top/45.usbdev_intr_test.3154788952 | Jun 09 01:05:52 PM PDT 24 | Jun 09 01:05:53 PM PDT 24 | 88901825 ps | ||
| T42 | /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3155181428 | Jun 09 01:04:39 PM PDT 24 | Jun 09 01:04:41 PM PDT 24 | 59337840 ps | ||
| T72 | /workspace/coverage/cover_reg_top/39.usbdev_intr_test.414551071 | Jun 09 01:05:52 PM PDT 24 | Jun 09 01:05:53 PM PDT 24 | 34113505 ps | ||
| T106 | /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.2891162290 | Jun 09 01:05:17 PM PDT 24 | Jun 09 01:05:18 PM PDT 24 | 76352241 ps | ||
| T54 | /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.20675007 | Jun 09 01:05:30 PM PDT 24 | Jun 09 01:05:33 PM PDT 24 | 258903914 ps | ||
| T107 | /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3148766145 | Jun 09 01:04:55 PM PDT 24 | Jun 09 01:04:59 PM PDT 24 | 528792934 ps | ||
| T108 | /workspace/coverage/cover_reg_top/23.usbdev_intr_test.2989692466 | Jun 09 01:05:47 PM PDT 24 | Jun 09 01:05:48 PM PDT 24 | 58615530 ps | ||
| T82 | /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.783607333 | Jun 09 01:05:29 PM PDT 24 | Jun 09 01:05:34 PM PDT 24 | 839891411 ps | ||
| T109 | /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3950934617 | Jun 09 01:04:40 PM PDT 24 | Jun 09 01:04:44 PM PDT 24 | 170852280 ps | ||
| T110 | /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3840496613 | Jun 09 01:05:59 PM PDT 24 | Jun 09 01:06:00 PM PDT 24 | 39031149 ps | ||
| T111 | /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2148518823 | Jun 09 01:05:32 PM PDT 24 | Jun 09 01:05:37 PM PDT 24 | 744279157 ps | ||
| T112 | /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2965442177 | Jun 09 01:05:54 PM PDT 24 | Jun 09 01:05:55 PM PDT 24 | 35238512 ps | ||
| T113 | /workspace/coverage/cover_reg_top/17.usbdev_intr_test.505396474 | Jun 09 01:05:37 PM PDT 24 | Jun 09 01:05:39 PM PDT 24 | 64839249 ps | ||
| T114 | /workspace/coverage/cover_reg_top/36.usbdev_intr_test.4078378863 | Jun 09 01:05:52 PM PDT 24 | Jun 09 01:05:53 PM PDT 24 | 41815029 ps | ||
| T43 | /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3597397433 | Jun 09 01:05:02 PM PDT 24 | Jun 09 01:05:11 PM PDT 24 | 953469016 ps | ||
| T115 | /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3966858316 | Jun 09 01:05:29 PM PDT 24 | Jun 09 01:05:30 PM PDT 24 | 53961918 ps | ||
| T116 | /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.3218855570 | Jun 09 01:05:13 PM PDT 24 | Jun 09 01:05:15 PM PDT 24 | 107574761 ps | ||
| T117 | /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3115767697 | Jun 09 01:04:40 PM PDT 24 | Jun 09 01:04:42 PM PDT 24 | 172232197 ps | ||
| T118 | /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2400388863 | Jun 09 01:05:46 PM PDT 24 | Jun 09 01:05:49 PM PDT 24 | 373694906 ps | ||
| T119 | /workspace/coverage/cover_reg_top/34.usbdev_intr_test.4187757448 | Jun 09 01:05:54 PM PDT 24 | Jun 09 01:05:55 PM PDT 24 | 49414220 ps | ||
| T81 | /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3461067432 | Jun 09 01:05:07 PM PDT 24 | Jun 09 01:05:12 PM PDT 24 | 955039121 ps | ||
| T44 | /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1050751239 | Jun 09 01:05:08 PM PDT 24 | Jun 09 01:05:10 PM PDT 24 | 118615499 ps | ||
| T45 | /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2540381173 | Jun 09 01:05:08 PM PDT 24 | Jun 09 01:05:17 PM PDT 24 | 1106476131 ps | ||
| T120 | /workspace/coverage/cover_reg_top/21.usbdev_intr_test.3591622168 | Jun 09 01:05:48 PM PDT 24 | Jun 09 01:05:49 PM PDT 24 | 31905341 ps | ||
| T121 | /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3316630158 | Jun 09 01:04:55 PM PDT 24 | Jun 09 01:04:57 PM PDT 24 | 157353202 ps | ||
| T122 | /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2603929434 | Jun 09 01:05:40 PM PDT 24 | Jun 09 01:05:41 PM PDT 24 | 64889504 ps | ||
| T123 | /workspace/coverage/cover_reg_top/30.usbdev_intr_test.1863667661 | Jun 09 01:05:47 PM PDT 24 | Jun 09 01:05:48 PM PDT 24 | 40081490 ps | ||
| T124 | /workspace/coverage/cover_reg_top/46.usbdev_intr_test.1081640076 | Jun 09 01:05:56 PM PDT 24 | Jun 09 01:05:57 PM PDT 24 | 53924247 ps | ||
| T125 | /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.4001728579 | Jun 09 01:04:52 PM PDT 24 | Jun 09 01:04:56 PM PDT 24 | 327349765 ps | ||
| T126 | /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.569231176 | Jun 09 01:05:46 PM PDT 24 | Jun 09 01:05:47 PM PDT 24 | 103572049 ps | ||
| T127 | /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.338091638 | Jun 09 01:05:21 PM PDT 24 | Jun 09 01:05:23 PM PDT 24 | 135901729 ps | ||
| T79 | /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1454852187 | Jun 09 01:05:43 PM PDT 24 | Jun 09 01:05:45 PM PDT 24 | 528082581 ps | ||
| T128 | /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2528196431 | Jun 09 01:05:42 PM PDT 24 | Jun 09 01:05:43 PM PDT 24 | 59987538 ps | ||
| T129 | /workspace/coverage/cover_reg_top/14.usbdev_intr_test.918750805 | Jun 09 01:05:36 PM PDT 24 | Jun 09 01:05:37 PM PDT 24 | 64458733 ps | ||
| T13 | /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3561430098 | Jun 09 01:04:42 PM PDT 24 | Jun 09 01:04:43 PM PDT 24 | 111884190 ps | ||
| T130 | /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3698291712 | Jun 09 01:05:07 PM PDT 24 | Jun 09 01:05:11 PM PDT 24 | 355841890 ps | ||
| T131 | /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1262738026 | Jun 09 01:05:14 PM PDT 24 | Jun 09 01:05:15 PM PDT 24 | 40869718 ps | ||
| T132 | /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.4014130687 | Jun 09 01:05:24 PM PDT 24 | Jun 09 01:05:25 PM PDT 24 | 119853406 ps | ||
| T133 | /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3000431483 | Jun 09 01:05:32 PM PDT 24 | Jun 09 01:05:34 PM PDT 24 | 150042403 ps | ||
| T134 | /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2431016802 | Jun 09 01:05:36 PM PDT 24 | Jun 09 01:05:39 PM PDT 24 | 263486866 ps | ||
| T135 | /workspace/coverage/cover_reg_top/28.usbdev_intr_test.1003668133 | Jun 09 01:05:47 PM PDT 24 | Jun 09 01:05:48 PM PDT 24 | 78698458 ps | ||
| T136 | /workspace/coverage/cover_reg_top/33.usbdev_intr_test.17719142 | Jun 09 01:05:53 PM PDT 24 | Jun 09 01:05:54 PM PDT 24 | 34920034 ps | ||
| T137 | /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2865479691 | Jun 09 01:05:16 PM PDT 24 | Jun 09 01:05:19 PM PDT 24 | 105900722 ps | ||
| T138 | /workspace/coverage/cover_reg_top/18.usbdev_intr_test.29950137 | Jun 09 01:05:43 PM PDT 24 | Jun 09 01:05:44 PM PDT 24 | 37515136 ps | ||
| T139 | /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3752702184 | Jun 09 01:05:41 PM PDT 24 | Jun 09 01:05:44 PM PDT 24 | 290085688 ps | ||
| T140 | /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3141989670 | Jun 09 01:05:28 PM PDT 24 | Jun 09 01:05:30 PM PDT 24 | 235640992 ps | ||
| T141 | /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2554441665 | Jun 09 01:05:46 PM PDT 24 | Jun 09 01:05:48 PM PDT 24 | 54767161 ps | ||
| T142 | /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2916970410 | Jun 09 01:05:46 PM PDT 24 | Jun 09 01:05:48 PM PDT 24 | 202670281 ps | ||
| T143 | /workspace/coverage/cover_reg_top/0.usbdev_intr_test.2629173712 | Jun 09 01:04:41 PM PDT 24 | Jun 09 01:04:42 PM PDT 24 | 122936101 ps | ||
| T144 | /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3137921874 | Jun 09 01:05:29 PM PDT 24 | Jun 09 01:05:30 PM PDT 24 | 53262124 ps | ||
| T145 | /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2544799987 | Jun 09 01:05:35 PM PDT 24 | Jun 09 01:05:36 PM PDT 24 | 46473637 ps | ||
| T146 | /workspace/coverage/cover_reg_top/29.usbdev_intr_test.962163112 | Jun 09 01:05:53 PM PDT 24 | Jun 09 01:05:54 PM PDT 24 | 37227551 ps | ||
| T147 | /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.705200048 | Jun 09 01:04:49 PM PDT 24 | Jun 09 01:04:54 PM PDT 24 | 1097792612 ps | ||
| T148 | /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.543358270 | Jun 09 01:05:26 PM PDT 24 | Jun 09 01:05:27 PM PDT 24 | 77115346 ps | ||
| T149 | /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.646063541 | Jun 09 01:05:42 PM PDT 24 | Jun 09 01:05:45 PM PDT 24 | 237456422 ps | ||
| T150 | /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2093215148 | Jun 09 01:05:27 PM PDT 24 | Jun 09 01:05:27 PM PDT 24 | 47422183 ps | ||
| T151 | /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3069504090 | Jun 09 01:05:47 PM PDT 24 | Jun 09 01:05:49 PM PDT 24 | 106873145 ps | ||
| T152 | /workspace/coverage/cover_reg_top/48.usbdev_intr_test.4019082073 | Jun 09 01:05:57 PM PDT 24 | Jun 09 01:05:58 PM PDT 24 | 43822922 ps | ||
| T153 | /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2482410227 | Jun 09 01:05:16 PM PDT 24 | Jun 09 01:05:19 PM PDT 24 | 100645432 ps | ||
| T154 | /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2778146343 | Jun 09 01:04:56 PM PDT 24 | Jun 09 01:04:57 PM PDT 24 | 57767889 ps | ||
| T155 | /workspace/coverage/cover_reg_top/25.usbdev_intr_test.734861502 | Jun 09 01:05:47 PM PDT 24 | Jun 09 01:05:48 PM PDT 24 | 62183438 ps | ||
| T156 | /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1398127547 | Jun 09 01:05:18 PM PDT 24 | Jun 09 01:05:20 PM PDT 24 | 76745930 ps | ||
| T157 | /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2543369447 | Jun 09 01:05:34 PM PDT 24 | Jun 09 01:05:35 PM PDT 24 | 143102498 ps | ||
| T158 | /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1700940957 | Jun 09 01:04:44 PM PDT 24 | Jun 09 01:04:46 PM PDT 24 | 289136095 ps | ||
| T159 | /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1320335284 | Jun 09 01:05:44 PM PDT 24 | Jun 09 01:05:45 PM PDT 24 | 44440304 ps | ||
| T160 | /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.656737547 | Jun 09 01:04:50 PM PDT 24 | Jun 09 01:04:51 PM PDT 24 | 89963639 ps | ||
| T161 | /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.740327231 | Jun 09 01:05:29 PM PDT 24 | Jun 09 01:05:30 PM PDT 24 | 91117128 ps | ||
| T162 | /workspace/coverage/cover_reg_top/26.usbdev_intr_test.433630571 | Jun 09 01:05:48 PM PDT 24 | Jun 09 01:05:49 PM PDT 24 | 76106450 ps | ||
| T163 | /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1218744969 | Jun 09 01:05:53 PM PDT 24 | Jun 09 01:05:54 PM PDT 24 | 33348611 ps | ||
| T78 | /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2713268448 | Jun 09 01:05:45 PM PDT 24 | Jun 09 01:05:51 PM PDT 24 | 1583366239 ps | ||
| T164 | /workspace/coverage/cover_reg_top/24.usbdev_intr_test.1504023747 | Jun 09 01:05:47 PM PDT 24 | Jun 09 01:05:48 PM PDT 24 | 35942627 ps | ||
| T165 | /workspace/coverage/cover_reg_top/41.usbdev_intr_test.683663128 | Jun 09 01:05:53 PM PDT 24 | Jun 09 01:05:55 PM PDT 24 | 49789489 ps | ||
| T80 | /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.819072733 | Jun 09 01:05:39 PM PDT 24 | Jun 09 01:05:45 PM PDT 24 | 1310786583 ps | ||
| T166 | /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1688782028 | Jun 09 01:05:07 PM PDT 24 | Jun 09 01:05:07 PM PDT 24 | 33347659 ps | ||
| T167 | /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.4137942115 | Jun 09 01:05:43 PM PDT 24 | Jun 09 01:05:45 PM PDT 24 | 213776357 ps | ||
| T168 | /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1455544101 | Jun 09 01:05:17 PM PDT 24 | Jun 09 01:05:20 PM PDT 24 | 397958686 ps | ||
| T169 | /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2478086360 | Jun 09 01:04:45 PM PDT 24 | Jun 09 01:04:46 PM PDT 24 | 64342659 ps | ||
| T170 | /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1201985106 | Jun 09 01:05:22 PM PDT 24 | Jun 09 01:05:23 PM PDT 24 | 74113587 ps | ||
| T171 | /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3457278519 | Jun 09 01:05:35 PM PDT 24 | Jun 09 01:05:36 PM PDT 24 | 66569471 ps | ||
| T172 | /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.359583778 | Jun 09 01:05:36 PM PDT 24 | Jun 09 01:05:39 PM PDT 24 | 95579804 ps | ||
| T173 | /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1757664526 | Jun 09 01:04:59 PM PDT 24 | Jun 09 01:05:04 PM PDT 24 | 681439300 ps | ||
| T174 | /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2547960836 | Jun 09 01:05:39 PM PDT 24 | Jun 09 01:05:43 PM PDT 24 | 298996721 ps | ||
| T175 | /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1462472361 | Jun 09 01:04:49 PM PDT 24 | Jun 09 01:04:51 PM PDT 24 | 146586266 ps |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1421628024 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 863455073 ps |
| CPU time | 5.09 seconds |
| Started | Jun 09 01:05:47 PM PDT 24 |
| Finished | Jun 09 01:05:52 PM PDT 24 |
| Peak memory | 205008 kb |
| Host | smart-cbe4ed64-997d-44c0-bc71-6625fc7a5931 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1421628024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.1421628024 |
| Directory | /workspace/15.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_intr_test.571416450 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 53427488 ps |
| CPU time | 0.71 seconds |
| Started | Jun 09 01:05:39 PM PDT 24 |
| Finished | Jun 09 01:05:40 PM PDT 24 |
| Peak memory | 204624 kb |
| Host | smart-ddaba5a6-ecd0-421f-99bf-356d7b472c0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=571416450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.571416450 |
| Directory | /workspace/16.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3662896154 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 91891367 ps |
| CPU time | 0.93 seconds |
| Started | Jun 09 01:04:45 PM PDT 24 |
| Finished | Jun 09 01:04:46 PM PDT 24 |
| Peak memory | 204716 kb |
| Host | smart-58d6f71d-0a30-4239-a096-0b6362933997 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3662896154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.3662896154 |
| Directory | /workspace/1.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1546037272 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 275752892 ps |
| CPU time | 3.37 seconds |
| Started | Jun 09 01:05:24 PM PDT 24 |
| Finished | Jun 09 01:05:28 PM PDT 24 |
| Peak memory | 220864 kb |
| Host | smart-98c58e9e-90de-4751-b41a-76f21434b9af |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1546037272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.1546037272 |
| Directory | /workspace/10.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_intr_test.2922580739 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 44468133 ps |
| CPU time | 0.69 seconds |
| Started | Jun 09 01:04:57 PM PDT 24 |
| Finished | Jun 09 01:04:58 PM PDT 24 |
| Peak memory | 204628 kb |
| Host | smart-e431abed-3c8b-4d02-a239-9c7a750f5e01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2922580739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.2922580739 |
| Directory | /workspace/3.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.usbdev_intr_test.3804625635 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 37090963 ps |
| CPU time | 0.69 seconds |
| Started | Jun 09 01:05:53 PM PDT 24 |
| Finished | Jun 09 01:05:54 PM PDT 24 |
| Peak memory | 204624 kb |
| Host | smart-e238f717-bbf5-4963-8ac8-fdd4a12a857e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3804625635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.3804625635 |
| Directory | /workspace/42.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.usbdev_intr_test.414551071 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 34113505 ps |
| CPU time | 0.66 seconds |
| Started | Jun 09 01:05:52 PM PDT 24 |
| Finished | Jun 09 01:05:53 PM PDT 24 |
| Peak memory | 204624 kb |
| Host | smart-70d80b20-8feb-4006-91d8-6a9e932b77ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=414551071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.414551071 |
| Directory | /workspace/39.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3561430098 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 111884190 ps |
| CPU time | 1.01 seconds |
| Started | Jun 09 01:04:42 PM PDT 24 |
| Finished | Jun 09 01:04:43 PM PDT 24 |
| Peak memory | 204712 kb |
| Host | smart-d7ac79ed-454f-4d2c-a977-fbde3e027c4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3561430098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.3561430098 |
| Directory | /workspace/0.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.385765645 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 72387553 ps |
| CPU time | 1.07 seconds |
| Started | Jun 09 01:05:12 PM PDT 24 |
| Finished | Jun 09 01:05:14 PM PDT 24 |
| Peak memory | 204972 kb |
| Host | smart-7bfd3782-3807-4c18-9c33-46dd2cc8a08d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=385765645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.385765645 |
| Directory | /workspace/5.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_intr_test.968992009 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 39209435 ps |
| CPU time | 0.66 seconds |
| Started | Jun 09 01:05:24 PM PDT 24 |
| Finished | Jun 09 01:05:25 PM PDT 24 |
| Peak memory | 204620 kb |
| Host | smart-4e52d190-22c3-47e1-8358-88e4966acd49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=968992009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.968992009 |
| Directory | /workspace/10.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1803029602 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1123103482 ps |
| CPU time | 4.96 seconds |
| Started | Jun 09 01:05:19 PM PDT 24 |
| Finished | Jun 09 01:05:24 PM PDT 24 |
| Peak memory | 204928 kb |
| Host | smart-aaa34dac-10ec-4561-975b-684af49df60d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1803029602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.1803029602 |
| Directory | /workspace/8.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3298321286 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 273307918 ps |
| CPU time | 2.78 seconds |
| Started | Jun 09 01:05:03 PM PDT 24 |
| Finished | Jun 09 01:05:06 PM PDT 24 |
| Peak memory | 205016 kb |
| Host | smart-2b9917ff-afb0-4df9-8a62-8daad6639502 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3298321286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.3298321286 |
| Directory | /workspace/4.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3115767697 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 172232197 ps |
| CPU time | 1.92 seconds |
| Started | Jun 09 01:04:40 PM PDT 24 |
| Finished | Jun 09 01:04:42 PM PDT 24 |
| Peak memory | 220624 kb |
| Host | smart-0d999c76-5e21-4445-baeb-c7f1ca13d454 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3115767697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.3115767697 |
| Directory | /workspace/0.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1634160835 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 394438193 ps |
| CPU time | 2.68 seconds |
| Started | Jun 09 01:05:24 PM PDT 24 |
| Finished | Jun 09 01:05:27 PM PDT 24 |
| Peak memory | 204972 kb |
| Host | smart-f1be2242-ce7a-413c-a2a4-e0aa67e200b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1634160835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.1634160835 |
| Directory | /workspace/11.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.177589139 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 52723177 ps |
| CPU time | 1.11 seconds |
| Started | Jun 09 01:05:23 PM PDT 24 |
| Finished | Jun 09 01:05:24 PM PDT 24 |
| Peak memory | 214896 kb |
| Host | smart-9734c007-4e7f-4248-a47c-a9c0c91461e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177589139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbde v_csr_mem_rw_with_rand_reset.177589139 |
| Directory | /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.20675007 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 258903914 ps |
| CPU time | 2.55 seconds |
| Started | Jun 09 01:05:30 PM PDT 24 |
| Finished | Jun 09 01:05:33 PM PDT 24 |
| Peak memory | 214208 kb |
| Host | smart-27010aff-e6a8-448c-b9a2-223c54fc2a1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=20675007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.20675007 |
| Directory | /workspace/12.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3141989670 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 235640992 ps |
| CPU time | 1.86 seconds |
| Started | Jun 09 01:05:28 PM PDT 24 |
| Finished | Jun 09 01:05:30 PM PDT 24 |
| Peak memory | 213136 kb |
| Host | smart-a372f824-67fe-4724-a8c0-7c5ff2aa1060 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141989670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd ev_csr_mem_rw_with_rand_reset.3141989670 |
| Directory | /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2864723306 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 204687283 ps |
| CPU time | 2.16 seconds |
| Started | Jun 09 01:04:44 PM PDT 24 |
| Finished | Jun 09 01:04:47 PM PDT 24 |
| Peak memory | 204972 kb |
| Host | smart-248bfa5b-e651-4a36-bbd7-7d256861fba2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2864723306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.2864723306 |
| Directory | /workspace/0.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1171249201 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 686837778 ps |
| CPU time | 4.57 seconds |
| Started | Jun 09 01:04:42 PM PDT 24 |
| Finished | Jun 09 01:04:47 PM PDT 24 |
| Peak memory | 204920 kb |
| Host | smart-db70652f-63bd-4773-9cee-f68be7b356e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1171249201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.1171249201 |
| Directory | /workspace/0.usbdev_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2478086360 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 64342659 ps |
| CPU time | 1.38 seconds |
| Started | Jun 09 01:04:45 PM PDT 24 |
| Finished | Jun 09 01:04:46 PM PDT 24 |
| Peak memory | 213156 kb |
| Host | smart-095ee9fa-c70d-4fa3-aad5-e9c6b6fa7d7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478086360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde v_csr_mem_rw_with_rand_reset.2478086360 |
| Directory | /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.855187427 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 71979817 ps |
| CPU time | 0.86 seconds |
| Started | Jun 09 01:04:39 PM PDT 24 |
| Finished | Jun 09 01:04:40 PM PDT 24 |
| Peak memory | 204716 kb |
| Host | smart-99159b49-9de6-4665-aba8-a6cd696b5200 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=855187427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.855187427 |
| Directory | /workspace/0.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_intr_test.2629173712 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 122936101 ps |
| CPU time | 0.73 seconds |
| Started | Jun 09 01:04:41 PM PDT 24 |
| Finished | Jun 09 01:04:42 PM PDT 24 |
| Peak memory | 204620 kb |
| Host | smart-239e9526-2fcf-480c-b408-14694bd15f87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2629173712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.2629173712 |
| Directory | /workspace/0.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3155181428 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 59337840 ps |
| CPU time | 1.42 seconds |
| Started | Jun 09 01:04:39 PM PDT 24 |
| Finished | Jun 09 01:04:41 PM PDT 24 |
| Peak memory | 213148 kb |
| Host | smart-c70c19c3-7376-4669-8451-9a6d764ef613 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3155181428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.3155181428 |
| Directory | /workspace/0.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3950934617 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 170852280 ps |
| CPU time | 3.82 seconds |
| Started | Jun 09 01:04:40 PM PDT 24 |
| Finished | Jun 09 01:04:44 PM PDT 24 |
| Peak memory | 204896 kb |
| Host | smart-782fe2b5-a858-4f99-a1f2-70073f95cdb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3950934617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.3950934617 |
| Directory | /workspace/0.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1700940957 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 289136095 ps |
| CPU time | 1.84 seconds |
| Started | Jun 09 01:04:44 PM PDT 24 |
| Finished | Jun 09 01:04:46 PM PDT 24 |
| Peak memory | 204960 kb |
| Host | smart-4df4dc16-d587-46e9-b506-4a49ea311fcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1700940957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.1700940957 |
| Directory | /workspace/0.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2016763435 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 644109961 ps |
| CPU time | 3.17 seconds |
| Started | Jun 09 01:04:43 PM PDT 24 |
| Finished | Jun 09 01:04:47 PM PDT 24 |
| Peak memory | 204984 kb |
| Host | smart-809c5471-fdee-4138-bb4f-3b7b3f09c490 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2016763435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.2016763435 |
| Directory | /workspace/0.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.4001728579 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 327349765 ps |
| CPU time | 3.45 seconds |
| Started | Jun 09 01:04:52 PM PDT 24 |
| Finished | Jun 09 01:04:56 PM PDT 24 |
| Peak memory | 204928 kb |
| Host | smart-06cf9fda-bdd3-4526-a45a-54a8bbc9a364 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=4001728579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.4001728579 |
| Directory | /workspace/1.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.705200048 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 1097792612 ps |
| CPU time | 4.89 seconds |
| Started | Jun 09 01:04:49 PM PDT 24 |
| Finished | Jun 09 01:04:54 PM PDT 24 |
| Peak memory | 204968 kb |
| Host | smart-e80c6d70-46c6-4f77-8860-3cee37960111 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=705200048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.705200048 |
| Directory | /workspace/1.usbdev_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1462472361 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 146586266 ps |
| CPU time | 1.89 seconds |
| Started | Jun 09 01:04:49 PM PDT 24 |
| Finished | Jun 09 01:04:51 PM PDT 24 |
| Peak memory | 213216 kb |
| Host | smart-3e603173-4e0d-472c-8a77-387febd99125 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462472361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde v_csr_mem_rw_with_rand_reset.1462472361 |
| Directory | /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1695450393 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 39725107 ps |
| CPU time | 0.77 seconds |
| Started | Jun 09 01:04:50 PM PDT 24 |
| Finished | Jun 09 01:04:51 PM PDT 24 |
| Peak memory | 204692 kb |
| Host | smart-df43e5b3-fd83-449d-a0e4-32e1790960b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1695450393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.1695450393 |
| Directory | /workspace/1.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1513982392 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 72213618 ps |
| CPU time | 0.71 seconds |
| Started | Jun 09 01:04:45 PM PDT 24 |
| Finished | Jun 09 01:04:46 PM PDT 24 |
| Peak memory | 204636 kb |
| Host | smart-9c271575-dbc0-4656-a8c4-da5667dbbf57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1513982392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.1513982392 |
| Directory | /workspace/1.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2716887468 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 105965962 ps |
| CPU time | 1.41 seconds |
| Started | Jun 09 01:04:42 PM PDT 24 |
| Finished | Jun 09 01:04:43 PM PDT 24 |
| Peak memory | 213148 kb |
| Host | smart-ac4bf40b-c5f2-4fd9-9bc1-a9095028cb89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2716887468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2716887468 |
| Directory | /workspace/1.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1143439001 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 265483546 ps |
| CPU time | 2.58 seconds |
| Started | Jun 09 01:04:42 PM PDT 24 |
| Finished | Jun 09 01:04:45 PM PDT 24 |
| Peak memory | 204948 kb |
| Host | smart-1f4f9445-cc90-4e0b-b12f-b44367145337 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1143439001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.1143439001 |
| Directory | /workspace/1.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.656737547 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 89963639 ps |
| CPU time | 1.11 seconds |
| Started | Jun 09 01:04:50 PM PDT 24 |
| Finished | Jun 09 01:04:51 PM PDT 24 |
| Peak memory | 204868 kb |
| Host | smart-99c50b72-deb8-4918-b6d0-2af1fc70767a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=656737547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.656737547 |
| Directory | /workspace/1.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2864575419 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 188785497 ps |
| CPU time | 2.45 seconds |
| Started | Jun 09 01:04:44 PM PDT 24 |
| Finished | Jun 09 01:04:47 PM PDT 24 |
| Peak memory | 220668 kb |
| Host | smart-3c2e91af-cc23-4538-a3d3-7a38ebe1e434 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2864575419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.2864575419 |
| Directory | /workspace/1.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1418335087 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 448884105 ps |
| CPU time | 2.77 seconds |
| Started | Jun 09 01:04:44 PM PDT 24 |
| Finished | Jun 09 01:04:47 PM PDT 24 |
| Peak memory | 204936 kb |
| Host | smart-e92944d5-6a0f-47ff-8f34-bf72ff5a0dba |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1418335087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.1418335087 |
| Directory | /workspace/1.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.226598989 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 65669700 ps |
| CPU time | 0.98 seconds |
| Started | Jun 09 01:05:26 PM PDT 24 |
| Finished | Jun 09 01:05:27 PM PDT 24 |
| Peak memory | 204972 kb |
| Host | smart-bfc38464-0c86-4922-b960-c25f97200e79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=226598989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.226598989 |
| Directory | /workspace/10.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2374035110 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 76371689 ps |
| CPU time | 1.12 seconds |
| Started | Jun 09 01:05:26 PM PDT 24 |
| Finished | Jun 09 01:05:27 PM PDT 24 |
| Peak memory | 204936 kb |
| Host | smart-00ef0075-d257-4ef5-a6e9-ccac92110af4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2374035110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.2374035110 |
| Directory | /workspace/10.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3339147204 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1715602293 ps |
| CPU time | 5.1 seconds |
| Started | Jun 09 01:05:23 PM PDT 24 |
| Finished | Jun 09 01:05:28 PM PDT 24 |
| Peak memory | 204880 kb |
| Host | smart-cf728cb0-8694-4cbe-b9b0-ce5d917cd1fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3339147204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.3339147204 |
| Directory | /workspace/10.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3966858316 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 53961918 ps |
| CPU time | 0.84 seconds |
| Started | Jun 09 01:05:29 PM PDT 24 |
| Finished | Jun 09 01:05:30 PM PDT 24 |
| Peak memory | 204744 kb |
| Host | smart-667b4518-955b-4484-9ed0-c3feadf22799 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3966858316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.3966858316 |
| Directory | /workspace/11.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2544799987 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 46473637 ps |
| CPU time | 0.67 seconds |
| Started | Jun 09 01:05:35 PM PDT 24 |
| Finished | Jun 09 01:05:36 PM PDT 24 |
| Peak memory | 204664 kb |
| Host | smart-355ccdaf-4cd2-4fc6-881c-23ba75e86290 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2544799987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.2544799987 |
| Directory | /workspace/11.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.740327231 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 91117128 ps |
| CPU time | 1.17 seconds |
| Started | Jun 09 01:05:29 PM PDT 24 |
| Finished | Jun 09 01:05:30 PM PDT 24 |
| Peak memory | 204964 kb |
| Host | smart-94a20aa3-1d2e-41fa-a405-c1b27f34a7fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=740327231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.740327231 |
| Directory | /workspace/11.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3272429146 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 121849730 ps |
| CPU time | 1.56 seconds |
| Started | Jun 09 01:05:27 PM PDT 24 |
| Finished | Jun 09 01:05:29 PM PDT 24 |
| Peak memory | 204984 kb |
| Host | smart-a7417ae3-d709-4fee-91fa-c4a08508b728 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3272429146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.3272429146 |
| Directory | /workspace/11.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2936025688 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 127426279 ps |
| CPU time | 1.26 seconds |
| Started | Jun 09 01:05:29 PM PDT 24 |
| Finished | Jun 09 01:05:30 PM PDT 24 |
| Peak memory | 215124 kb |
| Host | smart-4afcce39-e7cc-4ef6-abe8-e4f1e29fe899 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936025688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd ev_csr_mem_rw_with_rand_reset.2936025688 |
| Directory | /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3137921874 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 53262124 ps |
| CPU time | 0.81 seconds |
| Started | Jun 09 01:05:29 PM PDT 24 |
| Finished | Jun 09 01:05:30 PM PDT 24 |
| Peak memory | 204692 kb |
| Host | smart-8c68072f-94b3-4212-8617-52827dfce282 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3137921874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.3137921874 |
| Directory | /workspace/12.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2093215148 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 47422183 ps |
| CPU time | 0.68 seconds |
| Started | Jun 09 01:05:27 PM PDT 24 |
| Finished | Jun 09 01:05:27 PM PDT 24 |
| Peak memory | 204572 kb |
| Host | smart-3b86bdc1-6587-497a-8ca4-c99534cc51c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2093215148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.2093215148 |
| Directory | /workspace/12.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3000431483 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 150042403 ps |
| CPU time | 1.58 seconds |
| Started | Jun 09 01:05:32 PM PDT 24 |
| Finished | Jun 09 01:05:34 PM PDT 24 |
| Peak memory | 205212 kb |
| Host | smart-9c372ac6-0139-4110-8cc1-acd9d02c8da8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3000431483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.3000431483 |
| Directory | /workspace/12.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2148518823 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 744279157 ps |
| CPU time | 4.64 seconds |
| Started | Jun 09 01:05:32 PM PDT 24 |
| Finished | Jun 09 01:05:37 PM PDT 24 |
| Peak memory | 205216 kb |
| Host | smart-4a2867bd-ecff-47b2-8a2d-c5a1a91ed70a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2148518823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.2148518823 |
| Directory | /workspace/12.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3708232495 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 144764889 ps |
| CPU time | 1.56 seconds |
| Started | Jun 09 01:05:36 PM PDT 24 |
| Finished | Jun 09 01:05:38 PM PDT 24 |
| Peak memory | 213208 kb |
| Host | smart-eb7c61a0-c0e1-4fb0-ae98-380170f98696 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708232495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd ev_csr_mem_rw_with_rand_reset.3708232495 |
| Directory | /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2778443417 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 69550512 ps |
| CPU time | 0.85 seconds |
| Started | Jun 09 01:05:30 PM PDT 24 |
| Finished | Jun 09 01:05:32 PM PDT 24 |
| Peak memory | 204708 kb |
| Host | smart-1b46dc95-4def-4b50-b8b4-ca0b56f2a7b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2778443417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.2778443417 |
| Directory | /workspace/13.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3670015716 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 56720206 ps |
| CPU time | 0.67 seconds |
| Started | Jun 09 01:05:29 PM PDT 24 |
| Finished | Jun 09 01:05:30 PM PDT 24 |
| Peak memory | 204780 kb |
| Host | smart-bc0167d4-e8e4-4758-97ac-b22f642f1502 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3670015716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.3670015716 |
| Directory | /workspace/13.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1019042192 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 122766966 ps |
| CPU time | 1.18 seconds |
| Started | Jun 09 01:05:41 PM PDT 24 |
| Finished | Jun 09 01:05:42 PM PDT 24 |
| Peak memory | 204968 kb |
| Host | smart-9009ad60-ba9f-43c7-84a9-ce5fa442eaa1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1019042192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.1019042192 |
| Directory | /workspace/13.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.427972962 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 152291766 ps |
| CPU time | 1.69 seconds |
| Started | Jun 09 01:05:30 PM PDT 24 |
| Finished | Jun 09 01:05:32 PM PDT 24 |
| Peak memory | 204928 kb |
| Host | smart-d6a40f5e-9888-4772-b1ed-1c910d8b8a85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=427972962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.427972962 |
| Directory | /workspace/13.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.783607333 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 839891411 ps |
| CPU time | 5.28 seconds |
| Started | Jun 09 01:05:29 PM PDT 24 |
| Finished | Jun 09 01:05:34 PM PDT 24 |
| Peak memory | 204872 kb |
| Host | smart-8f6b9049-62d0-4207-8ce7-0ed5efe9bca0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=783607333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.783607333 |
| Directory | /workspace/13.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2543369447 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 143102498 ps |
| CPU time | 1.3 seconds |
| Started | Jun 09 01:05:34 PM PDT 24 |
| Finished | Jun 09 01:05:35 PM PDT 24 |
| Peak memory | 214696 kb |
| Host | smart-c6e27bb9-0c58-4919-b187-ccd8f7508134 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543369447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd ev_csr_mem_rw_with_rand_reset.2543369447 |
| Directory | /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2029683093 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 89705025 ps |
| CPU time | 1.04 seconds |
| Started | Jun 09 01:05:47 PM PDT 24 |
| Finished | Jun 09 01:05:48 PM PDT 24 |
| Peak memory | 204940 kb |
| Host | smart-d31b1642-b422-4e6c-86c3-f9d61fc7bfa8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2029683093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.2029683093 |
| Directory | /workspace/14.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_intr_test.918750805 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 64458733 ps |
| CPU time | 0.69 seconds |
| Started | Jun 09 01:05:36 PM PDT 24 |
| Finished | Jun 09 01:05:37 PM PDT 24 |
| Peak memory | 204624 kb |
| Host | smart-b019dbca-514e-4284-b001-60d69998304f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=918750805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.918750805 |
| Directory | /workspace/14.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3030303412 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 182884145 ps |
| CPU time | 1.68 seconds |
| Started | Jun 09 01:05:46 PM PDT 24 |
| Finished | Jun 09 01:05:49 PM PDT 24 |
| Peak memory | 204936 kb |
| Host | smart-374182d4-faea-4b96-a081-8fe1ab41fada |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3030303412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.3030303412 |
| Directory | /workspace/14.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2431016802 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 263486866 ps |
| CPU time | 3.01 seconds |
| Started | Jun 09 01:05:36 PM PDT 24 |
| Finished | Jun 09 01:05:39 PM PDT 24 |
| Peak memory | 220588 kb |
| Host | smart-3d9ed32b-d341-4c23-9e77-8a073d7d809c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2431016802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.2431016802 |
| Directory | /workspace/14.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2400388863 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 373694906 ps |
| CPU time | 2.53 seconds |
| Started | Jun 09 01:05:46 PM PDT 24 |
| Finished | Jun 09 01:05:49 PM PDT 24 |
| Peak memory | 204916 kb |
| Host | smart-5dfd3093-6486-470e-bb7e-23087fdeac95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2400388863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.2400388863 |
| Directory | /workspace/14.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2916970410 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 202670281 ps |
| CPU time | 1.98 seconds |
| Started | Jun 09 01:05:46 PM PDT 24 |
| Finished | Jun 09 01:05:48 PM PDT 24 |
| Peak memory | 216528 kb |
| Host | smart-45f797e2-55e0-454f-933e-5524ccff1002 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916970410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd ev_csr_mem_rw_with_rand_reset.2916970410 |
| Directory | /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3457278519 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 66569471 ps |
| CPU time | 0.82 seconds |
| Started | Jun 09 01:05:35 PM PDT 24 |
| Finished | Jun 09 01:05:36 PM PDT 24 |
| Peak memory | 204692 kb |
| Host | smart-a93225ae-141b-4d79-9923-d270a47bf6e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3457278519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.3457278519 |
| Directory | /workspace/15.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_intr_test.959140268 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 69084082 ps |
| CPU time | 0.69 seconds |
| Started | Jun 09 01:05:34 PM PDT 24 |
| Finished | Jun 09 01:05:35 PM PDT 24 |
| Peak memory | 204652 kb |
| Host | smart-240eb8b3-f94f-4675-a51e-89aa531f15ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=959140268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.959140268 |
| Directory | /workspace/15.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.636405848 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 98899396 ps |
| CPU time | 1.47 seconds |
| Started | Jun 09 01:05:40 PM PDT 24 |
| Finished | Jun 09 01:05:42 PM PDT 24 |
| Peak memory | 204960 kb |
| Host | smart-91ddbd10-7895-4ca3-b81a-d8bb054b7e94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=636405848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.636405848 |
| Directory | /workspace/15.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.359583778 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 95579804 ps |
| CPU time | 2.68 seconds |
| Started | Jun 09 01:05:36 PM PDT 24 |
| Finished | Jun 09 01:05:39 PM PDT 24 |
| Peak memory | 220896 kb |
| Host | smart-ef4ab804-87b0-4194-9b9a-516739e60878 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=359583778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.359583778 |
| Directory | /workspace/15.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.4241146326 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 79342371 ps |
| CPU time | 1.73 seconds |
| Started | Jun 09 01:05:34 PM PDT 24 |
| Finished | Jun 09 01:05:36 PM PDT 24 |
| Peak memory | 213148 kb |
| Host | smart-9cb10499-1956-4318-a059-08fbe7af2c70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241146326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd ev_csr_mem_rw_with_rand_reset.4241146326 |
| Directory | /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.614485792 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 79022530 ps |
| CPU time | 0.99 seconds |
| Started | Jun 09 01:05:37 PM PDT 24 |
| Finished | Jun 09 01:05:38 PM PDT 24 |
| Peak memory | 204892 kb |
| Host | smart-acc7ae38-5e01-4180-8d1c-d712dafd2afa |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=614485792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.614485792 |
| Directory | /workspace/16.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1090559875 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 346106817 ps |
| CPU time | 2.14 seconds |
| Started | Jun 09 01:05:39 PM PDT 24 |
| Finished | Jun 09 01:05:41 PM PDT 24 |
| Peak memory | 204908 kb |
| Host | smart-fdbb632c-5cf7-49cd-b2aa-4a91db34b70b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1090559875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.1090559875 |
| Directory | /workspace/16.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3772806249 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 72361362 ps |
| CPU time | 1.84 seconds |
| Started | Jun 09 01:05:35 PM PDT 24 |
| Finished | Jun 09 01:05:37 PM PDT 24 |
| Peak memory | 220456 kb |
| Host | smart-07521d9a-052c-4f12-ba9a-1f8184c0495b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3772806249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.3772806249 |
| Directory | /workspace/16.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.819072733 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1310786583 ps |
| CPU time | 5.6 seconds |
| Started | Jun 09 01:05:39 PM PDT 24 |
| Finished | Jun 09 01:05:45 PM PDT 24 |
| Peak memory | 204972 kb |
| Host | smart-eb7e0574-0014-402c-ac4b-735e189d37c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=819072733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.819072733 |
| Directory | /workspace/16.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3226920870 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 128715065 ps |
| CPU time | 2.13 seconds |
| Started | Jun 09 01:05:42 PM PDT 24 |
| Finished | Jun 09 01:05:44 PM PDT 24 |
| Peak memory | 213136 kb |
| Host | smart-fb6ac0b1-affc-4a87-8389-2ffc955e1104 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226920870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd ev_csr_mem_rw_with_rand_reset.3226920870 |
| Directory | /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2603929434 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 64889504 ps |
| CPU time | 0.96 seconds |
| Started | Jun 09 01:05:40 PM PDT 24 |
| Finished | Jun 09 01:05:41 PM PDT 24 |
| Peak memory | 204968 kb |
| Host | smart-dd322460-33e0-4936-bc04-a2dedb180779 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2603929434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.2603929434 |
| Directory | /workspace/17.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_intr_test.505396474 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 64839249 ps |
| CPU time | 0.75 seconds |
| Started | Jun 09 01:05:37 PM PDT 24 |
| Finished | Jun 09 01:05:39 PM PDT 24 |
| Peak memory | 204632 kb |
| Host | smart-e4727555-1fb8-4999-98bf-c529922ad60a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=505396474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.505396474 |
| Directory | /workspace/17.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.569231176 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 103572049 ps |
| CPU time | 1.28 seconds |
| Started | Jun 09 01:05:46 PM PDT 24 |
| Finished | Jun 09 01:05:47 PM PDT 24 |
| Peak memory | 204992 kb |
| Host | smart-853f1e64-233e-4f44-9e9d-bd8c43cf1783 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=569231176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.569231176 |
| Directory | /workspace/17.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3069504090 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 106873145 ps |
| CPU time | 1.78 seconds |
| Started | Jun 09 01:05:47 PM PDT 24 |
| Finished | Jun 09 01:05:49 PM PDT 24 |
| Peak memory | 205072 kb |
| Host | smart-20fdd5c4-48fb-49d3-83cb-e3450db6db28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3069504090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.3069504090 |
| Directory | /workspace/17.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2053580705 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 328069040 ps |
| CPU time | 2.55 seconds |
| Started | Jun 09 01:05:35 PM PDT 24 |
| Finished | Jun 09 01:05:38 PM PDT 24 |
| Peak memory | 204916 kb |
| Host | smart-5f3d2120-8a1c-4e5e-b095-c1f3320ab642 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2053580705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.2053580705 |
| Directory | /workspace/17.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1953027382 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 190011128 ps |
| CPU time | 2.16 seconds |
| Started | Jun 09 01:05:42 PM PDT 24 |
| Finished | Jun 09 01:05:45 PM PDT 24 |
| Peak memory | 213244 kb |
| Host | smart-28b46274-8c25-4825-9ea3-d89b69936bbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953027382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd ev_csr_mem_rw_with_rand_reset.1953027382 |
| Directory | /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3636589870 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 75971173 ps |
| CPU time | 0.98 seconds |
| Started | Jun 09 01:05:48 PM PDT 24 |
| Finished | Jun 09 01:05:49 PM PDT 24 |
| Peak memory | 204908 kb |
| Host | smart-138f6373-84b9-405a-9b59-40c6ee03c4d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3636589870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.3636589870 |
| Directory | /workspace/18.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_intr_test.29950137 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 37515136 ps |
| CPU time | 0.66 seconds |
| Started | Jun 09 01:05:43 PM PDT 24 |
| Finished | Jun 09 01:05:44 PM PDT 24 |
| Peak memory | 204644 kb |
| Host | smart-2942a59d-d45e-43e6-bf2e-bcfa86fe72ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=29950137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.29950137 |
| Directory | /workspace/18.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2714966780 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 99070516 ps |
| CPU time | 1.14 seconds |
| Started | Jun 09 01:05:47 PM PDT 24 |
| Finished | Jun 09 01:05:48 PM PDT 24 |
| Peak memory | 204896 kb |
| Host | smart-f82c8a73-6c8f-481e-8e84-5aefe511b518 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2714966780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.2714966780 |
| Directory | /workspace/18.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.646063541 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 237456422 ps |
| CPU time | 2.75 seconds |
| Started | Jun 09 01:05:42 PM PDT 24 |
| Finished | Jun 09 01:05:45 PM PDT 24 |
| Peak memory | 220556 kb |
| Host | smart-d7d44b7b-4a69-4898-b5b4-20bd49eed540 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=646063541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.646063541 |
| Directory | /workspace/18.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1454852187 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 528082581 ps |
| CPU time | 2.38 seconds |
| Started | Jun 09 01:05:43 PM PDT 24 |
| Finished | Jun 09 01:05:45 PM PDT 24 |
| Peak memory | 204948 kb |
| Host | smart-d17cd2af-2fe1-4e67-a151-7923d31d9a7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1454852187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.1454852187 |
| Directory | /workspace/18.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2123626859 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 250829187 ps |
| CPU time | 2.07 seconds |
| Started | Jun 09 01:05:43 PM PDT 24 |
| Finished | Jun 09 01:05:45 PM PDT 24 |
| Peak memory | 213216 kb |
| Host | smart-62ab8814-fb35-4610-94c7-54c68ea72016 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123626859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd ev_csr_mem_rw_with_rand_reset.2123626859 |
| Directory | /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1320335284 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 44440304 ps |
| CPU time | 0.8 seconds |
| Started | Jun 09 01:05:44 PM PDT 24 |
| Finished | Jun 09 01:05:45 PM PDT 24 |
| Peak memory | 204752 kb |
| Host | smart-02f96a1a-849e-40ae-bf12-4073be5c0e9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1320335284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.1320335284 |
| Directory | /workspace/19.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_intr_test.727528732 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 101711375 ps |
| CPU time | 0.72 seconds |
| Started | Jun 09 01:05:47 PM PDT 24 |
| Finished | Jun 09 01:05:49 PM PDT 24 |
| Peak memory | 204664 kb |
| Host | smart-62131618-23a1-4ee0-9179-963d6ff598ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=727528732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.727528732 |
| Directory | /workspace/19.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.4137942115 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 213776357 ps |
| CPU time | 1.73 seconds |
| Started | Jun 09 01:05:43 PM PDT 24 |
| Finished | Jun 09 01:05:45 PM PDT 24 |
| Peak memory | 204876 kb |
| Host | smart-3dc61286-b0dc-4585-90d6-bbdd32a97d95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4137942115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.4137942115 |
| Directory | /workspace/19.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3752702184 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 290085688 ps |
| CPU time | 2.99 seconds |
| Started | Jun 09 01:05:41 PM PDT 24 |
| Finished | Jun 09 01:05:44 PM PDT 24 |
| Peak memory | 205020 kb |
| Host | smart-9124f33b-41b7-458e-8c03-62f4976ee63e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3752702184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.3752702184 |
| Directory | /workspace/19.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2713268448 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1583366239 ps |
| CPU time | 5.52 seconds |
| Started | Jun 09 01:05:45 PM PDT 24 |
| Finished | Jun 09 01:05:51 PM PDT 24 |
| Peak memory | 204972 kb |
| Host | smart-ec8020d2-7bb0-45d0-8bcd-9c05debbdbb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2713268448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.2713268448 |
| Directory | /workspace/19.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2300688180 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 296393092 ps |
| CPU time | 3.68 seconds |
| Started | Jun 09 01:04:57 PM PDT 24 |
| Finished | Jun 09 01:05:01 PM PDT 24 |
| Peak memory | 204876 kb |
| Host | smart-3b179a78-ac80-4f58-9eba-5a9eb6dc5a27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2300688180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.2300688180 |
| Directory | /workspace/2.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.2557795414 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 474402383 ps |
| CPU time | 4.94 seconds |
| Started | Jun 09 01:04:59 PM PDT 24 |
| Finished | Jun 09 01:05:04 PM PDT 24 |
| Peak memory | 205004 kb |
| Host | smart-6130ee20-df67-4d2e-8e49-0512fb86bcc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2557795414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.2557795414 |
| Directory | /workspace/2.usbdev_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2637850379 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 126271130 ps |
| CPU time | 0.97 seconds |
| Started | Jun 09 01:04:56 PM PDT 24 |
| Finished | Jun 09 01:04:57 PM PDT 24 |
| Peak memory | 204748 kb |
| Host | smart-6d9ebf0f-f8d4-4ae1-93ae-6a1b67e68d01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2637850379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.2637850379 |
| Directory | /workspace/2.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2279525872 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 223076833 ps |
| CPU time | 1.98 seconds |
| Started | Jun 09 01:04:56 PM PDT 24 |
| Finished | Jun 09 01:04:58 PM PDT 24 |
| Peak memory | 213148 kb |
| Host | smart-56ba4fda-b4bc-4724-8ede-bccba8490159 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279525872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde v_csr_mem_rw_with_rand_reset.2279525872 |
| Directory | /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2778146343 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 57767889 ps |
| CPU time | 0.84 seconds |
| Started | Jun 09 01:04:56 PM PDT 24 |
| Finished | Jun 09 01:04:57 PM PDT 24 |
| Peak memory | 204688 kb |
| Host | smart-b8eba9c6-4fd1-4590-8c42-4ea7b26b0bc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2778146343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.2778146343 |
| Directory | /workspace/2.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_intr_test.497346 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 49050174 ps |
| CPU time | 0.68 seconds |
| Started | Jun 09 01:04:56 PM PDT 24 |
| Finished | Jun 09 01:04:57 PM PDT 24 |
| Peak memory | 204648 kb |
| Host | smart-48e6b04b-1e69-4643-ba50-73d307ea88d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=497346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.497346 |
| Directory | /workspace/2.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1713750655 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 116515712 ps |
| CPU time | 2.05 seconds |
| Started | Jun 09 01:04:55 PM PDT 24 |
| Finished | Jun 09 01:04:57 PM PDT 24 |
| Peak memory | 213164 kb |
| Host | smart-34762a74-8ce3-4a16-9a21-988fc49a8ec0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1713750655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.1713750655 |
| Directory | /workspace/2.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3148766145 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 528792934 ps |
| CPU time | 4.24 seconds |
| Started | Jun 09 01:04:55 PM PDT 24 |
| Finished | Jun 09 01:04:59 PM PDT 24 |
| Peak memory | 204948 kb |
| Host | smart-c42cbf15-b755-4dd1-909f-49a7f9d8f768 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3148766145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.3148766145 |
| Directory | /workspace/2.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3316630158 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 157353202 ps |
| CPU time | 1.77 seconds |
| Started | Jun 09 01:04:55 PM PDT 24 |
| Finished | Jun 09 01:04:57 PM PDT 24 |
| Peak memory | 204908 kb |
| Host | smart-148b7ef4-0ac3-4d1b-ace3-d68073eb04d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3316630158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.3316630158 |
| Directory | /workspace/2.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2547960836 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 298996721 ps |
| CPU time | 3.67 seconds |
| Started | Jun 09 01:05:39 PM PDT 24 |
| Finished | Jun 09 01:05:43 PM PDT 24 |
| Peak memory | 220500 kb |
| Host | smart-8c95a4a4-32fd-44bd-ac97-a9ed22c6e096 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2547960836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.2547960836 |
| Directory | /workspace/2.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1708183007 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1575542547 ps |
| CPU time | 5.67 seconds |
| Started | Jun 09 01:04:52 PM PDT 24 |
| Finished | Jun 09 01:04:58 PM PDT 24 |
| Peak memory | 204904 kb |
| Host | smart-2c8a27b1-3ca1-4f30-9f27-51316e7a9a0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1708183007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.1708183007 |
| Directory | /workspace/2.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2528196431 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 59987538 ps |
| CPU time | 0.72 seconds |
| Started | Jun 09 01:05:42 PM PDT 24 |
| Finished | Jun 09 01:05:43 PM PDT 24 |
| Peak memory | 204588 kb |
| Host | smart-56a38bd4-9f0d-4bab-9dd1-4b8213f1a82d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2528196431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.2528196431 |
| Directory | /workspace/20.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.usbdev_intr_test.3591622168 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 31905341 ps |
| CPU time | 0.73 seconds |
| Started | Jun 09 01:05:48 PM PDT 24 |
| Finished | Jun 09 01:05:49 PM PDT 24 |
| Peak memory | 204620 kb |
| Host | smart-94f55c80-4f18-4572-ae41-96767a3f9d85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3591622168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.3591622168 |
| Directory | /workspace/21.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.usbdev_intr_test.509920671 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 108381018 ps |
| CPU time | 0.74 seconds |
| Started | Jun 09 01:05:46 PM PDT 24 |
| Finished | Jun 09 01:05:47 PM PDT 24 |
| Peak memory | 204644 kb |
| Host | smart-bc2a8f09-1174-406d-af2e-c3b9c440e3c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=509920671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.509920671 |
| Directory | /workspace/22.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.usbdev_intr_test.2989692466 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 58615530 ps |
| CPU time | 0.69 seconds |
| Started | Jun 09 01:05:47 PM PDT 24 |
| Finished | Jun 09 01:05:48 PM PDT 24 |
| Peak memory | 204640 kb |
| Host | smart-b0bdc238-395a-4e67-8c4b-c927505abfa7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2989692466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.2989692466 |
| Directory | /workspace/23.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.usbdev_intr_test.1504023747 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 35942627 ps |
| CPU time | 0.65 seconds |
| Started | Jun 09 01:05:47 PM PDT 24 |
| Finished | Jun 09 01:05:48 PM PDT 24 |
| Peak memory | 204628 kb |
| Host | smart-be0e9ae7-7a99-448f-a516-8fe7026a6b20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1504023747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.1504023747 |
| Directory | /workspace/24.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.usbdev_intr_test.734861502 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 62183438 ps |
| CPU time | 0.73 seconds |
| Started | Jun 09 01:05:47 PM PDT 24 |
| Finished | Jun 09 01:05:48 PM PDT 24 |
| Peak memory | 204612 kb |
| Host | smart-a1f91adc-d0c4-4638-bd36-4d31a7191c71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=734861502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.734861502 |
| Directory | /workspace/25.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.usbdev_intr_test.433630571 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 76106450 ps |
| CPU time | 0.71 seconds |
| Started | Jun 09 01:05:48 PM PDT 24 |
| Finished | Jun 09 01:05:49 PM PDT 24 |
| Peak memory | 204652 kb |
| Host | smart-b286d703-387b-45c1-a8c4-a37dece11665 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=433630571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.433630571 |
| Directory | /workspace/26.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2554441665 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 54767161 ps |
| CPU time | 0.66 seconds |
| Started | Jun 09 01:05:46 PM PDT 24 |
| Finished | Jun 09 01:05:48 PM PDT 24 |
| Peak memory | 204624 kb |
| Host | smart-c7df3531-ce34-4842-9c9b-bdf99ae284d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2554441665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.2554441665 |
| Directory | /workspace/27.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.usbdev_intr_test.1003668133 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 78698458 ps |
| CPU time | 0.7 seconds |
| Started | Jun 09 01:05:47 PM PDT 24 |
| Finished | Jun 09 01:05:48 PM PDT 24 |
| Peak memory | 204572 kb |
| Host | smart-fbc28d6c-bc62-4cfa-93e4-9a98479a9f56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1003668133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.1003668133 |
| Directory | /workspace/28.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.usbdev_intr_test.962163112 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 37227551 ps |
| CPU time | 0.64 seconds |
| Started | Jun 09 01:05:53 PM PDT 24 |
| Finished | Jun 09 01:05:54 PM PDT 24 |
| Peak memory | 204664 kb |
| Host | smart-f198933a-a329-4eb7-aa46-c12aa77da37c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=962163112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.962163112 |
| Directory | /workspace/29.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.836947883 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 290619695 ps |
| CPU time | 3.58 seconds |
| Started | Jun 09 01:05:03 PM PDT 24 |
| Finished | Jun 09 01:05:07 PM PDT 24 |
| Peak memory | 204940 kb |
| Host | smart-fc4aa872-67fb-43b5-8f66-584d9501ec9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=836947883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.836947883 |
| Directory | /workspace/3.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3597397433 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 953469016 ps |
| CPU time | 7.96 seconds |
| Started | Jun 09 01:05:02 PM PDT 24 |
| Finished | Jun 09 01:05:11 PM PDT 24 |
| Peak memory | 204904 kb |
| Host | smart-3792b8e5-4620-47da-b927-8b3e0e5350be |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3597397433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.3597397433 |
| Directory | /workspace/3.usbdev_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2529389931 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 176900728 ps |
| CPU time | 0.99 seconds |
| Started | Jun 09 01:05:03 PM PDT 24 |
| Finished | Jun 09 01:05:04 PM PDT 24 |
| Peak memory | 204748 kb |
| Host | smart-8b1f5c8b-ce01-4386-a8fe-c08227ff6fa6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2529389931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.2529389931 |
| Directory | /workspace/3.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.175791105 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 139157507 ps |
| CPU time | 2.52 seconds |
| Started | Jun 09 01:05:04 PM PDT 24 |
| Finished | Jun 09 01:05:06 PM PDT 24 |
| Peak memory | 213156 kb |
| Host | smart-b4519822-203d-4649-8e6f-75ab3777390f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175791105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev _csr_mem_rw_with_rand_reset.175791105 |
| Directory | /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.216720475 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 85363944 ps |
| CPU time | 1.07 seconds |
| Started | Jun 09 01:05:02 PM PDT 24 |
| Finished | Jun 09 01:05:04 PM PDT 24 |
| Peak memory | 204856 kb |
| Host | smart-32201eca-b494-4170-a902-720995db6df7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=216720475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.216720475 |
| Directory | /workspace/3.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2789369010 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 140771216 ps |
| CPU time | 1.57 seconds |
| Started | Jun 09 01:05:03 PM PDT 24 |
| Finished | Jun 09 01:05:05 PM PDT 24 |
| Peak memory | 204972 kb |
| Host | smart-8cb7d567-380e-40a3-9a65-4078835fa2d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2789369010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.2789369010 |
| Directory | /workspace/3.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3094820041 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 323544751 ps |
| CPU time | 2.42 seconds |
| Started | Jun 09 01:04:55 PM PDT 24 |
| Finished | Jun 09 01:04:58 PM PDT 24 |
| Peak memory | 204928 kb |
| Host | smart-503b8780-040b-457e-adab-bf1cebc64ea7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3094820041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.3094820041 |
| Directory | /workspace/3.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3375853666 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 196527331 ps |
| CPU time | 1.32 seconds |
| Started | Jun 09 01:05:00 PM PDT 24 |
| Finished | Jun 09 01:05:01 PM PDT 24 |
| Peak memory | 204876 kb |
| Host | smart-a1e3a1f1-283d-4d40-b475-f1d8b8d0bea1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3375853666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.3375853666 |
| Directory | /workspace/3.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.692711131 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 112162990 ps |
| CPU time | 1.48 seconds |
| Started | Jun 09 01:04:55 PM PDT 24 |
| Finished | Jun 09 01:04:57 PM PDT 24 |
| Peak memory | 204992 kb |
| Host | smart-d452d9f3-a7c6-45ad-908e-b08356a0158d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=692711131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.692711131 |
| Directory | /workspace/3.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1757664526 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 681439300 ps |
| CPU time | 4.89 seconds |
| Started | Jun 09 01:04:59 PM PDT 24 |
| Finished | Jun 09 01:05:04 PM PDT 24 |
| Peak memory | 205016 kb |
| Host | smart-c98f0626-a09e-46ab-afbc-469f49529ef5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1757664526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.1757664526 |
| Directory | /workspace/3.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/30.usbdev_intr_test.1863667661 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 40081490 ps |
| CPU time | 0.64 seconds |
| Started | Jun 09 01:05:47 PM PDT 24 |
| Finished | Jun 09 01:05:48 PM PDT 24 |
| Peak memory | 204644 kb |
| Host | smart-bb72bc81-7d49-4c3b-9ef7-a85d2e948bb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1863667661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.1863667661 |
| Directory | /workspace/30.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3097111631 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 57960689 ps |
| CPU time | 0.72 seconds |
| Started | Jun 09 01:05:52 PM PDT 24 |
| Finished | Jun 09 01:05:53 PM PDT 24 |
| Peak memory | 204604 kb |
| Host | smart-0b19b76d-1406-46d9-a134-8248d04c7809 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3097111631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.3097111631 |
| Directory | /workspace/31.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.usbdev_intr_test.4028624746 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 50339146 ps |
| CPU time | 0.69 seconds |
| Started | Jun 09 01:05:54 PM PDT 24 |
| Finished | Jun 09 01:05:55 PM PDT 24 |
| Peak memory | 204644 kb |
| Host | smart-f850edc0-4504-4639-88c1-2c36f2d6c2ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4028624746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.4028624746 |
| Directory | /workspace/32.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.usbdev_intr_test.17719142 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 34920034 ps |
| CPU time | 0.66 seconds |
| Started | Jun 09 01:05:53 PM PDT 24 |
| Finished | Jun 09 01:05:54 PM PDT 24 |
| Peak memory | 204632 kb |
| Host | smart-11fa37a6-7b64-43b2-984f-12f4aca4283b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=17719142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.17719142 |
| Directory | /workspace/33.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.usbdev_intr_test.4187757448 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 49414220 ps |
| CPU time | 0.73 seconds |
| Started | Jun 09 01:05:54 PM PDT 24 |
| Finished | Jun 09 01:05:55 PM PDT 24 |
| Peak memory | 204652 kb |
| Host | smart-b64abf70-748a-4829-90f7-5d52d50d16c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4187757448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.4187757448 |
| Directory | /workspace/34.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3424034595 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 90772212 ps |
| CPU time | 0.7 seconds |
| Started | Jun 09 01:05:53 PM PDT 24 |
| Finished | Jun 09 01:05:54 PM PDT 24 |
| Peak memory | 204616 kb |
| Host | smart-1929c54c-f16a-469e-ba2d-605047306a18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3424034595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.3424034595 |
| Directory | /workspace/35.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.usbdev_intr_test.4078378863 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 41815029 ps |
| CPU time | 0.68 seconds |
| Started | Jun 09 01:05:52 PM PDT 24 |
| Finished | Jun 09 01:05:53 PM PDT 24 |
| Peak memory | 204624 kb |
| Host | smart-fc7aee04-3535-43ec-b2ed-af170146177c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4078378863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.4078378863 |
| Directory | /workspace/36.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1218744969 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 33348611 ps |
| CPU time | 0.64 seconds |
| Started | Jun 09 01:05:53 PM PDT 24 |
| Finished | Jun 09 01:05:54 PM PDT 24 |
| Peak memory | 204628 kb |
| Host | smart-a1526ac4-bd59-42e5-a405-34bed6a2eaeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1218744969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.1218744969 |
| Directory | /workspace/37.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.usbdev_intr_test.1470771430 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 35876125 ps |
| CPU time | 0.81 seconds |
| Started | Jun 09 01:05:54 PM PDT 24 |
| Finished | Jun 09 01:05:55 PM PDT 24 |
| Peak memory | 204652 kb |
| Host | smart-c5072917-1a3c-433e-a7d6-cac4000c4981 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1470771430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.1470771430 |
| Directory | /workspace/38.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3698291712 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 355841890 ps |
| CPU time | 3.66 seconds |
| Started | Jun 09 01:05:07 PM PDT 24 |
| Finished | Jun 09 01:05:11 PM PDT 24 |
| Peak memory | 204932 kb |
| Host | smart-69359441-f9f9-4b2e-9221-851ef99e0661 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3698291712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.3698291712 |
| Directory | /workspace/4.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2540381173 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1106476131 ps |
| CPU time | 8.38 seconds |
| Started | Jun 09 01:05:08 PM PDT 24 |
| Finished | Jun 09 01:05:17 PM PDT 24 |
| Peak memory | 204992 kb |
| Host | smart-a865ece3-a367-407a-ad1f-6652618dc6da |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2540381173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.2540381173 |
| Directory | /workspace/4.usbdev_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.727575883 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 194038947 ps |
| CPU time | 0.95 seconds |
| Started | Jun 09 01:05:07 PM PDT 24 |
| Finished | Jun 09 01:05:08 PM PDT 24 |
| Peak memory | 204708 kb |
| Host | smart-bcfa4691-b4d0-4bfb-80f9-69c3de31209d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=727575883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.727575883 |
| Directory | /workspace/4.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1590297744 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 115066239 ps |
| CPU time | 2.93 seconds |
| Started | Jun 09 01:05:14 PM PDT 24 |
| Finished | Jun 09 01:05:17 PM PDT 24 |
| Peak memory | 213152 kb |
| Host | smart-a7e14008-4b93-494f-ba72-ae9b154f88f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590297744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde v_csr_mem_rw_with_rand_reset.1590297744 |
| Directory | /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3852792395 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 63269706 ps |
| CPU time | 0.99 seconds |
| Started | Jun 09 01:05:10 PM PDT 24 |
| Finished | Jun 09 01:05:12 PM PDT 24 |
| Peak memory | 204936 kb |
| Host | smart-539cb7a3-edcb-4063-a30b-8443abe352b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3852792395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.3852792395 |
| Directory | /workspace/4.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1688782028 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 33347659 ps |
| CPU time | 0.66 seconds |
| Started | Jun 09 01:05:07 PM PDT 24 |
| Finished | Jun 09 01:05:07 PM PDT 24 |
| Peak memory | 204572 kb |
| Host | smart-5ce1f1d5-51f3-4906-a6bb-2f1c09b3f7f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1688782028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.1688782028 |
| Directory | /workspace/4.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1050751239 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 118615499 ps |
| CPU time | 1.56 seconds |
| Started | Jun 09 01:05:08 PM PDT 24 |
| Finished | Jun 09 01:05:10 PM PDT 24 |
| Peak memory | 213124 kb |
| Host | smart-2761ba0a-9bb0-4de9-9992-8e67f6f83b75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1050751239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.1050751239 |
| Directory | /workspace/4.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.4070177680 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 708582707 ps |
| CPU time | 4.98 seconds |
| Started | Jun 09 01:05:09 PM PDT 24 |
| Finished | Jun 09 01:05:14 PM PDT 24 |
| Peak memory | 204908 kb |
| Host | smart-78e4b068-e4da-46b4-9961-58a2add86aaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=4070177680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.4070177680 |
| Directory | /workspace/4.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.68157338 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 196974873 ps |
| CPU time | 1.66 seconds |
| Started | Jun 09 01:05:15 PM PDT 24 |
| Finished | Jun 09 01:05:17 PM PDT 24 |
| Peak memory | 204948 kb |
| Host | smart-d7166e10-99e4-4a36-813f-cb58717618c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=68157338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.68157338 |
| Directory | /workspace/4.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3461067432 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 955039121 ps |
| CPU time | 4.99 seconds |
| Started | Jun 09 01:05:07 PM PDT 24 |
| Finished | Jun 09 01:05:12 PM PDT 24 |
| Peak memory | 204920 kb |
| Host | smart-56555713-6f98-43a7-9071-895bcbcfb44a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3461067432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.3461067432 |
| Directory | /workspace/4.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3018789 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 115534015 ps |
| CPU time | 0.69 seconds |
| Started | Jun 09 01:05:51 PM PDT 24 |
| Finished | Jun 09 01:05:51 PM PDT 24 |
| Peak memory | 204624 kb |
| Host | smart-73f12ef3-7670-4fc6-abf4-918718289402 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3018789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.3018789 |
| Directory | /workspace/40.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.usbdev_intr_test.683663128 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 49789489 ps |
| CPU time | 0.73 seconds |
| Started | Jun 09 01:05:53 PM PDT 24 |
| Finished | Jun 09 01:05:55 PM PDT 24 |
| Peak memory | 204636 kb |
| Host | smart-48493763-bc43-402d-abbe-b39aed392c9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=683663128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.683663128 |
| Directory | /workspace/41.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3840496613 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 39031149 ps |
| CPU time | 0.68 seconds |
| Started | Jun 09 01:05:59 PM PDT 24 |
| Finished | Jun 09 01:06:00 PM PDT 24 |
| Peak memory | 204652 kb |
| Host | smart-f0a563cd-afb5-4983-b3c9-415acdb2a225 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3840496613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.3840496613 |
| Directory | /workspace/43.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2965442177 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 35238512 ps |
| CPU time | 0.7 seconds |
| Started | Jun 09 01:05:54 PM PDT 24 |
| Finished | Jun 09 01:05:55 PM PDT 24 |
| Peak memory | 204624 kb |
| Host | smart-7f55a3fa-0a73-4ab1-b44f-e96b50e19d30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2965442177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.2965442177 |
| Directory | /workspace/44.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.usbdev_intr_test.3154788952 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 88901825 ps |
| CPU time | 0.68 seconds |
| Started | Jun 09 01:05:52 PM PDT 24 |
| Finished | Jun 09 01:05:53 PM PDT 24 |
| Peak memory | 204624 kb |
| Host | smart-ee37bcbd-401d-47c3-961b-d605f45f5291 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3154788952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.3154788952 |
| Directory | /workspace/45.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.usbdev_intr_test.1081640076 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 53924247 ps |
| CPU time | 0.69 seconds |
| Started | Jun 09 01:05:56 PM PDT 24 |
| Finished | Jun 09 01:05:57 PM PDT 24 |
| Peak memory | 204652 kb |
| Host | smart-a385320e-ba0f-4d7d-be53-0f865851dc01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1081640076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.1081640076 |
| Directory | /workspace/46.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1079043894 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 38123654 ps |
| CPU time | 0.63 seconds |
| Started | Jun 09 01:05:52 PM PDT 24 |
| Finished | Jun 09 01:05:53 PM PDT 24 |
| Peak memory | 204588 kb |
| Host | smart-7ef50728-ec11-4268-b304-bacf88618f74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1079043894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.1079043894 |
| Directory | /workspace/47.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.usbdev_intr_test.4019082073 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 43822922 ps |
| CPU time | 0.68 seconds |
| Started | Jun 09 01:05:57 PM PDT 24 |
| Finished | Jun 09 01:05:58 PM PDT 24 |
| Peak memory | 204632 kb |
| Host | smart-588e6570-c58d-4c38-b6f4-d345afedbe48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4019082073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.4019082073 |
| Directory | /workspace/48.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.usbdev_intr_test.596238369 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 71507273 ps |
| CPU time | 0.67 seconds |
| Started | Jun 09 01:06:01 PM PDT 24 |
| Finished | Jun 09 01:06:02 PM PDT 24 |
| Peak memory | 204588 kb |
| Host | smart-235846da-87a2-414f-bd2e-b534443c3763 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=596238369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.596238369 |
| Directory | /workspace/49.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.3218855570 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 107574761 ps |
| CPU time | 1.59 seconds |
| Started | Jun 09 01:05:13 PM PDT 24 |
| Finished | Jun 09 01:05:15 PM PDT 24 |
| Peak memory | 213156 kb |
| Host | smart-f6edfd70-27f3-4023-8531-e3e27f98d7a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218855570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde v_csr_mem_rw_with_rand_reset.3218855570 |
| Directory | /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1262738026 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 40869718 ps |
| CPU time | 0.65 seconds |
| Started | Jun 09 01:05:14 PM PDT 24 |
| Finished | Jun 09 01:05:15 PM PDT 24 |
| Peak memory | 204648 kb |
| Host | smart-4b22139c-8134-4bcd-9965-c32e322dd7ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1262738026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.1262738026 |
| Directory | /workspace/5.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.4074570970 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 338664427 ps |
| CPU time | 1.65 seconds |
| Started | Jun 09 01:05:13 PM PDT 24 |
| Finished | Jun 09 01:05:15 PM PDT 24 |
| Peak memory | 204972 kb |
| Host | smart-27b90de2-7d0a-4d7e-ac2a-b5e54203eeb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4074570970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.4074570970 |
| Directory | /workspace/5.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2981872096 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 183374379 ps |
| CPU time | 2.05 seconds |
| Started | Jun 09 01:05:12 PM PDT 24 |
| Finished | Jun 09 01:05:14 PM PDT 24 |
| Peak memory | 204996 kb |
| Host | smart-b75106e2-fc0a-4209-bf82-794e3fc3dbdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2981872096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.2981872096 |
| Directory | /workspace/5.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1264538449 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 832287342 ps |
| CPU time | 4.53 seconds |
| Started | Jun 09 01:05:12 PM PDT 24 |
| Finished | Jun 09 01:05:17 PM PDT 24 |
| Peak memory | 204868 kb |
| Host | smart-47bd7e74-bf13-404c-8d29-9caa185361ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1264538449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.1264538449 |
| Directory | /workspace/5.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1931952541 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 129726467 ps |
| CPU time | 2.44 seconds |
| Started | Jun 09 01:05:34 PM PDT 24 |
| Finished | Jun 09 01:05:37 PM PDT 24 |
| Peak memory | 213388 kb |
| Host | smart-ff38276f-74d9-49a5-aced-270d21394392 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931952541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde v_csr_mem_rw_with_rand_reset.1931952541 |
| Directory | /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2841300960 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 42156909 ps |
| CPU time | 0.78 seconds |
| Started | Jun 09 01:05:16 PM PDT 24 |
| Finished | Jun 09 01:05:17 PM PDT 24 |
| Peak memory | 204712 kb |
| Host | smart-fcea7d22-f408-402c-97bc-247ed3ac0d8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2841300960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.2841300960 |
| Directory | /workspace/6.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_intr_test.130517183 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 95706979 ps |
| CPU time | 0.7 seconds |
| Started | Jun 09 01:05:22 PM PDT 24 |
| Finished | Jun 09 01:05:23 PM PDT 24 |
| Peak memory | 204860 kb |
| Host | smart-90076f1a-d007-4ce6-b7c7-bfdf35b03e92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=130517183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.130517183 |
| Directory | /workspace/6.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.2891162290 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 76352241 ps |
| CPU time | 1.06 seconds |
| Started | Jun 09 01:05:17 PM PDT 24 |
| Finished | Jun 09 01:05:18 PM PDT 24 |
| Peak memory | 204928 kb |
| Host | smart-d38f4086-f2f3-460d-b67f-2dc23e6a8ed0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2891162290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.2891162290 |
| Directory | /workspace/6.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2865479691 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 105900722 ps |
| CPU time | 2.87 seconds |
| Started | Jun 09 01:05:16 PM PDT 24 |
| Finished | Jun 09 01:05:19 PM PDT 24 |
| Peak memory | 204992 kb |
| Host | smart-5c1e3f72-3917-440c-8d2f-8f34b5a95a6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2865479691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.2865479691 |
| Directory | /workspace/6.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.913985872 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 368416897 ps |
| CPU time | 2.82 seconds |
| Started | Jun 09 01:05:17 PM PDT 24 |
| Finished | Jun 09 01:05:20 PM PDT 24 |
| Peak memory | 204988 kb |
| Host | smart-0412a59c-9d3d-4921-b3b3-f5db6b1cc590 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=913985872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.913985872 |
| Directory | /workspace/6.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1201985106 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 74113587 ps |
| CPU time | 1.5 seconds |
| Started | Jun 09 01:05:22 PM PDT 24 |
| Finished | Jun 09 01:05:23 PM PDT 24 |
| Peak memory | 213396 kb |
| Host | smart-e3fc34c1-2e00-4acd-9224-c543fdf76816 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201985106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde v_csr_mem_rw_with_rand_reset.1201985106 |
| Directory | /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1226963463 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 45062928 ps |
| CPU time | 0.99 seconds |
| Started | Jun 09 01:05:34 PM PDT 24 |
| Finished | Jun 09 01:05:35 PM PDT 24 |
| Peak memory | 205152 kb |
| Host | smart-d6edb371-9d30-42c4-955e-8c38eb9366e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1226963463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.1226963463 |
| Directory | /workspace/7.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2630481169 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 48408765 ps |
| CPU time | 0.66 seconds |
| Started | Jun 09 01:05:19 PM PDT 24 |
| Finished | Jun 09 01:05:20 PM PDT 24 |
| Peak memory | 204608 kb |
| Host | smart-ba8f2ed0-ce20-46e2-b9dd-fbf7e0461142 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2630481169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.2630481169 |
| Directory | /workspace/7.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.922541263 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 261610541 ps |
| CPU time | 1.92 seconds |
| Started | Jun 09 01:05:21 PM PDT 24 |
| Finished | Jun 09 01:05:23 PM PDT 24 |
| Peak memory | 204956 kb |
| Host | smart-ec64cc2d-2155-4e89-8acc-43a89611f3ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=922541263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.922541263 |
| Directory | /workspace/7.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1332272137 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 157279973 ps |
| CPU time | 2.05 seconds |
| Started | Jun 09 01:05:21 PM PDT 24 |
| Finished | Jun 09 01:05:23 PM PDT 24 |
| Peak memory | 213152 kb |
| Host | smart-6c0334d0-6c16-45b1-a890-1f73bbe7b2f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1332272137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.1332272137 |
| Directory | /workspace/7.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1455544101 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 397958686 ps |
| CPU time | 2.62 seconds |
| Started | Jun 09 01:05:17 PM PDT 24 |
| Finished | Jun 09 01:05:20 PM PDT 24 |
| Peak memory | 205212 kb |
| Host | smart-739b2ed0-62f2-43cb-838a-93d3fc6facbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1455544101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.1455544101 |
| Directory | /workspace/7.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.21357472 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 88593497 ps |
| CPU time | 1.27 seconds |
| Started | Jun 09 01:05:24 PM PDT 24 |
| Finished | Jun 09 01:05:25 PM PDT 24 |
| Peak memory | 214928 kb |
| Host | smart-dbdd77e1-a8ae-4d66-99a5-2b58b427c18e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21357472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_ csr_mem_rw_with_rand_reset.21357472 |
| Directory | /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1398127547 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 76745930 ps |
| CPU time | 0.88 seconds |
| Started | Jun 09 01:05:18 PM PDT 24 |
| Finished | Jun 09 01:05:20 PM PDT 24 |
| Peak memory | 204672 kb |
| Host | smart-05052b1e-4e96-4314-ba48-5c2b569d78f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1398127547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.1398127547 |
| Directory | /workspace/8.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_intr_test.4044168728 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 42459165 ps |
| CPU time | 0.66 seconds |
| Started | Jun 09 01:05:22 PM PDT 24 |
| Finished | Jun 09 01:05:23 PM PDT 24 |
| Peak memory | 204860 kb |
| Host | smart-34222889-abfc-4849-89dd-8f4d40ef227a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4044168728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.4044168728 |
| Directory | /workspace/8.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.338091638 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 135901729 ps |
| CPU time | 1.54 seconds |
| Started | Jun 09 01:05:21 PM PDT 24 |
| Finished | Jun 09 01:05:23 PM PDT 24 |
| Peak memory | 204892 kb |
| Host | smart-c6fa33ab-e573-45a7-bccc-72fa4c86086c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=338091638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.338091638 |
| Directory | /workspace/8.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2482410227 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 100645432 ps |
| CPU time | 2.15 seconds |
| Started | Jun 09 01:05:16 PM PDT 24 |
| Finished | Jun 09 01:05:19 PM PDT 24 |
| Peak memory | 220596 kb |
| Host | smart-2be956b1-7206-4f45-b314-9b8acb0e9a94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2482410227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.2482410227 |
| Directory | /workspace/8.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.533741490 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 131980801 ps |
| CPU time | 1.84 seconds |
| Started | Jun 09 01:05:24 PM PDT 24 |
| Finished | Jun 09 01:05:26 PM PDT 24 |
| Peak memory | 213144 kb |
| Host | smart-8fb3ee76-76ac-4b6c-8336-d29a8d38885a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533741490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev _csr_mem_rw_with_rand_reset.533741490 |
| Directory | /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.4014130687 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 119853406 ps |
| CPU time | 0.91 seconds |
| Started | Jun 09 01:05:24 PM PDT 24 |
| Finished | Jun 09 01:05:25 PM PDT 24 |
| Peak memory | 204724 kb |
| Host | smart-eefa953a-d767-446d-ba3f-08a9c7c2675c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=4014130687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.4014130687 |
| Directory | /workspace/9.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1604781725 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 48420702 ps |
| CPU time | 0.63 seconds |
| Started | Jun 09 01:05:24 PM PDT 24 |
| Finished | Jun 09 01:05:25 PM PDT 24 |
| Peak memory | 204624 kb |
| Host | smart-02def55c-56c4-4307-aaad-1bc415400629 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1604781725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.1604781725 |
| Directory | /workspace/9.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1984292681 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 118806846 ps |
| CPU time | 1.14 seconds |
| Started | Jun 09 01:05:22 PM PDT 24 |
| Finished | Jun 09 01:05:24 PM PDT 24 |
| Peak memory | 204900 kb |
| Host | smart-2d738bd2-533d-4367-b30a-0c6ee9b1bce2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1984292681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.1984292681 |
| Directory | /workspace/9.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.543358270 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 77115346 ps |
| CPU time | 1.55 seconds |
| Started | Jun 09 01:05:26 PM PDT 24 |
| Finished | Jun 09 01:05:27 PM PDT 24 |
| Peak memory | 213104 kb |
| Host | smart-990ed633-2ed2-41be-8d51-5a662ea2f29f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=543358270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.543358270 |
| Directory | /workspace/9.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1750236477 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1356407050 ps |
| CPU time | 6.26 seconds |
| Started | Jun 09 01:05:24 PM PDT 24 |
| Finished | Jun 09 01:05:31 PM PDT 24 |
| Peak memory | 204908 kb |
| Host | smart-240c4479-5c67-4745-9981-5dc57e8ed13f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1750236477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.1750236477 |
| Directory | /workspace/9.usbdev_tl_intg_err/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |