| ASSERT | PROPERTIES | SEQUENCES | |
| Total | 348 | 0 | 10 |
| Category 0 | 348 | 0 | 10 |
| ASSERT | PROPERTIES | SEQUENCES | |
| Total | 348 | 0 | 10 |
| Severity 0 | 348 | 0 | 10 |
| NUMBER | PERCENT | |
| Total Number | 348 | 100.00 |
| Uncovered | 8 | 2.30 |
| Success | 340 | 97.70 |
| Failure | 0 | 0.00 |
| Incomplete | 1 | 0.29 |
| Without Attempts | 0 | 0.00 |
| NUMBER | PERCENT | |
| Total Number | 10 | 100.00 |
| Uncovered | 0 | 0.00 |
| All Matches | 10 | 100.00 |
| First Matches | 10 | 100.00 |
| ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
| tb.dut.u_reg.u_wake_events_cdc.BusySrcReqChk_A | 0 | 0 | 1916280 | 0 | 0 | 0 | |
| tb.dut.u_reg.u_wake_events_cdc.SrcAckBusyChk_A | 0 | 0 | 1916280 | 0 | 0 | 0 | |
| tb.dut.u_reg.u_wake_events_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A | 0 | 0 | 20981 | 0 | 0 | 175 | |
| tb.dut.u_reg.u_wake_events_cdc.u_arb.gen_wr_req.HwIdSelCheck_A | 0 | 0 | 20981 | 0 | 0 | 0 | |
| tb.dut.u_reg.u_wake_events_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq | 0 | 0 | 1916280 | 0 | 0 | 0 | |
| tb.dut.u_reg.u_wake_events_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq | 0 | 0 | 20981 | 0 | 0 | 0 | |
| tb.dut.u_reg.u_wake_events_cdc.u_src_to_dst_req.DstPulseCheck_A | 0 | 0 | 20981 | 0 | 0 | 0 | |
| tb.dut.u_reg.u_wake_events_cdc.u_src_to_dst_req.SrcPulseCheck_M | 0 | 0 | 1916280 | 0 | 0 | 0 |
| ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
| tb.dut.u_reg.u_wake_events_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A | 0 | 0 | 20981 | 0 | 0 | 175 |
| COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
| tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 1916280 | 6657 | 6657 | 0 | |
| tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 1916280 | 454 | 454 | 0 | |
| tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 1916280 | 557 | 557 | 0 | |
| tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 1916280 | 346 | 346 | 0 | |
| tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 1916280 | 255 | 255 | 0 | |
| tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 1916280 | 281 | 281 | 0 | |
| tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 1916280 | 260 | 260 | 0 | |
| tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 1916280 | 4529 | 4529 | 0 | |
| tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 1916280 | 8336 | 8336 | 0 | |
| tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 1916280 | 16861 | 16861 | 155 |
| COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
| tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 1916280 | 6657 | 6657 | 0 | |
| tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 1916280 | 454 | 454 | 0 | |
| tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 1916280 | 557 | 557 | 0 | |
| tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 1916280 | 346 | 346 | 0 | |
| tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 1916280 | 255 | 255 | 0 | |
| tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 1916280 | 281 | 281 | 0 | |
| tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 1916280 | 260 | 260 | 0 | |
| tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 1916280 | 4529 | 4529 | 0 | |
| tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 1916280 | 8336 | 8336 | 0 | |
| tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 1916280 | 16861 | 16861 | 155 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |