Total Groups Coverage Summary 

COVERED	EXPECTED	SCORE	COVERED	EXPECTED	INST SCORE	WEIGHT
534	555	96.22	534	555	96.22	1

Total groups in report: 12

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NAME	COVERED	EXPECTED	SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING	COMMENT
tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if::prim_onehot_check_without_addr_fault_if_proxy::onehot_without_addr_fault_cg	0	2	0.00	0.00	1	100	1	1	64	64
tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=16}	1	16	6.25	6.25	1	100	1	1	64	64
tl_agent_pkg::pending_req_on_rst_cg	1	2	50.00	50.00	1	100	1	1	64	64
cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg	12	15	80.00	100.00	1	100	1	1	64	64
alert_esc_agent_pkg::alert_handshake_complete_cg	3	3	100.00	100.00	1	100	1	1	64	64
cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}	94	94	100.00		1	100	1	0	64	64
cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}	94	94	100.00		1	100	1	0	64	64
cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}	132	132	100.00		1	100	1	0	64	64
cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg	14	14	100.00	100.00	1	100	1	1	64	64
cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg	24	24	100.00	100.00	1	100	1	1	64	64
dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg	4	4	100.00	89.29	1	100	1	1	64	64
tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}	137	137	100.00	100.00	1	100	1	1	64	64