Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	362	1		T1	5		T3	8		T7	5
all_pins[1]	362	1		T1	5		T3	8		T7	5
all_pins[2]	362	1		T1	5		T3	8		T7	5
all_pins[3]	362	1		T1	5		T3	8		T7	5
all_pins[4]	362	1		T1	5		T3	8		T7	5
all_pins[5]	362	1		T1	5		T3	8		T7	5
all_pins[6]	362	1		T1	5		T3	8		T7	5
all_pins[7]	362	1		T1	5		T3	8		T7	5
all_pins[8]	362	1		T1	5		T3	8		T7	5
all_pins[9]	362	1		T1	5		T3	8		T7	5
all_pins[10]	362	1		T1	5		T3	8		T7	5
all_pins[11]	362	1		T1	5		T3	8		T7	5
all_pins[12]	362	1		T1	5		T3	8		T7	5
all_pins[13]	362	1		T1	5		T3	8		T7	5
all_pins[14]	362	1		T1	5		T3	8		T7	5
all_pins[15]	362	1		T1	5		T3	8		T7	5
all_pins[16]	362	1		T1	5		T3	8		T7	5
all_pins[17]	362	1		T1	5		T3	8		T7	5

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	5352	1		T1	65		T3	119		T7	64
values[0x1]	1164	1		T1	25		T3	25		T7	26
transitions[0x0=>0x1]	856	1		T1	17		T3	19		T7	21
transitions[0x1=>0x0]	869	1		T1	18		T3	19		T7	22

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	297	1		T1	4		T3	7		T7	3
all_pins[0]	values[0x1]	65	1		T1	1		T3	1		T7	2
all_pins[0]	transitions[0x0=>0x1]	51	1		T1	1		T3	1		T7	2
all_pins[0]	transitions[0x1=>0x0]	42	1		T3	2		T7	1		T14	2
all_pins[1]	values[0x0]	306	1		T1	5		T3	6		T7	4
all_pins[1]	values[0x1]	56	1		T3	2		T7	1		T14	2
all_pins[1]	transitions[0x0=>0x1]	45	1		T3	2		T14	2		T60	2
all_pins[1]	transitions[0x1=>0x0]	66	1		T1	3		T3	2		T7	2
all_pins[2]	values[0x0]	285	1		T1	2		T3	6		T7	2
all_pins[2]	values[0x1]	77	1		T1	3		T3	2		T7	3
all_pins[2]	transitions[0x0=>0x1]	55	1		T1	2		T3	2		T7	2
all_pins[2]	transitions[0x1=>0x0]	42	1		T3	1		T14	2		T61	3
all_pins[3]	values[0x0]	298	1		T1	4		T3	7		T7	4
all_pins[3]	values[0x1]	64	1		T1	1		T3	1		T7	1
all_pins[3]	transitions[0x0=>0x1]	46	1		T3	1		T61	3		T69	1
all_pins[3]	transitions[0x1=>0x0]	37	1		T1	2		T3	1		T14	2
all_pins[4]	values[0x0]	307	1		T1	2		T3	7		T7	4
all_pins[4]	values[0x1]	55	1		T1	3		T3	1		T7	1
all_pins[4]	transitions[0x0=>0x1]	37	1		T1	2		T3	1		T7	1
all_pins[4]	transitions[0x1=>0x0]	48	1		T7	2		T14	1		T64	1
all_pins[5]	values[0x0]	296	1		T1	4		T3	8		T7	3
all_pins[5]	values[0x1]	66	1		T1	1		T7	2		T14	1
all_pins[5]	transitions[0x0=>0x1]	46	1		T1	1		T7	2		T60	2
all_pins[5]	transitions[0x1=>0x0]	55	1		T3	3		T14	4		T61	2
all_pins[6]	values[0x0]	287	1		T1	5		T3	5		T7	5
all_pins[6]	values[0x1]	75	1		T3	3		T14	5		T61	2
all_pins[6]	transitions[0x0=>0x1]	62	1		T3	2		T14	4		T61	1
all_pins[6]	transitions[0x1=>0x0]	44	1		T1	2		T7	1		T14	1
all_pins[7]	values[0x0]	305	1		T1	3		T3	7		T7	4
all_pins[7]	values[0x1]	57	1		T1	2		T3	1		T7	1
all_pins[7]	transitions[0x0=>0x1]	45	1		T1	1		T3	1		T14	2
all_pins[7]	transitions[0x1=>0x0]	46	1		T3	2		T7	1		T69	2
all_pins[8]	values[0x0]	304	1		T1	4		T3	6		T7	3
all_pins[8]	values[0x1]	58	1		T1	1		T3	2		T7	2
all_pins[8]	transitions[0x0=>0x1]	42	1		T3	1		T7	2		T69	1
all_pins[8]	transitions[0x1=>0x0]	55	1		T1	3		T3	2		T14	1
all_pins[9]	values[0x0]	291	1		T1	1		T3	5		T7	5
all_pins[9]	values[0x1]	71	1		T1	4		T3	3		T14	1
all_pins[9]	transitions[0x0=>0x1]	55	1		T1	4		T3	1		T60	4
all_pins[9]	transitions[0x1=>0x0]	55	1		T3	1		T7	2		T14	1
all_pins[10]	values[0x0]	291	1		T1	5		T3	5		T7	3
all_pins[10]	values[0x1]	71	1		T3	3		T7	2		T14	2
all_pins[10]	transitions[0x0=>0x1]	45	1		T3	2		T7	2		T14	1
all_pins[10]	transitions[0x1=>0x0]	53	1		T1	3		T3	2		T14	1
all_pins[11]	values[0x0]	283	1		T1	2		T3	5		T7	5
all_pins[11]	values[0x1]	79	1		T1	3		T3	3		T14	2
all_pins[11]	transitions[0x0=>0x1]	51	1		T1	3		T3	2		T14	2
all_pins[11]	transitions[0x1=>0x0]	48	1		T7	3		T14	1		T69	1
all_pins[12]	values[0x0]	286	1		T1	5		T3	7		T7	2
all_pins[12]	values[0x1]	76	1		T3	1		T7	3		T14	1
all_pins[12]	transitions[0x0=>0x1]	54	1		T3	1		T7	3		T69	2
all_pins[12]	transitions[0x1=>0x0]	41	1		T3	1		T7	1		T14	1
all_pins[13]	values[0x0]	299	1		T1	5		T3	7		T7	4
all_pins[13]	values[0x1]	63	1		T3	1		T7	1		T14	2
all_pins[13]	transitions[0x0=>0x1]	45	1		T3	1		T7	1		T14	1
all_pins[13]	transitions[0x1=>0x0]	55	1		T1	1		T7	2		T14	1
all_pins[14]	values[0x0]	289	1		T1	4		T3	8		T7	3
all_pins[14]	values[0x1]	73	1		T1	1		T7	2		T14	2
all_pins[14]	transitions[0x0=>0x1]	62	1		T1	1		T7	2		T14	2
all_pins[14]	transitions[0x1=>0x0]	38	1		T1	2		T7	1		T14	4
all_pins[15]	values[0x0]	313	1		T1	3		T3	8		T7	4
all_pins[15]	values[0x1]	49	1		T1	2		T7	1		T14	4
all_pins[15]	transitions[0x0=>0x1]	41	1		T7	1		T14	4		T71	3
all_pins[15]	transitions[0x1=>0x0]	50	1		T3	1		T7	3		T14	2
all_pins[16]	values[0x0]	304	1		T1	3		T3	7		T7	2
all_pins[16]	values[0x1]	58	1		T1	2		T3	1		T7	3
all_pins[16]	transitions[0x0=>0x1]	47	1		T1	2		T3	1		T7	3
all_pins[16]	transitions[0x1=>0x0]	40	1		T1	1		T7	1		T60	1
all_pins[17]	values[0x0]	311	1		T1	4		T3	8		T7	4
all_pins[17]	values[0x1]	51	1		T1	1		T7	1		T14	1
all_pins[17]	transitions[0x0=>0x1]	27	1		T60	1		T64	2		T71	1
all_pins[17]	transitions[0x1=>0x0]	54	1		T1	1		T3	1		T7	2