Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	272	1		T1	4		T3	7		T7	4
all_values[1]	272	1		T1	4		T3	7		T7	4
all_values[2]	272	1		T1	4		T3	7		T7	4
all_values[3]	272	1		T1	4		T3	7		T7	4
all_values[4]	272	1		T1	4		T3	7		T7	4
all_values[5]	272	1		T1	4		T3	7		T7	4
all_values[6]	272	1		T1	4		T3	7		T7	4
all_values[7]	272	1		T1	4		T3	7		T7	4
all_values[8]	272	1		T1	4		T3	7		T7	4
all_values[9]	272	1		T1	4		T3	7		T7	4
all_values[10]	272	1		T1	4		T3	7		T7	4
all_values[11]	272	1		T1	4		T3	7		T7	4
all_values[12]	272	1		T1	4		T3	7		T7	4
all_values[13]	272	1		T1	4		T3	7		T7	4
all_values[14]	272	1		T1	4		T3	7		T7	4
all_values[15]	272	1		T1	4		T3	7		T7	4
all_values[16]	272	1		T1	4		T3	7		T7	4
all_values[17]	272	1		T1	4		T3	7		T7	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2526	1		T1	27		T3	62		T7	46
auto[1]	2370	1		T1	45		T3	64		T7	26

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	887	1		T1	11		T3	19		T7	17
auto[1]	4009	1		T1	61		T3	107		T7	55

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2900	1		T1	38		T3	77		T7	46
auto[1]	1996	1		T1	34		T3	49		T7	26

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	30	1		T60	1		T64	2		T70	1
all_values[0]	auto[0]	auto[0]	auto[1]	51	1		T1	1		T7	1		T14	1
all_values[0]	auto[0]	auto[1]	auto[0]	20	1		T3	3		T65	3		T72	1
all_values[0]	auto[0]	auto[1]	auto[1]	51	1		T3	2		T14	3		T61	1
all_values[0]	auto[1]	auto[0]	auto[1]	66	1		T1	2		T7	1		T14	3
all_values[0]	auto[1]	auto[1]	auto[1]	54	1		T1	1		T3	2		T7	2
all_values[1]	auto[0]	auto[0]	auto[0]	30	1		T61	1		T67	1		T73	1
all_values[1]	auto[0]	auto[0]	auto[1]	61	1		T1	2		T3	2		T14	3
all_values[1]	auto[0]	auto[1]	auto[0]	17	1		T1	1		T66	1		T67	2
all_values[1]	auto[0]	auto[1]	auto[1]	51	1		T3	1		T7	2		T60	1
all_values[1]	auto[1]	auto[0]	auto[1]	66	1		T1	1		T3	3		T7	1
all_values[1]	auto[1]	auto[1]	auto[1]	47	1		T3	1		T7	1		T14	2
all_values[2]	auto[0]	auto[0]	auto[0]	30	1		T7	1		T61	2		T68	1
all_values[2]	auto[0]	auto[0]	auto[1]	54	1		T3	2		T14	1		T60	2
all_values[2]	auto[0]	auto[1]	auto[0]	28	1		T60	1		T61	2		T68	1
all_values[2]	auto[0]	auto[1]	auto[1]	49	1		T1	2		T3	2		T7	2
all_values[2]	auto[1]	auto[0]	auto[1]	52	1		T1	1		T14	6		T64	4
all_values[2]	auto[1]	auto[1]	auto[1]	59	1		T1	1		T3	3		T7	1
all_values[3]	auto[0]	auto[0]	auto[0]	27	1		T7	1		T14	2		T61	1
all_values[3]	auto[0]	auto[0]	auto[1]	54	1		T1	1		T3	1		T7	1
all_values[3]	auto[0]	auto[1]	auto[0]	24	1		T3	4		T60	1		T64	1
all_values[3]	auto[0]	auto[1]	auto[1]	59	1		T7	1		T14	3		T60	2
all_values[3]	auto[1]	auto[0]	auto[1]	47	1		T14	1		T68	1		T62	3
all_values[3]	auto[1]	auto[1]	auto[1]	61	1		T1	3		T3	2		T7	1
all_values[4]	auto[0]	auto[0]	auto[0]	23	1		T3	1		T14	1		T61	1
all_values[4]	auto[0]	auto[0]	auto[1]	52	1		T3	1		T7	1		T14	1
all_values[4]	auto[0]	auto[1]	auto[0]	20	1		T1	1		T60	1		T69	1
all_values[4]	auto[0]	auto[1]	auto[1]	65	1		T1	1		T3	1		T7	2
all_values[4]	auto[1]	auto[0]	auto[1]	67	1		T3	2		T7	1		T14	1
all_values[4]	auto[1]	auto[1]	auto[1]	45	1		T1	2		T3	2		T14	3
all_values[5]	auto[0]	auto[0]	auto[0]	30	1		T3	1		T7	2		T68	1
all_values[5]	auto[0]	auto[0]	auto[1]	56	1		T1	1		T3	3		T14	2
all_values[5]	auto[0]	auto[1]	auto[0]	15	1		T60	1		T66	1		T67	1
all_values[5]	auto[0]	auto[1]	auto[1]	52	1		T3	1		T7	1		T14	3
all_values[5]	auto[1]	auto[0]	auto[1]	68	1		T3	2		T7	1		T14	1
all_values[5]	auto[1]	auto[1]	auto[1]	51	1		T1	3		T14	1		T60	1
all_values[6]	auto[0]	auto[0]	auto[0]	23	1		T1	1		T7	2		T60	4
all_values[6]	auto[0]	auto[0]	auto[1]	67	1		T1	1		T3	2		T7	1
all_values[6]	auto[0]	auto[1]	auto[0]	17	1		T68	1		T66	3		T74	1
all_values[6]	auto[0]	auto[1]	auto[1]	62	1		T1	1		T3	1		T14	3
all_values[6]	auto[1]	auto[0]	auto[1]	56	1		T1	1		T3	3		T7	1
all_values[6]	auto[1]	auto[1]	auto[1]	47	1		T3	1		T14	2		T61	1
all_values[7]	auto[0]	auto[0]	auto[0]	39	1		T3	3		T7	1		T61	1
all_values[7]	auto[0]	auto[0]	auto[1]	55	1		T7	1		T14	4		T60	2
all_values[7]	auto[0]	auto[1]	auto[0]	25	1		T14	1		T69	1		T64	1
all_values[7]	auto[0]	auto[1]	auto[1]	49	1		T1	1		T3	2		T7	1
all_values[7]	auto[1]	auto[0]	auto[1]	52	1		T1	1		T3	1		T60	2
all_values[7]	auto[1]	auto[1]	auto[1]	52	1		T1	2		T3	1		T7	1
all_values[8]	auto[0]	auto[0]	auto[0]	21	1		T7	1		T14	1		T68	1
all_values[8]	auto[0]	auto[0]	auto[1]	64	1		T3	2		T14	2		T60	1
all_values[8]	auto[0]	auto[1]	auto[0]	21	1		T1	1		T69	1		T64	2
all_values[8]	auto[0]	auto[1]	auto[1]	46	1		T1	1		T3	3		T7	1
all_values[8]	auto[1]	auto[0]	auto[1]	55	1		T1	2		T14	2		T60	3
all_values[8]	auto[1]	auto[1]	auto[1]	65	1		T3	2		T7	2		T69	2
all_values[9]	auto[0]	auto[0]	auto[0]	23	1		T61	1		T64	1		T71	1
all_values[9]	auto[0]	auto[0]	auto[1]	55	1		T3	1		T7	2		T69	1
all_values[9]	auto[0]	auto[1]	auto[0]	20	1		T14	2		T68	1		T71	1
all_values[9]	auto[0]	auto[1]	auto[1]	64	1		T1	3		T3	2		T14	3
all_values[9]	auto[1]	auto[0]	auto[1]	55	1		T7	2		T61	1		T69	1
all_values[9]	auto[1]	auto[1]	auto[1]	55	1		T1	1		T3	4		T14	2
all_values[10]	auto[0]	auto[0]	auto[0]	30	1		T1	3		T7	1		T60	1
all_values[10]	auto[0]	auto[0]	auto[1]	50	1		T3	1		T7	1		T14	2
all_values[10]	auto[0]	auto[1]	auto[0]	16	1		T1	1		T14	1		T64	2
all_values[10]	auto[0]	auto[1]	auto[1]	55	1		T3	3		T7	1		T14	2
all_values[10]	auto[1]	auto[0]	auto[1]	66	1		T3	1		T7	1		T60	1
all_values[10]	auto[1]	auto[1]	auto[1]	55	1		T3	2		T14	2		T69	3
all_values[11]	auto[0]	auto[0]	auto[0]	26	1		T7	4		T60	2		T61	1
all_values[11]	auto[0]	auto[0]	auto[1]	47	1		T3	1		T14	4		T69	1
all_values[11]	auto[0]	auto[1]	auto[0]	13	1		T61	1		T68	2		T64	2
all_values[11]	auto[0]	auto[1]	auto[1]	67	1		T1	2		T3	1		T14	1
all_values[11]	auto[1]	auto[0]	auto[1]	57	1		T1	1		T3	5		T69	2
all_values[11]	auto[1]	auto[1]	auto[1]	62	1		T1	1		T14	2		T60	1
all_values[12]	auto[0]	auto[0]	auto[0]	24	1		T61	2		T66	2		T70	1
all_values[12]	auto[0]	auto[0]	auto[1]	50	1		T1	1		T3	2		T7	2
all_values[12]	auto[0]	auto[1]	auto[0]	24	1		T1	2		T3	1		T61	2
all_values[12]	auto[0]	auto[1]	auto[1]	58	1		T3	2		T7	1		T14	1
all_values[12]	auto[1]	auto[0]	auto[1]	60	1		T3	1		T7	1		T14	2
all_values[12]	auto[1]	auto[1]	auto[1]	56	1		T1	1		T3	1		T14	1
all_values[13]	auto[0]	auto[0]	auto[0]	36	1		T1	1		T7	1		T60	2
all_values[13]	auto[0]	auto[0]	auto[1]	50	1		T1	1		T3	3		T7	1
all_values[13]	auto[0]	auto[1]	auto[0]	24	1		T14	1		T60	2		T69	3
all_values[13]	auto[0]	auto[1]	auto[1]	54	1		T3	1		T14	3		T61	2
all_values[13]	auto[1]	auto[0]	auto[1]	55	1		T1	2		T3	3		T61	1
all_values[13]	auto[1]	auto[1]	auto[1]	53	1		T7	2		T14	3		T68	2
all_values[14]	auto[0]	auto[0]	auto[0]	30	1		T7	2		T60	1		T71	1
all_values[14]	auto[0]	auto[0]	auto[1]	56	1		T1	1		T3	2		T14	5
all_values[14]	auto[0]	auto[1]	auto[0]	18	1		T3	2		T68	2		T71	1
all_values[14]	auto[0]	auto[1]	auto[1]	55	1		T3	1		T7	1		T14	1
all_values[14]	auto[1]	auto[0]	auto[1]	51	1		T1	1		T3	1		T7	1
all_values[14]	auto[1]	auto[1]	auto[1]	62	1		T1	2		T3	1		T60	1
all_values[15]	auto[0]	auto[0]	auto[0]	28	1		T3	2		T69	1		T64	4
all_values[15]	auto[0]	auto[0]	auto[1]	48	1		T3	1		T7	1		T61	2
all_values[15]	auto[0]	auto[1]	auto[0]	32	1		T3	2		T60	4		T69	3
all_values[15]	auto[0]	auto[1]	auto[1]	62	1		T1	2		T14	4		T68	1
all_values[15]	auto[1]	auto[0]	auto[1]	60	1		T7	3		T61	2		T68	1
all_values[15]	auto[1]	auto[1]	auto[1]	42	1		T1	2		T3	2		T14	3
all_values[16]	auto[0]	auto[0]	auto[0]	24	1		T7	1		T70	3		T75	2
all_values[16]	auto[0]	auto[0]	auto[1]	51	1		T3	2		T14	1		T69	2
all_values[16]	auto[0]	auto[1]	auto[0]	29	1		T60	4		T68	4		T70	1
all_values[16]	auto[0]	auto[1]	auto[1]	70	1		T1	2		T3	3		T7	1
all_values[16]	auto[1]	auto[0]	auto[1]	48	1		T1	1		T3	2		T14	3
all_values[16]	auto[1]	auto[1]	auto[1]	50	1		T1	1		T7	2		T14	1
all_values[17]	auto[0]	auto[0]	auto[0]	26	1		T69	2		T64	1		T71	2
all_values[17]	auto[0]	auto[0]	auto[1]	66	1		T3	4		T7	3		T14	3
all_values[17]	auto[0]	auto[1]	auto[0]	24	1		T14	1		T69	2		T71	1
all_values[17]	auto[0]	auto[1]	auto[1]	57	1		T1	3		T3	2		T60	1
all_values[17]	auto[1]	auto[0]	auto[1]	58	1		T3	1		T7	1		T14	2
all_values[17]	auto[1]	auto[1]	auto[1]	41	1		T1	1		T14	1		T60	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal