USBDEV Simulation Results

Monday June 10 2024 23:28:43 UTC

GitHub Revision: `a8c9c17a8c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 72227341233107832543509484606850665418885932500709631655793413524197290927900

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	usbdev_smoke	1.060s	265.678us	50	50	100.00
V1	csr_hw_reset	usbdev_csr_hw_reset	1.060s	164.580us	5	5	100.00
V1	csr_rw	usbdev_csr_rw	1.150s	96.307us	20	20	100.00
V1	csr_bit_bash	usbdev_csr_bit_bash	8.690s	2.257ms	5	5	100.00
V1	csr_aliasing	usbdev_csr_aliasing	3.400s	127.832us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	usbdev_csr_mem_rw_with_rand_reset	2.730s	107.358us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	usbdev_csr_rw	1.150s	96.307us	20	20	100.00
		usbdev_csr_aliasing	3.400s	127.832us	5	5	100.00
V1	mem_walk	usbdev_mem_walk	4.910s	708.310us	5	5	100.00
V1	mem_partial_access	usbdev_mem_partial_access	2.270s	176.464us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	in_trans	usbdev_in_trans	1.030s	221.701us	50	50	100.00
V2	data_toggle_clear	data_toggle_clear			0	0	--
V2	phy_pins_sense	usbdev_phy_pins_sense	0.750s	45.586us	50	50	100.00
V2	av_buffer	usbdev_av_buffer	0.920s	198.278us	50	50	100.00
V2	rx_fifo	rx_fifo			0	0	--
V2	phy_config_tx_osc_test_mode	phy_config_tx_osc_test_mode			0	0	--
V2	phy_config_eop_single_bit_handling	usbdev_phy_config_eop_single_bit_handling	1.000s	237.483us	50	50	100.00
V2	phy_config_pinflip	phy_config_pinflip			0	0	--
V2	phy_config_usb_ref_disable	usbdev_phy_config_usb_ref_disable	0.950s	167.685us	50	50	100.00
V2	max_length_out_transaction	usbdev_max_length_out_transaction	1.010s	195.574us	50	50	100.00
V2	max_length_in_transaction	max_length_in_transaction			0	0	--
V2	min_length_out_transaction	usbdev_min_length_out_transaction	0.900s	197.721us	50	50	100.00
V2	min_length_in_transaction	min_length_in_transaction			0	0	--
V2	random_length_out_trans	usbdev_random_length_out_trans	0.960s	237.852us	50	50	100.00
V2	random_length_in_trans	random_length_in_trans			0	0	--
V2	out_stall	usbdev_out_stall	0.970s	217.272us	50	50	100.00
V2	in_stall	usbdev_in_stall	0.860s	188.220us	50	50	100.00
V2	out_iso	out_iso			0	0	--
V2	in_iso	usbdev_in_iso	1.050s	288.800us	50	50	100.00
V2	pkt_received	usbdev_pkt_received	0.950s	199.419us	50	50	100.00
V2	pkt_sent	usbdev_pkt_sent	0.980s	272.484us	50	50	100.00
V2	disconnected	usbdev_disconnected	0.870s	138.072us	50	50	100.00
V2	host_lost	host_lost			0	0	--
V2	link_reset	link_reset			0	0	--
V2	link_suspend	usbdev_link_suspend	4.940s	3.302ms	50	50	100.00
V2	link_resume	link_resume			0	0	--
V2	av_empty	av_empty			0	0	--
V2	rx_full	rx_full			0	0	--
V2	av_overflow	av_overflow			0	0	--
V2	link_in_err	usbdev_link_in_err	1.000s	287.993us	50	50	100.00
V2	rx_crc_err	usbdev_rx_crc_err	0.850s	166.304us	50	50	100.00
V2	rx_pid_err	rx_pid_err			0	0	--
V2	rx_bitstuff_err	usbdev_bitstuff_err	0.930s	219.386us	50	50	100.00
V2	link_out_err	link_out_err			0	0	--
V2	enable	usbdev_enable	0.750s	82.203us	50	50	100.00
V2	resume_link_active	resume_link_active			0	0	--
V2	device_address	device_address			0	0	--
V2	invalid_data1_data0_toggle_test	invalid_data1_data0_toggle_test			0	0	--
V2	setup_stage	usbdev_setup_stage	0.900s	195.975us	50	50	100.00
V2	endpoint_access	usbdev_endpoint_access	2.650s	923.993us	50	50	100.00
V2	disable_endpoint	disable_endpoint			0	0	--
V2	out_trans_nak	usbdev_out_trans_nak	0.940s	219.524us	50	50	100.00
V2	setup_trans_ignored	usbdev_setup_trans_ignored	0.900s	173.330us	50	50	100.00
V2	nak_trans	usbdev_nak_trans	0.980s	271.022us	50	50	100.00
V2	stall_trans	usbdev_stall_trans	0.940s	226.692us	50	50	100.00
V2	setup_priority_over_stall_response	setup_priority_over_stall_response			0	0	--
V2	stall_priority_over_nak	usbdev_stall_priority_over_nak	0.910s	183.162us	50	50	100.00
V2	pending_in_trans	usbdev_pending_in_trans	0.940s	205.070us	50	50	100.00
V2	streaming_test	usbdev_streaming_out	6.929m	14.411ms	50	50	100.00
V2	max_clock_error_untracked	max_clock_error_untracked			0	0	--
V2	max_clock_error_tracking	max_clock_error_tracking			0	0	--
V2	max_phase_error	max_phase_error			0	0	--
V2	min_inter_pkt_delay	min_inter_pkt_delay			0	0	--
V2	max_inter_pkt_delay	max_inter_pkt_delay			0	0	--
V2	device_timeout_missing_host_handshake	device_timeout_missing_host_handshake			0	0	--
V2	device_timeout	device_timeout			0	0	--
V2	packet_buffer	usbdev_pkt_buffer	54.370s	24.040ms	50	50	100.00
V2	nak_to_out_trans_when_avbuffer_empty_rxfifo_full	nak_to_out_trans_when_avbuffer_empty_rxfifo_full			0	0	--
V2	aon_wake_resume	usbdev_aon_wake_resume	31.370s	23.338ms	50	50	100.00
V2	aon_wake_reset	usbdev_aon_wake_reset	16.570s	13.417ms	50	50	100.00
V2	aon_wake_disconnect	usbdev_aon_wake_disconnect	6.060s	3.945ms	50	50	100.00
V2	invalid_sync	invalid_sync			0	0	--
V2	spurious_tokens_ignored	spurious_tokens_ignored			0	0	--
V2	low_speed_traffic	low_speed_traffic			0	0	--
V2	rand_bus_resets	rand_bus_resets			0	0	--
V2	rand_disconnects	rand_disconnects			0	0	--
V2	max_usb_traffic	max_usb_traffic			0	0	--
V2	stress_usb_traffic	stress_usb_traffic			0	0	--
V2	in_packet_retraction	in_packet_retraction			0	0	--
V2	data_toggle_restore	usbdev_data_toggle_restore	3.970s	1.757ms	50	50	100.00
V2	setup_priority	setup_priority			0	0	--
V2	fifo_resets	usbdev_fifo_rst	2.490s	312.030us	50	50	100.00
V2	intr_test	usbdev_intr_test	0.790s	48.933us	50	50	100.00
V2	alert_test	usbdev_alert_test			0	0	--
V2	tl_d_oob_addr_access	usbdev_tl_errors	3.810s	324.417us	20	20	100.00
V2	tl_d_illegal_access	usbdev_tl_errors	3.810s	324.417us	20	20	100.00
V2	tl_d_outstanding_access	usbdev_csr_hw_reset	1.060s	164.580us	5	5	100.00
		usbdev_csr_rw	1.150s	96.307us	20	20	100.00
		usbdev_csr_aliasing	3.400s	127.832us	5	5	100.00
		usbdev_same_csr_outstanding	2.070s	213.159us	20	20	100.00
V2	tl_d_partial_access	usbdev_csr_hw_reset	1.060s	164.580us	5	5	100.00
		usbdev_csr_rw	1.150s	96.307us	20	20	100.00
		usbdev_csr_aliasing	3.400s	127.832us	5	5	100.00
		usbdev_same_csr_outstanding	2.070s	213.159us	20	20	100.00
V2		TOTAL			1790	1790	100.00
V2S	tl_intg_err	usbdev_sec_cm	2.020s	1.064ms	5	5	100.00
		usbdev_tl_intg_err	6.050s	2.169ms	20	20	100.00
V2S	sec_cm_bus_integrity	usbdev_tl_intg_err	6.050s	2.169ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
	Unmapped tests	usbdev_dpi_config_host	44.290s	5.134ms	1	1	100.00
		usbdev_max_usb_traffic	7.263m	15.322ms	50	50	100.00
		usbdev_out_iso	0.950s	267.772us	50	50	100.00
		usbdev_rand_bus_disconnects	12.541m	30.993ms	10	10	100.00
		usbdev_rand_bus_resets	7.211m	15.695ms	10	10	100.00
		usbdev_rand_suspends	15.787m	39.049ms	10	10	100.00
		usbdev_stress_usb_traffic	10.159m	22.311ms	5	5	100.00
		random_length_in_trans	1.080s	249.303us	49	50	98.00
		min_length_in_transaction	0.950s	228.736us	50	50	100.00
		max_length_in_transaction	1.060s	286.092us	50	50	100.00
		usbdev_stress_all_with_rand_reset	0.700s	38.587us	0	50	0.00
		usbdev_stress_all	0.660s		0	50	0.00
		TOTAL			2066	2166	95.38

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	9	9	7	77.78
V1	8	8	8	100.00
V2	76	37	37	48.68
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.36	97.48	92.33	97.44	68.75	95.77	98.17	96.58

Failure Buckets

UVM_WARNING [BDTYP] Cannot create an object of type 'usbdev_stress_all_vseq' because it is not registered with the factory.

has 100 failures:

Test usbdev_stress_all_with_rand_reset has 50 failures.

0.usbdev_stress_all_with_rand_reset.55383045568866490209945875173208570774958001239033910203508846075458609505789
Line 251, in log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @  15360676 ps: [BDTYP] Cannot create an object of type 'usbdev_stress_all_vseq' because it is not registered with the factory.
  UVM_INFO @  15360676 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

1.usbdev_stress_all_with_rand_reset.105866279934931647362173862972232783719025271363461677174078417585159512034678
Line 251, in log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/1.usbdev_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @  19049803 ps: [BDTYP] Cannot create an object of type 'usbdev_stress_all_vseq' because it is not registered with the factory.
  UVM_INFO @  19049803 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

... and 48 more failures.

Test usbdev_stress_all has 50 failures.

0.usbdev_stress_all.52898358841482151805446752281612493643736497666493489801158606705285553719548
Line 251, in log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_stress_all/latest/run.log

  UVM_WARNING @         0 ps: [BDTYP] Cannot create an object of type 'usbdev_stress_all_vseq' because it is not registered with the factory.
  UVM_INFO @         0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

1.usbdev_stress_all.40079799326949498211729790025059274132099328825077972019455150969084124873706
Line 251, in log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/1.usbdev_stress_all/latest/run.log

  UVM_WARNING @         0 ps: [BDTYP] Cannot create an object of type 'usbdev_stress_all_vseq' because it is not registered with the factory.
  UVM_INFO @         0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

... and 48 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test random_length_in_trans has 1 failures.

37.random_length_in_trans.91637433231703840223943787122572787636104082189049574869015392196956569040050
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/37.random_length_in_trans/latest/run.log

  [make]: simulate
  cd /workspace/37.random_length_in_trans/latest && /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4551858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.random_length_in_trans.4551858
  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Jun 10 17:28 2024
  Cannot find license file.
  Make sure that you have a license file and that your
  LM_LICENSE_FILE is pointing to the right location.
  
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 255