USBDEV Simulation Results

Tuesday June 11 2024 19:02:38 UTC

GitHub Revision: dd5ad5fb77

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 66418170746903624595625818392428707033482455256751560525176982524210226376736

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 1.020s 311.566us 50 50 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 0.900s 86.443us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.160s 146.593us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 11.360s 1.806ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.030s 140.373us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.830s 115.726us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.160s 146.593us 20 20 100.00
usbdev_csr_aliasing 3.030s 140.373us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.710s 708.439us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.150s 101.930us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 in_trans usbdev_in_trans 1.080s 243.773us 50 50 100.00
V2 data_toggle_clear data_toggle_clear 0 0 --
V2 phy_pins_sense usbdev_phy_pins_sense 0.730s 68.419us 50 50 100.00
V2 av_buffer usbdev_av_buffer 0.900s 197.233us 50 50 100.00
V2 rx_fifo usbdev_pkt_buffer 48.090s 21.794ms 50 50 100.00
V2 phy_config_tx_osc_test_mode phy_config_tx_osc_test_mode 0 0 --
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 0.990s 171.052us 50 50 100.00
V2 phy_config_pinflip phy_config_pinflip 0 0 --
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 0.860s 154.812us 50 50 100.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 0.930s 231.357us 50 50 100.00
V2 max_length_in_transaction usbdev_max_length_in_transaction 1.050s 237.893us 50 50 100.00
V2 min_length_out_transaction usbdev_min_length_out_transaction 0.870s 179.965us 50 50 100.00
V2 min_length_in_transaction usbdev_min_length_in_transaction 0.860s 219.958us 50 50 100.00
V2 random_length_out_transaction usbdev_random_length_out_transaction 0.940s 191.757us 50 50 100.00
V2 random_length_in_transaction usbdev_random_length_in_transaction 1.010s 221.292us 50 50 100.00
V2 out_stall usbdev_out_stall 0.970s 174.494us 50 50 100.00
V2 in_stall usbdev_in_stall 0.850s 190.440us 50 50 100.00
V2 out_iso usbdev_out_iso 0.940s 188.191us 50 50 100.00
V2 in_iso usbdev_in_iso 1.020s 222.303us 50 50 100.00
V2 pkt_received usbdev_pkt_received 0.930s 187.608us 50 50 100.00
V2 pkt_sent usbdev_pkt_sent 1.010s 311.005us 50 50 100.00
V2 disconnected usbdev_disconnected 0.850s 209.945us 50 50 100.00
V2 host_lost host_lost 0 0 --
V2 link_reset link_reset 0 0 --
V2 link_suspend usbdev_link_suspend 4.960s 3.336ms 50 50 100.00
V2 link_resume link_resume 0 0 --
V2 av_empty av_empty 0 0 --
V2 rx_full rx_full 0 0 --
V2 av_overflow av_overflow 0 0 --
V2 link_in_err usbdev_link_in_err 0.970s 245.130us 50 50 100.00
V2 rx_crc_err usbdev_rx_crc_err 0.830s 177.578us 50 50 100.00
V2 rx_pid_err rx_pid_err 0 0 --
V2 rx_bitstuff_err usbdev_bitstuff_err 0.890s 236.753us 50 50 100.00
V2 link_out_err link_out_err 0 0 --
V2 enable usbdev_enable 0.740s 59.705us 50 50 100.00
V2 resume_link_active resume_link_active 0 0 --
V2 device_address device_address 0 0 --
V2 invalid_data1_data0_toggle_test invalid_data1_data0_toggle_test 0 0 --
V2 setup_stage usbdev_setup_stage 0.860s 211.577us 50 50 100.00
V2 endpoint_access usbdev_endpoint_access 2.590s 1.051ms 50 50 100.00
V2 disable_endpoint disable_endpoint 0 0 --
V2 out_trans_nak usbdev_out_trans_nak 0.910s 263.094us 50 50 100.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 0.880s 152.452us 50 50 100.00
V2 nak_trans usbdev_nak_trans 0.970s 230.206us 50 50 100.00
V2 stall_trans usbdev_stall_trans 0.970s 187.045us 50 50 100.00
V2 setup_priority_over_stall_response setup_priority_over_stall_response 0 0 --
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 0.930s 189.276us 50 50 100.00
V2 pending_in_trans usbdev_pending_in_trans 0.860s 160.751us 50 50 100.00
V2 streaming_test usbdev_streaming_out 6.700m 14.407ms 50 50 100.00
V2 max_clock_error_untracked max_clock_error_untracked 0 0 --
V2 max_clock_error_tracking max_clock_error_tracking 0 0 --
V2 max_phase_error max_phase_error 0 0 --
V2 min_inter_pkt_delay min_inter_pkt_delay 0 0 --
V2 max_inter_pkt_delay max_inter_pkt_delay 0 0 --
V2 device_timeout_missing_host_handshake device_timeout_missing_host_handshake 0 0 --
V2 device_timeout device_timeout 0 0 --
V2 packet_buffer usbdev_pkt_buffer 48.090s 21.794ms 50 50 100.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full nak_to_out_trans_when_avbuffer_empty_rxfifo_full 0 0 --
V2 aon_wake_resume usbdev_aon_wake_resume 29.880s 23.315ms 50 50 100.00
V2 aon_wake_reset usbdev_aon_wake_reset 17.120s 13.436ms 50 50 100.00
V2 aon_wake_disconnect usbdev_aon_wake_disconnect 5.820s 4.223ms 50 50 100.00
V2 invalid_sync invalid_sync 0 0 --
V2 spurious_tokens_ignored spurious_tokens_ignored 0 0 --
V2 low_speed_traffic low_speed_traffic 0 0 --
V2 rand_bus_resets usbdev_rand_bus_resets 12.494m 26.547ms 10 10 100.00
V2 rand_disconnects usbdev_rand_bus_disconnects 10.480m 25.771ms 10 10 100.00
V2 max_usb_traffic usbdev_max_usb_traffic 7.199m 15.289ms 50 50 100.00
V2 stress_usb_traffic usbdev_stress_usb_traffic 3.881m 30.535ms 5 5 100.00
V2 in_packet_retraction in_packet_retraction 0 0 --
V2 data_toggle_restore usbdev_data_toggle_restore 3.450s 1.646ms 50 50 100.00
V2 setup_priority setup_priority 0 0 --
V2 fifo_resets usbdev_fifo_rst 2.850s 467.948us 50 50 100.00
V2 intr_test usbdev_intr_test 0.760s 76.574us 50 50 100.00
V2 alert_test usbdev_alert_test 0 0 --
V2 tl_d_oob_addr_access usbdev_tl_errors 3.900s 378.974us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.900s 378.974us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 0.900s 86.443us 5 5 100.00
usbdev_csr_rw 1.160s 146.593us 20 20 100.00
usbdev_csr_aliasing 3.030s 140.373us 5 5 100.00
usbdev_same_csr_outstanding 1.810s 392.711us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 0.900s 86.443us 5 5 100.00
usbdev_csr_rw 1.160s 146.593us 20 20 100.00
usbdev_csr_aliasing 3.030s 140.373us 5 5 100.00
usbdev_same_csr_outstanding 1.810s 392.711us 20 20 100.00
V2 TOTAL 2065 2065 100.00
V2S tl_intg_err usbdev_sec_cm 1.630s 806.065us 5 5 100.00
usbdev_tl_intg_err 5.550s 872.182us 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 5.550s 872.182us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
Unmapped tests usbdev_dpi_config_host 2.071m 5.138ms 1 1 100.00
usbdev_rand_suspends 9.762m 25.313ms 10 10 100.00
usbdev_stress_all_with_rand_reset 0.700s 48.472us 0 50 0.00
usbdev_stress_all 0.650s 0 50 0.00
TOTAL 2216 2316 95.68

Testplan Progress

Items Total Written Passing Progress
N.A. 4 4 2 50.00
V1 8 8 8 100.00
V2 75 45 45 60.00
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
92.36 97.48 92.35 97.44 68.75 95.77 98.17 96.58

Failure Buckets

Past Results